JPH03178096A - Controller for storage device - Google Patents

Abstract

PURPOSE:To make asynchronously and freely access by providing a second competitive control part sending a refresh requiring signal, and a central processor selected by a first competitive control part, and a data buffer to execute the input and output of the data between storage devices. CONSTITUTION:The subject device is provided with the second competitive control part 5b sending the refresh requiring signal at the time of refresh require ment at every prescribed interval from a refresh timer 4 by denying a memory access requirement of the requirement of the competitive decision and the cen tral processor selected by the first competitive control part 5a, and the data buffer 8 to execute the input/output of the data between the memory devices. By the first and the second competitive control parts 5a, 5b, the competitive control of refresh priority and the competitive control of memory access require ment from plural CPUs 1a, 1b are allowed to independently compete and by allowing the refresh requirement to have the priority, the competitive decision of memory access requirement from the plural CPUs 1a, 1b is executed. In such a manner, the controller for the storage device making a DRAM 2 access with asynchronous is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device for a storage device, and particularly to a device for controlling a Dyna main type storage device.

[Conventional technology]

FIG. 2 is a circuit diagram showing a control device for a dynamic storage device (hereinafter referred to as DRAM), which is shown in, for example, "Transistor Technology J (October 1988 issue, pages 404-415). 1) is the central processing unit (
(hereinafter referred to as cpu), (2) is DRAM, (3) is c
pu (1) is an address decoder that selects the required memory according to the address from the address, (4) is a refresh timer that makes a refresh request to refresh DRAM (2) at regular intervals, and (5) is an address decoder (3).
) is a refresh arbiter that arbitrates the conflict between memory access requests from CPU (1) and refresh requests from refresh timer (4), and (6) is
2) a timing generator that creates the control signals necessary for
(7) is an address multiplexer for switching to input the upper and lower addresses of the CPLI (1) to the DRAM (2), and (8) is the CPLI
(1) DR by controlling read/write from
This is a data buffer that controls the output of data from AM (2).

Next, the operation will be explained. CPLI (1) to DR
The address for the access request of AM (2) is manually entered into the address decoder (3), and the address decoder (3)
The memory access request refresh arbiter (5) is output from the memory access request refresh arbiter (5). Next, the refresh arbiter (5) arbitrates a conflict between the refresh request signal from the refresh timer (4) and the memory access request from the address decoder (3). Whichever of the above memory access request signal or refresh request signal is issued earlier is granted first, and if there is a conflict, subsequent requests are allowed until the cycle of the request that was granted first is completed. made to wait.

Next, based on the memory access request signal selected by the refresh arbiter (5) by the timing generator (δ>) and the memory access request signal and refresh request signal selected by the refresh arbiter (5) by the tying generator (6), The timing of the RAS and CAS signals necessary for memory access and refresh is generated by the timing generator (6), and the timing of the DR
AM (2) is input.

Further, for example, the memory access request signal (or refresh request signal) selected by the tying generator (6) is input to the address multiplexer (7), and the row address and column address of the DRAM (2) are time-divided. The address of the CPU (1) for manual processing is switched and input to the DRAM (2). Next, when reading the DRAM (2), the CP
When reading and writing data stored at the address requested by t1 (1), the CPU (1
) writes data to the address requested by At that time, the data buffer (8) uses a bidirectional buffer, and the direction of data (from DRAM (2) to c
pu(1) When writing, from cpu(1) to DRAM
(2) ) controls the buffer.

(Problem to be Solved by the Invention) Since the control device of the conventional dynamic storage device is configured as described above, access by multiple CPUs requires complex CPU control such as refresh control and contention arbitration control. There are problems such as requiring additional processing procedures, interrupts, and circuits, and increasing the scale of the hardware.There are also problems such as the need to have a certain degree of flexibility in the refresh interval. Ta.

This invention was made in order to solve the above-mentioned problems, and it makes the refresh interval constant, gives priority, refreshes in the maximum time, and controls contention in requests from multiple CPUs. The object of the present invention is to obtain a control device for a dynamic storage device that can be freely accessed asynchronously by performing the following steps.

[Means to solve the problem]

A storage device control device according to the present invention is a storage device control device that asynchronously accesses a dynamic storage device shared by a plurality of central processing units.
an address decoder that decodes each memory access request output from each central processing unit; a selector that selects an address from the central processing unit that accesses the storage device; and each central processing unit provided through each of the address decoders. a first contention control unit that performs contention arbitration on memory access requests from a refresh timer and sends a selection control signal to the selector; a second contention control unit that sends a refresh request signal; a timing generator that normally sends a memory access control signal to the storage device and sends a refresh control signal when the refresh request signal is input; an address multiplexer that switches the upper and lower addresses of the central processing unit selected by the contention control unit and sends the same to the storage device; and an address multiplexer that switches the upper and lower addresses of the central processing unit selected by the contention control unit and sends the same to the storage device; It is equipped with a data buffer for inputting and outputting data.

[Effect]

The storage device control device according to the present invention independently competes refresh priority conflict control and memory access request conflict control from a plurality of CPUs by the first and second conflict control units, and also gives priority to refresh requests. have the right,
Competitive arbitration is performed for memory access requests from multiple CPUs.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, (la) and (lb) are the first and second C
PU, (2) is DRAM, (3a) and (3
b) is an address decoder for the first and second CPUs (la) and (1b), (4) is a refresh timer that issues a refresh request to refresh the DRAM (2) at regular intervals, and (5a) is the first and second CPU (la)
The first contention control unit performs contention arbitration based on memory access requests from and (lb), and (5b) is the CPU (la).
and (1b) a second contention control unit that cancels the memory access request resulting from contention arbitration at the time of a refresh request and outputs a refresh request signal; (6) is the DRAM; (2) control signals during necessary refresh and memory access; The timing generator (7) is the first
cpu (l
Address multiplexer (8) switches to input the upper and lower addresses of either address (a) or (lb) to DRAM (2);
The data bus and DRA of the selected one of la) and (1b)
Connect the data bus of M (2) and connect the connected CPU.
(la) or (lb) is a data buffer that controls the output of data from DRAM (2) by controlling reading/writing; (9) is the CPU (la) or (1b) that accesses DRAM (2); This is a selector for selecting an address.

Next, the operation will be explained. CPU (la), (
In order to access DRAM (2) from C
Address decoder (3a) of PU (la) and CPU
When a memory access request is issued from the address decoder (3b) of (lb), the first contention control unit (5a) grants access rights to the CPU that issued the access request first to the second contention control unit (5b) and the second contention control unit (5b). Notify the selector (9). Next, the second contention control unit (5b) checks whether there is a refresh request from the refresh timer (4), and if there is no refresh request, it outputs a memory access request signal from the contention control unit (5a). Timing generator (6) Notifies the address multiplexer (7), the timing generator (6) generates DRAM control signals RAS and CAS based on the memory access request signal, and outputs the DRAM control signals RAS and CAS to the address multiplexer (7).
7) The selected CPU address is time-divisionally switched to a row address and a column address.

Also, if there is a refresh request, the contention control unit (5
The timing generator (6) and address multiplexer (7) are not notified of the request signal of either CPU (la) or (lb) selected by a), but the refresh request is notified to the timing generator (6).

While the refresh request is issued to the contention control unit (5b), the selected CPU waits, and from the time the refresh request is released, the CPU request signal is sent from the second contention control unit (5b) to the timing generator. (6)
Output to address multiplexer (7).

Therefore, according to the above embodiment, the DRAM shared by a plurality of cpo can be accessed asynchronously.

〔Effect of the invention〕

As described above, according to the present invention, refresh requests are prioritized and asynchronous contention control is performed between multiple CPOs, thereby eliminating the need for software flag sensing and the addition of an interrupt processing circuit. It's okay,
This also has the effect of maximizing the refresh interval.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a storage device control device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional storage device control device. (la), (tb) are the first and second CPUs,
(2) is DRAM. (3a) and (3b) are first and second address decoders, (4) is a refresh timer, (5a) is a first contention control unit, (5b) is a second contention control unit, and (6) is a Timing generator, (7) address multiplexer, (8) data buffer, (9) selector. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] A storage device control device that asynchronously accesses a dynamic storage device shared by a plurality of central processing units includes an address decoder that decodes each memory access request output from each central processing unit, and an address decoder that decodes each memory access request output from each central processing unit; A selector that selects an address from the central processing unit to be accessed; and a first competition that determines a conflict between memory access requests from each central processing unit provided via each of the address decoders and sends a selection control signal to the selector. a second contention control unit that cancels the memory access request resulting from the contention arbitration result and sends a refresh request signal when the refresh timer requests a refresh at predetermined intervals; and a timing generator that sends out a refresh control signal when the refresh request signal is input, and a timing generator that switches the upper and lower addresses of the central processing unit address selected by the first contention control unit to the storage device. 1. A control device for a storage device, comprising: an address multiplexer for sending data; and a data buffer for inputting and outputting data between a central processing unit selected by a first contention control unit and the storage device.