JPH03176734A - Encoder for parallel type multiplier - Google Patents

Abstract

PURPOSE:To make plural output delay variables identical and to increase the processing speed of an encoder by forming a double selective signal with an OR circuit and a NAND circuit, forming an mono-selective signal by an OR circuit and a NAND circuit and passing both the signals only with two steps of gates. CONSTITUTION:The double selective signal 2X and the mono-selective signal 1X are formed by two-stage logic circuits consisting of inverters 61, 63, 64 or inverters 63, 64 and a 6-input composite gate circuit 70 or a 4-input compositive gate circuit 80. Thereby, the output delay variable of the signal 2X coincides with that of the signal 1X and both signals 2X, 1X are obtained at the same timing. The number of stages of logic circuits for passing the signals 2X, 1X is reduced to two, the selective signal forming time can be shortened. Consequently, the processing speed of the encoder can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an encoder for parallel multipliers processed according to Booth's algorithm.

``Prior art'' Parallel multipliers that multiply digital signals have larger circuit scales than series-parallel multipliers, but they are currently widely used because they have fast calculation speed and can be integrated into LSI. It is becoming more and more common.

Among these parallel multipliers, there is one that uses a modified Booth algorithm as a means for particularly high-speed multiplication processing. This attempts to obtain the entire product by adding the partial products of the multiplier Y and the multiplicand X.

The Booth encoder obtains the signals (symbol selection signal, double selection signal, and single selection I8) necessary for generating partial products from the multiplier Y.

FIG. 3 is a diagram for explaining multiplication processing by partial products using the 2-bit Booth algorithm. The meaning of 2 bits here is the multiplier Y (e.g. 8-bit configuration yO
~y7) is divided into two bits from the LSB@, and each two bits (actually, one bit is used in overlap, so three bits) are processed.

When performing 8 x 8 pit multiplication from each 2 bits of the multiplier Y and the multiplicand is generated. Then, the respective partial products 1 to 4 are added. During this addition process, the complement conversion pit 5ao=Sd6 is added to the LSB of each partial product 1 to 4. The complement conversion bit is for converting a negative partial product into a two's complement.

Wallace's tree is one of the addition means that performs the addition process of partial products at high speed.
) circuit is known.

FIG. 4 shows an example of a parallel multiplier that performs multiplication according to Booth's algorithm and also performs partial product addition at high speed using a Wallace tree circuit.

The figure shows an 8 x 8 bit multiplier, in which four partial product circuits 10 are used to perform partial product processing between the multiplier Y and the multiplicand X.
~40 are provided.

The partial product circuits 10 to 40 shift or invert the multiplicand X based on the Booth encoders IOA to 40A to which the multiplier Y is supplied in 2-bit increments and the selection signals output from these encoders IOA to 40A. thick inverters IOB to 40B.

Partial product 4 (Fig. 3) is output from thick inverter IOB, and similarly thick inverters 20B to 40B
Partial products 3 to 1 (Fig. 3) are output.

The adder circuit 50 is composed of a Wallace tree circuit 50A to which partial products 1 to 4 are supplied, and a CLA adder (CLA is an abbreviation for Carry Look Ahead) 50B to which the output thereof is supplied, and performs CLA addition! 50B, the multiplication output Po=P14 is obtained.

As is well known, the Booth encoder used in such a parallel multiplier is constructed as shown in FIG.

Although the figure shows the configuration of encoder IOA, the other encoders 20A to 40A are similarly configured. FIG. 6 shows the truth table of this encoder IOA.

The upper bit y7 is connected to a two-stage inverter (NOT circuit) 11.
12, the code selection signal S is obtained from this.

The middle bit y6 and the lower bit y5 are each connected to a NOR circuit (
NOR circuit) 17 and AND circuit (AND circuit) 18
The respective outputs are NORed by a NOR circuit 19, and the output is used as a 1x selection signal IX.

On the other hand, the upper bit y7 and the middle bit y6 are a NAND circuit (NAND circuit) 13 and an OR circuit (OR circuit), respectively.
14, and the respective outputs are NANDed by a NAND circuit 15. The output and the 1x selection signal 1x are NORed in the NOR circuit 16, and the output is used as the 2x selection signal 13 2X.

"Problems to be Solved by the Invention" As is clear from the configuration of the encoder IOA shown in FIG. The bus of the NOR circuit 16 or the bus of the NOR circuits 17, 19, and 16 passes through three stages of gate circuits.

On the other hand, since the critical path of the 1x selection signal 1x becomes the bus of the NOR circuits 17 and 19, it passes through only the two-stage gate circuit.

Therefore, the timings at which the values of the double selection signal 2X and the single selection signal IX are determined are different from each other. Since each value is input to the same gate, a hazard (whisker) occurs in the output of that gate.

The present invention solves these conventional problems by correcting the amount of output delay so that the double selection signal 2x and the single selection signal LX are obtained at the same timing,
The present invention also proposes an encoder that enables faster partial product processing by reducing the number of stages through which gates pass.

"Means for Solving the Problem" In order to solve the above-mentioned problems, in the first invention,
The one at the booth? In encoders used in parallel multipliers using
As a circuit to obtain No. 4, the lower, middle, and upper powers rl! Lower, middle, and upper negation circuits that generate the negation ε of each of the i signals, a second upper negation circuit that further negates the output signal of the upper negation circuit, and a first three-input logic. a sum circuit, a second 3-input OR circuit, and a first 2-input logic to which the output signal of the first 3-input OR circuit and the output signal of the second 3-input OR circuit are input. a 6-input composite gate circuit configured with a product circuit, a first 2-input OR circuit, a second 2-input OR circuit, an output signal of the first 2-input OR circuit, and the second and a second two-input AND circuit to which the output signal of the two-input OR circuit is input; A code selection signal is obtained by passing through an upper NOT circuit, and the upper multiplier signal, the output signal of the upper NOT circuit, the middle multiplier signal, the output No. 45 of the middle NOT circuit, the lower multiplier signal, and the lower The output signal of the NOT circuit is inputted to the 6-input composite gate circuit to obtain 2x selection A8, and the intermediate multiplier 4G, the output signal of the intermediate NOT circuit, and the lower multiplier signal are The output signal of the lower-order NOT circuit is inputted to the four-input symptom gate circuit, and a one-time selection signal is obtained from this.

In the second invention, in a parallel multiplication 11M encoder using Booth's method, as a circuit for obtaining a code selection signal from successive lower, middle, and upper multiplier numbers 4g, the lower, middle, a lower, middle, and upper negation circuit that generates negation signals for each of the upper multiplier signals; a second upper negation circuit that further negates the output ε of the upper negation circuit; an input AND circuit, a second 3-input AND circuit, and a first 2-input AND circuit to which the output signal of the first 3-input AND circuit and the output signal of the second 3-input AND circuit are input. a 6-input symptom gate circuit configured with an input OR circuit, a first 2-input AND circuit, a second 2-input AND circuit, and an output signal of the first 2-input AND circuit; a 4-input combination gate circuit configured with an output signal of the second 2-input AND circuit and a second 2-input OR circuit to which the output signal of the second 2-input AND circuit is input; and a second upper NOT circuit to obtain a code selection signal, and the upper multiplier signal, the output signal of the upper NOT circuit, the middle multiplier signal, the output signal of the middle NOT circuit, and the lower multiplier signal. and the output signal of the lower negation circuit are input to the six-input combination gate circuit to obtain a 2x selection signal, and the intermediate multiplier signal, the output signal of the intermediate negation circuit, and the lower multiplier signal and the output signal of the lower-order NOT circuit are input to the four-input combination gate circuit to obtain the one-time selection ε.

``Function'' In this configuration, in the configuration of FIG. 1, the double selection signal 2x is generated by the OR circuit 71, 72 and the NAND circuit 73, and in the configuration of FIG. 7
7, the negation 7X of double selection A ε is generated.

Similarly, with the configuration shown in Figure 1, OR circuit 81.82 and NAND @
1883 generates a 1-time selection ε IX, and in the configuration shown in FIG.
Negation of double select signal - "X is produced.

As a result, in the configuration of FIG. 1, both the double selection signal 2X and the single selection signal 1x, and in the configuration of FIG. You will pass through only two stages of Gate @ Road. Now, since the output delay amounts are the same, the output timings match. Furthermore, since the number of stages of passing gates is reduced by one, the processing speed of the encoder is also increased.

"Embodiment" Next, an example of the encoder of the parallel multiplier according to the present invention will be described in detail with reference to FIG. M1 and FIG. 2.

Although this example also exemplifies the encoder provided in the partial product circuit 10, it is obvious that other encoders are similarly configured.

In FIG. 1, an inverter 61°63.64 is connected to each of the upper bit y7, middle bit y6, and lower bit y5.
is provided, and in addition to the upper multiplier signal, middle multiplier signal, and lower multiplier signal, their negative signals are output.

The upper multiplier signal (bit y7) is then used as the code selection signal S through two stages of inverters 61 and 62.

Upper, middle and lower multiplier signals (bits y7, y6...
y5) and their negation No. 13 are supplied to the six-input symptom gate circuit 70.

The 6-input symptom gate circuit 70 is configured such that when the upper and middle multiplier signals are different and the middle and lower multiplier signals are equal, the double scaling signal 2x becomes "1". ,
In the case of positive logic, a pair of OR circuits 71.7 as shown in the figure
2 and a NAND circuit 73 that receives their outputs.

The first OR circuit 71 is supplied with an upper multiplier signal and middle and lower negation signals, and the second OR circuit 72 is supplied with middle and lower multiplier signals in addition to the upper negation signal. be done.

This 6-input composite gate circuit 70 provides double selection (g 2X), so this 6-input composite gate circuit 70 and inverters 61, 63, 64 are composed of seven logic circuits 13 to 19 shown in FIG. The function is similar to that of the gate circuit.

The middle and lower multiplier signals and their negations are provided to a four-input composite gate circuit 80.

This 4-input composite gate circuit 80 is configured so that when the middle and lower multiplier signals are different, the 1x multiplier IX becomes "1", and in the case of positive logic, the It is composed of a pair of OR circuits 81 and 82 and a NAND circuit 83 to which their outputs are supplied.

The third OR circuit 81 is supplied with the middle multiplier signal and the lower NOT signal, and the fourth OR circuit 82 is supplied with the middle NOT 13 and the lower multiplier signal. Since the NAND circuit 83 outputs a 1x selection signal 1x,
This 4-input composite gate circuit 80 and inverter 63.64
functions similarly to the gate circuit composed of logic circuits 17 to 19 shown in FIG.

As is clear from this configuration, both the double selection signal 2X and the single selection signal 1x are connected to the inverter 61°63.64 or the inverter 63.64 and the 6-input composite gate circuit 70.
Alternatively, since it is configured with a two-stage logic circuit consisting of a 4-input composite gate circuit 80, the output delay amount of the double selection compensation code 2X and the single selection compensation code 1X is the same, and the reselection signal is sent at the same timing. 2x and IX are obtained.

Since the number of stages of logic circuits through which the fs signal passes through the double selection code 2X and the single selection code 1x is reduced to 2, the generation time of the selection code 8 is shortened accordingly, so the processing time is faster. , and can realize a high-speed encoder.

FIG. 2 is a modification of FIG. 1, and is a composite gate circuit 7.
This is a case where 0.80 is configured as a negative logic.

Therefore, each of the double selection signal 2x and the single selection signal IX is inverted and output.

Therefore, the 6-input composite gate circuit 70 is composed of a pair of AND circuits 75 and 76 and a NOR circuit 77. Also,
The 4-input composite gate circuit 80 is a pair of AND circuits 85.8
6 and a NOR circuit 87.

The input/output relationships for them are exactly the same except that the output polarity is reversed, so a detailed explanation thereof is provided below.

In this configuration as well, the output timings of the reselection points ε and T'X match, and the number of gate stages can be reduced by one.

"Effects of the Invention" As explained above, in the present invention, a selection signal is generated using a composite gate circuit having a 6-input and 4-input configuration.

According to this, the generation timing of the double selection signal and the single selection signal can be made to match, so that it is possible to predict the occurrence of a hazard.

In addition, since the number of stages of composite gates with 6-input and 4-input configurations is suppressed, selection signal generation time is shortened accordingly, processing time is increased, and a high-speed encoder can be realized.

[Brief explanation of drawings]

1 and 2 are connection diagrams showing an example of a parallel multiplication processing encoder according to the present invention, FIG. 3 is an explanatory diagram of parallel multiplication processing, FIG. 4 is a parallel multiplication processing system diagram, and FIG. A connection diagram of the encoder used, and FIG. 6 is a diagram showing its truth table. 10-40 ・ 10A-40A ・ 10B-40B ・ 50 ・ 50A ・ 50B ・ 70 ・ 80 ・

Claims (2)

[Claims] (1) In an encoder used in a parallel multiplier using Booth's method, as a circuit for obtaining a code selection signal from successive lower, middle, and upper multiplier signals, the lower, middle, and upper multiplier signals are Lower, middle, and upper negation circuits that generate negation signals for each of the multiplier signals, a second upper negation circuit that further negates the output signal of the upper negation circuit, and a first 3-input OR circuit. , a second 3-input OR circuit, and a first 2-input AND circuit to which the output signal of the first 3-input OR circuit and the output signal of the second 3-input OR circuit are input. a 6-input composite gate circuit configured with a first 2-input OR circuit, a second 2-input OR circuit, an output signal of the first 2-input OR circuit, and the second 2-input OR circuit; and a second two-input AND circuit to which the output signal of the input OR circuit is input; A code selection signal is obtained by passing through a negation circuit, and the upper multiplier signal, the output signal of the upper negation circuit, the middle multiplier signal, the output signal of the middle negation circuit, the lower multiplier signal, and the output signal of the lower negation circuit are The output signal is input to the six-input composite gate circuit to obtain a double selection signal, and the intermediate multiplier signal, the output signal of the intermediate NOT circuit, the lower multiplier signal, and the output of the lower NOT circuit are input. An encoder for a parallel multiplier, characterized in that a signal is input to the four-input composite gate circuit to obtain a one-time selection signal. (2) In an encoder for parallel multipliers using Booth's method, each of the lower, middle, and upper multiplier signals is used as a circuit for obtaining a code selection signal from successive lower, middle, and upper multiplier signals. a lower, middle, and upper NOT circuit that generates a NOT signal, a second upper NOT circuit that further negates the output signal of the upper NOT circuit, a first 3-input AND circuit, and a second a 3-input AND circuit, and a first 2-input OR circuit to which the output signal of the first 3-input AND circuit and the output signal of the second 3-input AND circuit are input. a 6-input composite gate circuit, a first 2-input AND circuit, a second 2-input AND circuit, an output signal of the first 2-input AND circuit, and the second 2-input AND circuit; a 4-input composite gate circuit configured with a second 2-input OR circuit to which an output signal of the 4-input OR circuit is input, and passes the higher-order multiplier signal through the upper-order NOT circuit and a second higher-order NOT circuit. a code selection signal is obtained by the above, and the upper multiplier signal, the output signal of the upper NOT circuit, the middle multiplier signal, the output signal of the middle NOT circuit, the lower multiplier signal and the output signal of the lower NOT circuit are combined. input to the 6-input composite gate circuit to obtain a double selection signal therefrom; 1. An encoder for a parallel multiplier, characterized in that the encoder is input to a 4-input composite gate circuit to obtain a 1x selection signal.