JPS59202542A - Decoder circuit - Google Patents

Abstract

PURPOSE:To speed up a decoder circuit of a parallel digital multiplier using the algorithm of the modified Booth and also to reduce the number of components by combining effectively a transfer gate and a tri-stage inverter. CONSTITUTION:X1, X2 and N are obtained in place of 0+ or -X, + or -2X as a control output of the Booth decoder circuit, where X1 is a partial product of X, X2 is a partial product of 2X and N represents that the partial product is inverted into a negative number. In taking a notice that the logical equation of this decoder is modified as shown in Equation, the circuit is constituted that the tri-state inverter 8 is activated by y2i and the transfer gate 7 is activated by y2i+2'. Thus, the number of transistors required is decreased to 28 pieces, while 34 pieces were hitherto required.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital multiplier suitable for configuring with MOS transistors, and in particular to a decoder/circuit for a parallel digital multiplier using a modified Booth's algorithm. Example configuration and its problems Parallel digital multipliers are increasingly being used in an increasingly wide range of applications, and are increasingly being integrated into LSIs. Parallel digital multipliers implemented in LSI, which are sometimes required to have high multiplication speeds, are constructed based on a modified Booth algorithm. This transformation Bo, oth
To explain the algorithm, if X is a multiplicand and Y is a multiplier, and each is expressed as a two's complement number, the multiplication result can be expressed as follows.

X@Y=X-(-2n-'ayn+2n-2myn',
+...→-y1) However, yO-O.

Here PP, -(y2i+y2.+1-2y2□+2)
・X is a partial product, and its value takes either O2±X or ±2X depending on the continuous Y rabbit pattern. The number of partial products is approximately half the number of pits of Y, and accordingly, the time for adding these partial products is also halved, allowing high-speed multiplication. Parallel digital multipliers usually have a cell that generates a partial product, adds it to the partial sum sent from the previous stage, and sends the partial sum to the next stage, and a partial product of either O2±X or ±2X to this cell. The latter is particularly called a Booth decoder circuit.

The Booth decoder circuit outputs ○, ±X,
In place of ±2X, Xl, X2. It has three pieces of N, and Xl represents that X is a partial product, X2 represents that 2X is a partial product, and N represents that the partial product is a negative number. The bit patterns correspond as shown in the table below.

Below margin XL, x2. Each of N can be expressed as the following logical formula, X1=72i0y2i+1 (■ is exclusive OR) (2)
X2=y2i @y2i+1 ′″y2i+2+y2i
@V2i+1°y2i+2(3) N=y21+2(4) As a result, Booth's decoder circuit becomes as shown in Figure 1 when one stage of inverter is added to provide sufficient driving capability for the control output. 1 to 3 are consecutive Y 3-bit input signal lines y2□T72□+1. y2
□+2, and 4 to 6 are each X1°X2. This is a control output line corresponding to N.

However, if the circuit shown in Figure 1 is configured with ordinary 0MO8 logic gates, it will require 34 transistors, and it will also include composite gates such as 6-man AND-NOR gates, which are disadvantageous in terms of speed, resulting in high integration. , it was difficult to increase the speed.

OBJECTS OF THE INVENTION The present invention has been made in view of such conventional problems, and its purpose is to reduce the total number of elements in a circuit,
The present invention provides a Booth decoder circuit that achieves high speed and high integration.

Structure of the Invention The present invention realizes an Eooth decoder circuit that reduces the total number of elements by effectively using transfer gates and tristate inverters without using slow multi-input composite gates. It is something to do.

DESCRIPTION OF THE EMBODIMENTS FIG. 2 shows a Booth decoder circuit in the first embodiment of the present invention, 1 to 6 in the same figure are the same as 1 to 6 in FIG. 1, 7 is a transfer gate, and 8 is a try. State inverter, 9 is NAND gate, 1o is ○R-NA
An ND gate, 11 is a NOR gate, and 12 is an inverter, each of which has a CMO8 configuration.

Equation (3) can be transformed as shown in the following equation.

(5) What this formula means is that when 72i+2 is at a high logic level, the NOR output of y2i and y2i+1 is inverted and output, and when y2i+2 is at a low logic level, y2□ and 72i+1
This means that the N A N D output of is used as an output, and this output is further inverted. For the former pair 1-, by activating the tri-state inverter 8 at y2i+2, for the latter pair, the transfer gate 7
Each output can be obtained by activating y2i+2. Since the NAND output of 72i, y2□, etc. can be obtained in the process of obtaining the <Xl signal as shown in FIG. Xl.

The N signal is obtained with the same gate configuration as the conventional example.

As described above, according to this embodiment, the transfer gate 7 and the tristate inverter 8 are effectively used and activated in a complementary manner to obtain the desired output depending on the logic level of y2□+2. By doing so, it is possible to reduce the number of transistors that were conventionally required from 34 to 28. In the conventional example, a six-person composite gate is used to obtain the X2 signal, but such multi-input composite gates generally have large wiring capacitances, large diffusion capacitances in the drain and source regions, and require many loads to be driven. The speed is slow because it is carried out through transistors. In addition, in the case of R-bad in the six-man power combination gate shown in FIG. 1, the output load must be driven through three transistors. On the other hand, in the configuration in which the X2 signal is obtained in the present embodiment, the output load is driven through two transistors even in the worst case, and the wiring capacitance and diffusion capacitance can also be made smaller than in the conventional example. The average operating speed is faster than that of the conventional example. If the delay time of an inverter is actually 1.△, a conventional 6-man power gate using the same transistors would require about 3△ to 4△, whereas a tri-state inverter would require 2△ to 2.6△. ,
The transfer switch has a delay of about 0.5△ to 1△.

In this embodiment, the Xl signal is the exclusive signal of Y2i and y214-1 obtained from gate 9.10.
The NOR output is obtained by inverting it with the inverter 12, but the exact of Y2i and y2i+1 is obtained using the NOR gate and A
e The OR output may be output as Xl and 1~, and in this case, the X2 signal can be obtained from the same configuration by adding a new NAND gate instead of adding a new N0ft gate in the embodiment. can.

Further, in this embodiment, one stage of inverter 12 is added in order to provide sufficient driving capacity to the control output lines 4 to 6, but if this inverter is not added, each X1. X2. Inverted output of N signal X1. X2. It is also clear that N can be obtained.

Furthermore, input signals y2□, y2□+1. It is clear that a configuration in which the respective inverted signals y2□, y2□+1, and 2□+2 are input instead of y2□+2 can be easily devised from this embodiment.

Effects of the Invention As described above, the present invention activates the transfer gate and the tri-state inverter in a complementary manner so that each N A
By inverting the ND output and inverting the NOR output, it is possible to realize an excellent Booth decoder circuit that can reduce the number of constituent transistors and increase signal propagation speed.

[Brief explanation of the drawing]

FIG. 1 is a conventional Booth decoder circuit diagram, and FIG. 2 is a Booth decoder circuit Ii in an embodiment of the present invention.
! This is Figure 8. 1 to 3...Continuous Y 3-pit input signal line,
4-6...Xl, X2. Control output line corresponding to N, 7... Transnor gate, 8...
- Tri-state inverter.

Claims (1)

[Claims] 1st. a NAND gate that receives a second input signal;
Said 1st. a NOR gate that receives a second input signal as an input; a transfer gate that receives the output of the NAND gate as an input; a state inverter, the transfer gate and the tristate inverter are configured to be activated in a complementary manner according to a logic level of a third input signal, and the transfer gate A decoder circuit characterized in that an output signal is obtained at the output of the decoder circuit.