JPH03174648A - Integrated circuit with constitution for parallel processing system - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the system performance by performing the communication of data between optional component elements with no intervention of the control of software regardless of the presence or absence of the rule properties included in the connection relation between the processing execution units forming a parallel processing system. CONSTITUTION:When data are inputted via an input/output port 5, a communication control means 1 retrieves an accepted data tag address holding means 3 and a port output data tag address holding means 4. When the tag address of the inputted data is held by the means 3, a processing execution means 2 is started to receive and process the inputted data. Meanwhile the data decided by the retrieving result and inputted via the port 5 are outputted if the tag address of the inputted data is held by the means 4. As a result, the system performance is improved.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention aims to perform parallel processing and improve processing capacity by connecting a plurality of integrated circuits that serve as structural units and processing execution units. A parallel processing system configuration integration that improves system performance by efficiently and quickly transferring data between arbitrary constituent units in a parallel processing system, regardless of whether or not the succession relationship between constituent units is regular. Regarding circuits.

(Prior Art) In order to improve the performance of a computer system, processing can be performed in parallel not only by one processor but by multiple processors. Parallel processing systems such as loosely coupled multiprocessor systems in which multiple processors with local memory are connected are suitable for processing problems with large parallelism. In the case of this loosely coupled multiprocessor system, it is important to connect more processors to achieve higher performance. However, there is a physical limit to the number of processing execution units that can be connected to one processing execution unit consisting of local memory and a processor, and it is difficult to realize data communication between any two processing execution units. This required relay transmission of data.

In order to relay data, each processing execution unit has an address. Data communication is performed by specifying the address of the processing execution unit to which data is to be sent.

Each processing execution unit identifies the tag address, which is the address of the processing execution unit to which data added to data or given as part of the data is sent, and accepts the input data if it matches its own address. If they do not match, the data input via the port determined by the tag address is output.

By relaying the input data to other processing execution units in this way, data communication can be performed between arbitrary processing execution units.

When performing data communication between any two processing execution units,
As the number of processing units required for relaying increases, the time required for data communication increases, and the performance of the system deteriorates. In order to avoid this problem, each processing execution unit is Connected. Furthermore, the time required for relaying is not shortened...Secondly, the operation of recognizing the tag address and transmitting data, or the operation of outputting data, is usually controlled by hardware.

However, in the case of such a physically fixed connection relationship, depending on the problem to be processed, there is a possibility that some buses may be blocked due to the problematic locality of data communication. For this reason, it is preferable to be able to change the physical connection relationship or change the logical communication path. Figure 4 is a diagram showing an example in which a bus is blocked and data communications are obstructed due to the problematic locality of data communications, and Figure 5 shows how to solve the problem by changing the physical connection relationship. FIG.

Furthermore, FIG. 6 is a diagram showing a method for solving the above problem by changing the logical communication path.

(Problems to be Solved by the Invention) The conventional parallel processing system configuration integrated circuit shown above is
If there is no regularity in the physical connection relationship between processing execution units, it is difficult to determine the output port for the data to be transferred. Must be done via control,
This method has the disadvantage that the time required for data transfer is longer and system performance is lowered.

(Means for Solving the Problems) The parallel processing system configuration integrated circuit of the present invention has the following (A)
(3).

(A) at least one input/output port for inputting or outputting data; (B) zero or more processing means for receiving and processing input data input through the input/output port; (C) executing the processing. The process retains the same tag address as the tag address given to the input data in order to indicate whether or not to accept the input data and perform data processing by the process execution means in accordance with the means. (D) as many receiving data tag address holding means as execution means, corresponding to said input/output ports that output data;
Data that holds the same tag address as the tag address assigned to the input data, in order to indicate whether or not the input data or the processed data output from the processing execution means is outputted from the input/output port as output data. (E) When the input data is input through the input/output ports, the receiving data tag address holding means and the port output data tag address A hardware search is performed to determine whether or not the same tag address as the input data is held in the holding means, and if the tag address is held in the received data tag address holding means, the input data is Sends the input data to the processing execution processing means, and if the tag address is held in the port output data tag address holding means, sends the input data through the input/output port, and sends the input data to the processing execution means. When the processed data is output from the port output data tag address holding means, it is searched by hardware whether the same tag address as the processed data is held,
If the data is held, the communication control means sends the processed data via the input/output port.

(effect) Next, the operation of the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing the constituent elements of the present invention.

In FIG. 1, 1 is communication control means, 2 is processing execution means, 3 is received data tab address holding means, 4 is port output data tag address holding means, and 5 is an input/output port.

In FIG. 1, when data is input through the human output port 5 during data communication, the communication control means 1 searches the received data tag address holding means 3 and the port output data tag address holding means 4. .

When the tag address of the input data is held in the received data tag address holding means 3, the processing execution means 2 is activated to accept the input data and execute the processing. When the tag address of the input data is held in the port output data tag address holding means 4, the input/output port 5 determined as a result of the search is
The input data is outputted via.

(Example 1) Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows an embodiment of the integrated circuit of this patent. Further, FIG. 3 shows an example of a parallel processing system configured using the integrated circuit of this patent as a structural unit and a processing execution unit.

2 and 3, reference numeral 10 denotes a communication control section, which corresponds to the communication control means 1. In FIG. Reference numeral 20 denotes a processing execution unit, which corresponds to processing execution means. The communication control unit 10 has the same number of received data tag addresses CAMII as the processing execution units 20 corresponding to the received data tag address holding means 3, and the same number of output port tag addresses CAM12 as the input/output ports that output data.
have. Further, 100 is an integrated circuit of this embodiment.

In this embodiment, the integrated circuit 100 includes one processing execution unit 20.
and four input/output ports 5. These are identified by port numbers. Further, the parallel processing system of this embodiment is composed of four integrated circuits 100. These are identified by addresses.

In FIG. 2, when data is input through the input/output port 5 during data communication, the communication control unit IO determines the received data tag address CAMII and the number of ports according to the tag address of the input data. The same number of port output data tag addresses CAM12, that is, four port output data tag addresses CAM12, are accessed to search for the tag address. If the received data tag address CAMII holds the tag address of the input data, the processing execution unit 20
, accepts the input data, and executes the process. When the tag address of the input data is held in the port output data tag address CAM12, the input data is transferred through the human output port 5 corresponding to the held port output data tag address CAM12. Output.

Furthermore, when processing data is output from the processing execution section 20 as a processing result, the communication control section 10 accesses the four port output data tag addresses CAM12 using the tag address of the processing data, and searches for the tag address. conduct. When a tag address is held in the port output data tag address CAM, the processed data is outputted via the input/output port 5 corresponding to the held port output data tag address CAM12.

In FIG. 3, in order to process problems in parallel, integrated circuits 100, which are constituent units and processing execution units, are interconnected via human output ports 5 to constitute a parallel processing system. The operation of the integrated circuit 100 in data communication performed between arbitrary integrated circuits will be described using data communication from an integrated circuit at address O to an integrated circuit at address 3 as an example.

The data output as a result of the processing by the processing execution unit 20 of the integrated circuit 100 at address O has an address of the integrated circuit that is the processing execution unit to which the data is sent, that is, a tag address. The communication control unit 10 of the integrated circuit 100 at address O has port output data tag address CAM1.
Perform the search in step 2. In this example, the tag address is registered in the port output data tag address CAM 12 corresponding to the port with port number 3, and the communication control unit 10 outputs the output data via the input/output port 5 with port number 3. .

Data output from the integrated circuit 100 at address 0 is input to the integrated circuit 100 at address 2 via the input/output port with port number 1. The communication control unit 10 of the integrated circuit (11) 100 at address 2 receives the received data tag address C.
AMII and port output data address CAM12 are searched. The tag address of the input data is held in the port output data tag address CAM 12 corresponding to the port with port number 2, and is output through the port with port number 2.

The data output from the integrated circuit 100 at address 2 is
Integrated circuit 1 at address 3 through port number 0
00 is input. The communication control unit 10 of the integrated circuit 100 at address 3 searches for the received data tag address CAMII and the port output data address CAM12.

The tag address of the input data is held in the accepted data tag address CAMII, the input data is accepted, and data communication from the integrated circuit at address O to the integrated circuit at address 3 is completed.

(Example 2) Example 1 was an example of a parallel processing system composed of the same parallel processing system configuration integrated circuits.

Example 2 consists of two different types of integrated circuits (1
2) A parallel processing system will be explained as an example with reference to the drawings. FIG. 7 is a diagram showing the two types of integrated circuits, and FIG. 8 is a diagram showing the two types of integrated circuits.
1 is a diagram illustrating an example of a parallel processing system composed of various types of integrated circuits; FIG.

7(a), (b) and FIG. 8, 200
is an integrated circuit that performs processing, and has a processing execution section 20. 300 is a parallel processing system configuration integrated circuit that controls communication between integrated circuits 200 that perform processing, and has a communication control unit 10 having the same number of output port tag addresses CAM12 as ports that output data.

In this embodiment, the parallel processing system configuration integrated circuit 300 that controls communication has four input/output ports, which are identified by port numbers. Further, the parallel processing system of this embodiment is composed of an integrated circuit 200 that performs eight processes and four integrated circuits that control communications. The eight processing execution units are identified by addresses.

In FIG. 7, in the parallel processing system configuration integrated circuit 300 that controls communication, when data is input through the input/output port 5 during data communication, the communication control unit 10
Based on the tag address of the input data, the same number of port output data tag addresses CAM12 as the number of ports, that is, four port output data tag addresses CAM12 are accessed to search for the tag address. When the tag address of the input data is held in the port output data tag address CAM12, the input data is transferred via the input/output port 5 corresponding to the held port output data tag address CAM12. Output.

Address 3 from the integrated circuit 200 that processes address 0
Data transfer to the integrated circuit 200 that performs the processing is performed as follows.

The integrated circuit 200 that processes address O specifies the data transfer destination address, that is, address 3, as a tag address, and sends the data to the parallel processing system configuration integrated circuit 300 that controls the communication of A via port number 0. Output data. In the parallel processing system configuration integrated circuit 300 that controls the communication of port A, address 3 is held in the output port tag address CAM12 corresponding to the port with port number 2, and the communication control unit 10 controls the port number 2. Data is transferred via input/output ports. In the parallel processing system configuration integrated circuit 300 that controls communication of B to which data is input through the input/output port with port number O, address 3 is held in the output port tag address CAM12 corresponding to the port with port number 2. The communication control unit 10
Data is output through the input/output port with port number 2, and data transfer from the integrated circuit 200 that processes address O to the integrated circuit 200 that processes address 3 is completed.

For example, a path connecting the parallel processing system configuration integrated circuit 300 that controls the communication of A used in this data transfer and the parallel processing system configuration integrated circuit 300 that controls the communication of B is connected to the integrated circuit 200 that processes the address l. address 2
If the integrated circuit 20 is used for data transfer between integrated circuits that process address O,
Data transfer between integrated circuits processing addresses 0 and 3 is inhibited. In this case, address 3 is set to the output port tag address CAM12 corresponding to the input/output port with port number 3 of the parallel processing system configuration integrated circuit 300 that controls the communication of A, and the parallel processing system configuration integrated circuit that controls the communication of B Output port tag address corresponding to input/output port with port number 2 of circuit 300 Address 3 is assigned to CAM12; parallel processing system configuration integrated circuit 3 that controls communication of C;
By setting address 3 in the output port tag address CAM12 corresponding to port number 10 input/output port of 00, data communication is performed by data transfer between the integrated circuit 200 that processes address 1 and the integrated circuit that processes address 2. It is possible to avoid the inhibition of

(Effects of the Invention) As explained above, the present invention enables the processing to be performed without using software control, regardless of whether or not there is regularity in the connection relationships between processing execution units that constitute a parallel processing system.
This has the effect that data communication between arbitrary components can be performed efficiently and at high speed, and that deterioration in system performance can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the components of the present invention, FIG. 2 is a diagram showing an embodiment of the integrated circuit of the present invention, and FIG. 3 is an example of a parallel processing system configured using the integrated circuit of the present invention. Figure 4 is a diagram showing a state in which data transfer is inhibited due to the locality of data transfer, and Figure 5 is a diagram showing a state in which data transfer is inhibited by changing the physical connection relationship. FIG. 6 is a diagram showing a method of avoiding the problem of inhibiting data transfer by changing the data transfer route. FIGS. 7 and 8 are diagrams showing a method for avoiding the problem of inhibiting data transfer. FIG. 3 is a diagram for explaining an example. 1... Communication control means, 2... Process execution means, 3...
- Reception data tag address holding means, 4: Port output data tag address holding means, 5: Input/output port, 10: Communication control unit, 11: Reception data tag address CAM. 12... Port output data tag address CAM. 20... Process execution unit, 100... Integrated circuit.

Claims (1)

[Scope of Claims] A parallel processing system configuration integrated circuit characterized by comprising the following (A) to (E). (A) at least one input/output port for inputting or outputting data; (B) zero or more processing means for receiving and processing input data input through the input/output port; (C) executing the processing. The processing execution means holds the same tag address as the tag address given to the input data to indicate whether or not to accept the input data and perform data processing by the processing execution means. (D) a number of receiving data tag address holding means corresponding to said input/output ports for outputting data;
Data that holds the same tag address as the tag address assigned to the input data, in order to indicate whether or not the input data or the processed data output from the processing execution means is outputted from the input/output port as output data. (E) When the input data is input through the input/output ports, the receiving data tag address holding means and the port output data tag address holding means have the same number as the input/output ports that output the data. A hardware search is performed to determine whether or not the same tag address as the input data is held in the means, and if the tag address is held in the received data tag address holding means, the input data is If the tag address is held in the port output data tag address holding means, the input data is sent to the processing execution means, and if the tag address is held in the port output data tag address holding means, the input data is sent out through the input/output port, and When the processed data is output, searching by hardware whether or not the same tag address as the processed data is held in the port output data tag address holding means;
If the data is held, the communication control means sends the processed data via the input/output port.