JPH03173115A - Inspecting method for focus of reduction projection exposure apparatus for lsi - Google Patents
Inspecting method for focus of reduction projection exposure apparatus for lsiInfo
- Publication number
- JPH03173115A JPH03173115A JP1312968A JP31296889A JPH03173115A JP H03173115 A JPH03173115 A JP H03173115A JP 1312968 A JP1312968 A JP 1312968A JP 31296889 A JP31296889 A JP 31296889A JP H03173115 A JPH03173115 A JP H03173115A
- Authority
- JP
- Japan
- Prior art keywords
- patterns
- pattern
- focus
- lsi
- projection exposure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 17
- 238000007689 inspection Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本願発明は集積回路製造工程におけるレジスト露光プロ
セスの適正状態の良否を評価するＬＳＩ用縮小投影露光
装置の焦点検査方法に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a focus inspection method for a reduction projection exposure apparatus for LSI, which evaluates the suitability of a resist exposure process in an integrated circuit manufacturing process.
〈従来の技術〉
集積回路素子のＬＳＩマスクパターンをウェハー上に露
光して形成する工程においては、集積度の増加、パター
ン寸法の微細化に伴い、縮小投影露光装置を使用した露
光方法が一般的となり、従ってパターンの解像度を向上
させるために、レンズの開口数ＮＡが次第に高くなる傾
向になってきている。<Prior art> In the process of forming an LSI mask pattern for integrated circuit elements by exposure on a wafer, as the degree of integration increases and pattern dimensions become finer, an exposure method using a reduction projection exposure apparatus is common. Therefore, in order to improve the pattern resolution, there is a tendency for the numerical aperture NA of the lens to gradually increase.
〈発明が解決しようとする課題〉
しかしながら、前述したように縮小投影露光装置のレン
ズの開口数ＮＡが高くなってきている関係上、解像度の
向上が期待できる反面、焦点深度が浅くなり、段差を有
するパターンでは、極めて焦点深度が浅くなるという問
題があった。すなわち、縮小投影露光装置において、そ
のレンズの開口数ＮＡを上げる環境のもとでは、段差を
有するパターンは好ましくない。<Problems to be Solved by the Invention> However, as mentioned above, as the numerical aperture NA of the lens of reduction projection exposure equipment is becoming higher, while an improvement in resolution can be expected, the depth of focus becomes shallower, making it difficult to reduce the level difference. This pattern has a problem in that the depth of focus becomes extremely shallow. That is, in a reduction projection exposure apparatus, a pattern having steps is not preferable under an environment where the numerical aperture NA of the lens is increased.
本発明は上記事情に鑑みて創案されたもので、集積回路
素子の製造工程時における上記問題点を排除するために
、ＬＳＩに簡易検査パターンを設けることにより、縮小
投影露光装置の焦点状態の便利、簡易なる検査方法を従
供することを目的としている。The present invention was devised in view of the above-mentioned circumstances, and in order to eliminate the above-mentioned problems during the manufacturing process of integrated circuit elements, it is possible to conveniently adjust the focus state of a reduction projection exposure apparatus by providing a simple inspection pattern on an LSI. The purpose is to provide a simple inspection method.
〈課題を解決するための手段〉
本願発明に係るＬＳＩ用縮小投影露光装置の焦点検査方
法は、基板に段差を設ける工程と、上段に順次寸法の異
なるパターンを設けるとともに、下段に前記パターンと
同一寸法のパターンを並列した状態で設け、前記同一寸
法のパターンを観察することにより、ＬＳＩ用縮小投影
露光装置の焦点が適正状態にあるか否かを検査すること
を特徴としている。<Means for Solving the Problems> A focus inspection method for a reduction projection exposure apparatus for LSI according to the present invention includes the steps of providing a step on a substrate, providing patterns with sequentially different dimensions on the upper layer, and forming patterns identical to the aforementioned pattern on the lower layer. The present invention is characterized in that patterns of the same dimensions are arranged in parallel, and by observing the patterns of the same dimensions, it is inspected whether the focal point of the reduction projection exposure apparatus for LSI is in a proper state.
く作用〉
基板上に段差を設け、その段差の対応した位置に同一寸
法のパターンを並列して設ける。その後、前記対応した
パターンの寸法を観察することにより、ＬＳＩ用縮小投
影露光装置の焦点が適正であるかどうかを検査する。Effect> Steps are provided on the substrate, and patterns of the same size are arranged in parallel at positions corresponding to the steps. Thereafter, by observing the dimensions of the corresponding pattern, it is checked whether the focus of the reduction projection exposure apparatus for LSI is appropriate.
〈実施例〉
以下、図面を参照して本発明に係る一実施例を説明する
。第１図は本願発明に係る工程断面図であって、（１）
は段差パターンの形成状態、（２）はレジスト塗布後、
（３）は露光状態、（４）は現像後の状態の断面図をそ
れぞれ示している。<Example> Hereinafter, an example according to the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of the process according to the present invention, (1)
(2) is the state of formation of the step pattern, (2) is after resist coating,
(3) shows a cross-sectional view of the exposed state, and (4) shows a cross-sectional view of the developed state.
ここで第１図の工程の手順について説明する。Here, the procedure of the process shown in FIG. 1 will be explained.
■基板１に適宜な方法（例えばエツチング）で、段差パ
ターン２を形成する（同図（１））。(2) A step pattern 2 is formed on the substrate 1 by an appropriate method (for example, etching) ((1) in the same figure).
■形成された段差パターン２の上にフォトレジスト３を
平面状に塗布する（同図（２））。(2) A photoresist 3 is applied in a planar manner on the formed step pattern 2 ((2) in the same figure).
■上記フォトレジスト３を塗布したものにおいて、マス
ク４を用いて紫外線露光を行う（同図（３））。(2) The photoresist 3 coated thereon is exposed to ultraviolet light using a mask 4 ((3) in the same figure).
■現像を行い、レジストパターン５を形成する。(2) Development is performed to form a resist pattern 5.
このレジストパターン５は説明の関係上、基板１（下段
）の上にパターンＡ、Ｂ、Ｃが形成されており、段差パ
ターン２（上段）の上にパターン八１．９／、（Ｈｌが
形成されているものとする。そして前記パターンのサイ
ズはＡ ＝Ａ ’ 、Ｂ ＝Ｂ ’ｃ ＝ｃ ’であり
、且つＡ ＜Ｂ ＜Ｃであるものとする（同図（４））
、。For the sake of explanation, this resist pattern 5 has patterns A, B, and C formed on the substrate 1 (lower stage), and patterns 81.9/, (Hl) formed on the step pattern 2 (upper stage). The size of the pattern is A = A', B = B'c = c', and A < B < C ((4) in the same figure).
,.
０次に光学顕微鏡を用いて、焦点が適正であるか否かの
検査を行う。In the 0th order, an optical microscope is used to inspect whether the focus is appropriate.
第２図は光学顕微鏡を用いて前記各パターンを観察した
場合の検査パターンの平面図である。FIG. 2 is a plan view of the inspection patterns when each of the patterns is observed using an optical microscope.
焦点が適正である場合には、前記パターンの大きさは前
記したように、＾＝Ａ ’ 、Ｂ ＝Ｂ ’ 、Ｃ＝Ｃ
′のように観察される（第２図（１））。When the focus is appropriate, the size of the pattern is as described above, ^=A', B=B', C=C
' (Figure 2 (1)).
段差の上下でパターン寸法に差異がある場合には、Ａ
＜Ａ ’ 、Ｂ ＜Ｂ ’ 、Ｃ＜Ｃ’のように観察さ
れる（第２図（２）ａ） 、または第２図（２）ｂに図
示するように寸法の小さいパターンが消失して観察され
る。すなわち、同図では、へのパターンが消失して観察
される。If there is a difference in pattern dimensions above and below the step, please use A.
<A', B<B', C<C' (Fig. 2 (2) a), or as shown in Fig. 2 (2) b, small patterns disappear. be observed. That is, in the same figure, the pattern of is observed to have disappeared.
〈発明の効果〉
本願発明に係るＬＳＩ用縮小投影露光装置の焦点検査方
法は、基板に段差を設ける工程と、上段に順次寸法の異
なるパターンを設けるとともに、下段に前記パターンと
同一寸法のパターンを並列した状態で設け、前記同一寸
法のパターンを観察することにより、ＬＳＩ用縮小投影
露光装置の焦点が適正状態にあるか否かを検査するもの
であるから、この検査方法は極めて簡便であり、少なく
とも検査パターンに段差をつけることにより、適正な焦
点が段差の上下段で２箇所存在することを観察するだけ
で正確な焦点検査が可能になるという効果を奏する。<Effects of the Invention> The focus inspection method for a reduction projection exposure apparatus for LSI according to the present invention includes the steps of providing a step on a substrate, providing patterns with sequentially different dimensions on the upper layer, and forming a pattern with the same size as the pattern on the lower layer. This inspection method is extremely simple, since it is inspected whether the focal point of the LSI reduction projection exposure apparatus is in a proper state by providing them in parallel and observing the patterns of the same size. At least by providing a step in the inspection pattern, an effect is achieved in that accurate focus inspection can be performed simply by observing that there are two proper focal points at the upper and lower stages of the step.
第１図は本願発明に係る工程断面図であって、（１）は
段差パターンの形成状態、（２）はレジスト塗布後、（
３）は露光状態、（４）は現像後の状態の断面図をそれ
ぞれ示している。
第２図は光学顕微鏡を用いて前記各パターンを観察した
場合の検査パターンの平面図である。
１ ・・・・基板
２ ・・・・段差パターン
３ ・・・・フォトレジスト
４ ・・・・マスク
５ ・・・・レジストパターンFIG. 1 is a cross-sectional view of the process according to the present invention, in which (1) shows the state of formation of the step pattern, and (2) shows the state of formation of the step pattern, and (2) shows the state of formation of the step pattern after resist application.
3) shows a cross-sectional view of the exposed state, and (4) shows a cross-sectional view of the state after development. FIG. 2 is a plan view of the inspection patterns when each of the patterns is observed using an optical microscope. 1...Substrate 2...Step pattern 3...Photoresist 4...Mask 5...Resist pattern
Claims (1)
なるパターンを設けるとともに、下段に前記パターンと
同一寸法のパターンを並列した状態で設け、前記同一寸
法のパターンを観察することにより、ＬＳＩ用縮小投影
露光装置の焦点が適正状態にあるか否かを検査すること
を特徴とするＬＳＩ用縮小投影露光装置の焦点検査方法
。(1) A process of providing steps on the substrate, providing patterns with sequentially different dimensions on the upper layer, and providing patterns with the same dimensions in parallel on the lower layer, and observing the patterns with the same dimensions to make the LSI 1. A focus inspection method for a reduction projection exposure apparatus for LSI, the method comprising inspecting whether the focus of the reduction projection exposure apparatus for LSI is in a proper state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1312968A JPH03173115A (en) | 1989-11-30 | 1989-11-30 | Inspecting method for focus of reduction projection exposure apparatus for lsi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1312968A JPH03173115A (en) | 1989-11-30 | 1989-11-30 | Inspecting method for focus of reduction projection exposure apparatus for lsi |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03173115A true JPH03173115A (en) | 1991-07-26 |
Family
ID=18035653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1312968A Pending JPH03173115A (en) | 1989-11-30 | 1989-11-30 | Inspecting method for focus of reduction projection exposure apparatus for lsi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03173115A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100241530B1 (en) * | 1996-12-28 | 2000-03-02 | 김영환 | Focus value correction method using multi-focal plane wafer for focus value correction of exposure equipment |
| US7436489B2 (en) | 2004-02-27 | 2008-10-14 | Powerchip Semiconductor Corp. | Device for testing an exposure apparatus |
-
1989
- 1989-11-30 JP JP1312968A patent/JPH03173115A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100241530B1 (en) * | 1996-12-28 | 2000-03-02 | 김영환 | Focus value correction method using multi-focal plane wafer for focus value correction of exposure equipment |
| US7436489B2 (en) | 2004-02-27 | 2008-10-14 | Powerchip Semiconductor Corp. | Device for testing an exposure apparatus |
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