JPH0317263B2 - - Google Patents
Info
- Publication number
- JPH0317263B2 JPH0317263B2 JP58152470A JP15247083A JPH0317263B2 JP H0317263 B2 JPH0317263 B2 JP H0317263B2 JP 58152470 A JP58152470 A JP 58152470A JP 15247083 A JP15247083 A JP 15247083A JP H0317263 B2 JPH0317263 B2 JP H0317263B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- electric field
- phase jitter
- value
- field level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005684 electric field Effects 0.000 claims description 30
- 238000005259 measurement Methods 0.000 claims description 11
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 8
- 238000005562 fading Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000008929 regeneration Effects 0.000 description 2
- 238000011069 regeneration method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000002277 temperature effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/34—Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
- H03G3/341—Muting when no signals or only weak signals are present
Landscapes
- Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Dc Digital Transmission (AREA)
- Radio Transmission System (AREA)
Description
【発明の詳細な説明】
本発明は、デジタル信号を受信する無線受信機
において、受信電界がある値より下つたことを判
断してスケルチ信号を発生するスケルチ信号発生
回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a squelch signal generation circuit that generates a squelch signal by determining that a received electric field has fallen below a certain value in a radio receiver that receives digital signals.
従来のスケルチ信号発生回路においては、受信
電界について、高周波アンプ、ミキサ、フイル
タ、中間周波アンプ等を経て、測定容易なレベル
にしてから、レベル測定回路により対応する電圧
値に変換し、さらに、一定の基準と比較して出力
する方法を用いていた。 In conventional squelch signal generation circuits, the received electric field is brought to a level that is easy to measure through a high frequency amplifier, mixer, filter, intermediate frequency amplifier, etc., then converted to a corresponding voltage value by a level measurement circuit, and then The method used was to compare and output the results with the standard.
しかしながら、この方法では、高周波部から、
中間周波部、そして、レベル測定回路までの各回
路のバラツキばかりでなく、温度等の環境条件に
よる変化が重複して重なるので、受信電界の測定
値には、非常に大きな誤差が生じることになる。
従つて、この測定値を一定の基準と比較する方法
では、正確にスケルチ信号が得られないという欠
点があつた。 However, in this method, from the high frequency part,
Not only variations in each circuit from the intermediate frequency section to the level measurement circuit, but also changes due to environmental conditions such as temperature overlap, resulting in extremely large errors in the measured value of the received electric field. .
Therefore, the method of comparing this measured value with a certain standard has the disadvantage that an accurate squelch signal cannot be obtained.
また、受信したデータの誤り率とは独立して、
単に電界強度のみに対応して、スケルチ判定を行
なつていたため、必ずしもスケルチ応答のあつた
時点が所定の誤り率に対応するとは限らず、受信
したデータの品質が良い場合にもスケルチ信号が
出されたり、あるいは、悪すぎる場合にも、スケ
ルチ信号が発せられない不具合が生じる事があつ
た。 Also, independent of the error rate of the received data,
Because the squelch judgment was made based solely on the electric field strength, the time point at which the squelch response occurred did not necessarily correspond to a predetermined error rate, and a squelch signal was generated even when the quality of the received data was good. In some cases, the squelch signal is not emitted when the squelch signal is not emitted.
本発明の目的は、以上述べた従来の欠点を除去
し、精度の良いスケルチ信号を得る事ができるス
ケルチ信号発生回路を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a squelch signal generation circuit that eliminates the above-mentioned conventional drawbacks and can obtain a highly accurate squelch signal.
本発明では測定した電界強度を、受信したデー
タの位相ジツタ量に換算した値に対応させ、位相
ジツタがある値以上となる様な電界強度に対して
スケルチ信号を発生する方法を用いる。 In the present invention, a method is used in which the measured electric field strength is made to correspond to a value converted to the amount of phase jitter of received data, and a squelch signal is generated for the electric field strength such that the phase jitter exceeds a certain value.
本発明によれば、受信信号の電界のレベルを測
定する電界レベル測定回路、前記受信信号からベ
ースバンド信号を復調する復調器、前記復調器出
力のベースバンド信号に含まれる位相ジツタを測
定する位相ジツタ測定回路、前記位相ジツタ測定
回路によつて測定された位相ジツタが指定の値に
達したか否かを判断する判断回路、前記測定され
た位相ジツタが前記指定の値に達したと、前記判
断回路が判断した時、前記電界レベル測定回路に
よつて測定された電界レベルを記憶する記憶回路
を有し、前記電界レベル測定回路によつて測定さ
れた電界レベルが、前記記憶回路の内容に比べて
低いときに、スケルチ信号を発生する事を特徴と
するスケルチ信号発生回路が得られる。 According to the present invention, there is provided an electric field level measurement circuit that measures the electric field level of a received signal, a demodulator that demodulates a baseband signal from the received signal, and a phase jitter that measures phase jitter included in the baseband signal output from the demodulator. a jitter measuring circuit; a determining circuit for determining whether the phase jitter measured by the phase jitter measuring circuit has reached a specified value; When the determination circuit makes a determination, the determination circuit includes a storage circuit that stores the electric field level measured by the electric field level measurement circuit, and the electric field level measured by the electric field level measurement circuit is stored in the contents of the storage circuit. A squelch signal generation circuit is obtained which is characterized in that it generates a squelch signal when the squelch signal is relatively low.
以下、図面を参照して本発明を詳細に説明す
る。 Hereinafter, the present invention will be explained in detail with reference to the drawings.
第１図は本発明の一実施例に係るスケルチ信号
発生回路を示す図である。第１図において、１は
受信信号の電界Ｅの強さを測定する電界レベル測
定回路で、受信電界Ｅに比例した電圧x1を出力す
る。２は受信信号の中間周波IFよりベースバン
ド信号x2を得る復調器、３はベースバンド信号x2
より位相ジツタを測定する位相ジツタ測定回路、
４は位相ジツタが指定の値に達したか否か判断す
る判断回路である。 FIG. 1 is a diagram showing a squelch signal generation circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an electric field level measuring circuit that measures the strength of the electric field E of the received signal, and outputs a voltage x 1 proportional to the received electric field E. 2 is a demodulator that obtains baseband signal x 2 from the intermediate frequency IF of the received signal, 3 is baseband signal x 2
A phase jitter measurement circuit that measures phase jitter,
Reference numeral 4 denotes a determination circuit that determines whether the phase jitter has reached a specified value.
５は判断回路４の出力x4に従つて、電界情報x1
を記憶する回路であり、記憶された値x5はベース
バンド信号x2の位相ジツタが指定の値に達した時
点でのx1の値に相当する。記憶回路５は、トラン
スフアー・ゲート１４とコンデンサC4とを有す
る。 5 is the electric field information x 1 according to the output x 4 of the judgment circuit 4
The stored value x5 corresponds to the value of x1 at the time when the phase jitter of the baseband signal x2 reaches a specified value. Memory circuit 5 includes a transfer gate 14 and a capacitor C4 .
記憶回路５に値x5が記憶されてからは、比較器
６によりx1をx5と比較してスケルチ信号Ｓを得て
いる。 After the value x 5 is stored in the memory circuit 5, the comparator 6 compares x 1 with x 5 to obtain the squelch signal S.
ここで、電界情報x1を比較する値x5は受信デー
タのジツタ量と対応しているため、精度の良い結
果が得られる。この事を、第１図の各部の波形の
タイムチヤートを示した第２図をも参照して説明
する。 Here, since the value x5 with which the electric field information x1 is compared corresponds to the amount of jitter in the received data, highly accurate results can be obtained. This will be explained with reference to FIG. 2, which shows a time chart of waveforms at various parts in FIG. 1.
第２図において、スケルチ信号Ｓは電界情報x1
が比較値x5より下つた時点で発生している。x3は
位相ジツタの測定値である。判断回路４におい
て、x3が、指定の値VDより上がつた時点で、比
較器１２がパルスx12を出力して、排他的論理和
回路１３が、x12の変化する時点で幅の狭いパル
スx4を出力している。すなわち、x4のパルスが発
生するのはx3が指定値VDをクロスする時である。 In Fig. 2, the squelch signal S is electric field information x 1
This occurs when the value falls below the comparison value x 5 . x 3 is the measured value of phase jitter. In the judgment circuit 4, when x 3 rises above the specified value V D , the comparator 12 outputs the pulse x 12, and the exclusive OR circuit 13 outputs the pulse x 12 at the point when x 12 changes. Outputs narrow pulse x 4 . That is, the x 4 pulse is generated when x 3 crosses the specified value V D.
x5の値はx4のパルスが発生した時点のx1の値で
ある。十分カツトオフの低いx3を得るために、位
相ジツタ測定回路３内にフイルタR2，C2が入つ
ている。このため、x3はゆつくり変動している。
すなわち、フエージング速度が十分遅い時点で、
位相ジツタが指定の値まで大きくなつた時の電界
情報x1が比較基準値x5として読み込まれる。 The value of x 5 is the value of x 1 at the time the pulse of x 4 occurs. In order to obtain x 3 with a sufficiently low cutoff, filters R 2 and C 2 are included in the phase jitter measuring circuit 3. Therefore, x 3 fluctuates slowly.
In other words, when the fading speed is slow enough,
The electric field information x1 when the phase jitter increases to a specified value is read as the comparison reference value x5 .
ここで、x5の値は次の様な性質を持つている。
x1の測定値には、温度変化あるいは、x1を得るた
めのフイルタ、アンプ等回路のバラツキによつ
て、レベル測定誤差xeがあつたとする。また、x5
に対する電界測定の理想値をxEとすると、x1＝xE
＋xeなる関係がある。ここで、x5の値としては理
想値をxEDとしたときに対して、誤差分xeも含ん
で、x5＝xED＋xeの値として読み込まれる。例え
ば、温度が変化したためx1の値がΔx1＝Δxeだけ
ずれたとすると、これを遅いフエージングのとき
に、x5も読み込んでしまうため、x5の値もΔx5＝
Δxeだけずれる。 Here, the value of x 5 has the following properties.
Assume that there is a level measurement error x e in the measured value of x 1 due to temperature changes or variations in circuits such as filters and amplifiers used to obtain x 1 . Also x 5
Let x E be the ideal value for electric field measurement, then x 1 = x E
There is a relationship called +x e . Here, the value of x 5 is read as the value x 5 = x ED + x e , including the error x e with respect to the ideal value x ED . For example, if the value of x 1 deviates by Δx 1 = Δx e due to a change in temperature, then during slow fading, x 5 will also be read, so the value of x 5 will also become Δx 5 =
deviates by Δx e .
従つて、x1をx5に対して比較する事はxEをxED
と比較する事を意味するため、得られたスケルチ
信号Ｓには、誤差分xeが打ち消し合つて出力され
る。 Therefore, comparing x 1 to x 5 means x E to x ED
Since this means comparing with , the obtained squelch signal S is outputted after the error x e cancels each other out.
また、さらに、x5は受信データの位相ジツタ量
に対応している。位相ジツタ量は受信したときの
データの誤り率に強い相関があり、ジツタ量があ
る値に達すれば、誤り率もこの時に、ほぼ定まつ
た値を有する。この事はx5の値が、受信データの
誤り率をほぼ正確に表現している事を意味し、x1
がx5の値に達した時点でスケルチ応答させれば、
正確に受信データの誤り率に対応したスケルチ信
号が得られる事を意味する。また、第２図に示さ
れる様に、x3はゆつくり変化して、低速フエージ
ングに対して測定されるが、これはx3を得るのに
時間をかけて正確に判断している事を意味する。
高速フエージングに対して、瞬時のものであれば
x3は応答しないが、x5が定まつた値に達していれ
ば、x1の速い応答に対してスケルチ信号Ｓを得る
事が出来る。 Furthermore, x 5 corresponds to the amount of phase jitter of the received data. The amount of phase jitter has a strong correlation with the error rate of data when received, and if the amount of jitter reaches a certain value, the error rate also has a substantially fixed value at this time. This means that the value of x 5 almost accurately represents the error rate of the received data, and x 1
If you make a squelch response when reaches the value of x 5 ,
This means that a squelch signal that accurately corresponds to the error rate of received data can be obtained. Also, as shown in Figure 2, x 3 changes slowly and is measured against slow fading, but this means that it takes time to accurately judge x 3 . means.
For fast fading, if it is instantaneous
Although x 3 does not respond, if x 5 reaches a predetermined value, a squelch signal S can be obtained for the fast response of x 1 .
次に、第１図の位相ジツタ測定回路３について
説明する。第３図は位相ジツタ測定回路３の動作
を説明するタイムチヤートである。(a)は受信電界
が十分な場合であり、(b)は不十分な場合である。 Next, the phase jitter measuring circuit 3 shown in FIG. 1 will be explained. FIG. 3 is a time chart illustrating the operation of the phase jitter measuring circuit 3. (a) is the case where the received electric field is sufficient, and (b) is the case where it is insufficient.
復調出力x2は、電界が十分なときには、雑音が
含まれないが、不十分なときには雑音により変動
する。x7は比較器７によりx2を比較した結果であ
る。位相面は(a)の場合に安定し、(b)の場合に不安
定になつている。x7の変化について、R1，C1お
よび排他的論理和回路９を用いて幅の狭いパルス
x9を得ている。x9を使つて、高速クロツクfHをカ
ウントしているカウンタ１０をリセツトしてパル
ス列x10を得る。x10としては、x2のデータ速度に
相当するクロツク周波数を選ぶ様にカウンタ１０
の分周比を設定する。x10は受信データの位相ジ
ツタに直接関連している。 The demodulated output x 2 contains no noise when the electric field is sufficient, but fluctuates due to noise when the electric field is insufficient. x 7 is the result of comparing x 2 by comparator 7. The phase front is stable in case (a) and unstable in case (b). For changes in x 7 , narrow pulses are generated using R 1 , C 1 and exclusive OR circuit 9.
You're getting x9 . x 9 is used to reset the counter 10 counting the high speed clock f H to obtain a pulse train x 10 . x 10 , the counter 10 selects the clock frequency corresponding to the data rate x 2 .
Set the division ratio. x 10 is directly related to the phase jitter of the received data.
他方、x7を、ジツタ分を抑圧したクロツク再生
回路８へ入力し、安定したクロツクx8を得る。x8
とx10を排他的論理和回路１１へ入力すると、出
力x11は両者が一致するとき“０”、不一致のとき
“１”を出力する。x11のパルス幅は受信データの
位相ジツタに比例する。x11をカツトオフの十分
低いフイルタR2，C2へ入力して、x3を得る。x3
の振幅（ΔV）はジツタ量に比例する。 On the other hand, x 7 is input to a clock regeneration circuit 8 in which jitter is suppressed to obtain a stable clock x 8 . x8
When and x10 are input to the exclusive OR circuit 11, the output x11 outputs "0" when the two match, and "1" when they do not match. The pulse width of x 11 is proportional to the phase jitter of the received data. Input x 11 to filters R 2 and C 2 with sufficiently low cutoff to obtain x 3 . x3
The amplitude (ΔV) of is proportional to the amount of jitter.
以上の第３図において、R1，C1の値はカウン
タ１０をリセツトするのに十分細いパルスx9を得
るために使われ、R1，C1とも約２倍位に大きく
ばらついたとしても波形x10に影響はない。また、
R2，C2の値も、十分遅いフエージング時に動作
すれば良いので、カツトオフの誤差範囲として、
かなり大きな値が許され、部品のバラツキ、ある
いは温度の影響によつて変化しても、静的な状態
でのx3の値には悪影響がない。以上の様にして、
位相ジツタに対応する電圧は正確に得られる。 In Fig. 3 above, the values of R 1 and C 1 are used to obtain a sufficiently thin pulse x 9 to reset the counter 10, and even if both R 1 and C 1 vary greatly by about twice Waveform x 10 is not affected. Also,
The values of R 2 and C 2 only need to operate during sufficiently slow fading, so as the cutoff error range,
Quite large values are allowed, and changes due to component variations or temperature effects will not adversely affect the value of x 3 in static conditions. As above,
The voltage corresponding to the phase jitter can be obtained accurately.
以上説明した様に、本発明のスケルチ信号発生
回路を用いれば、受信データの誤り率に対応する
スケルチ信号を正確に得る事が出来る。 As explained above, by using the squelch signal generation circuit of the present invention, it is possible to accurately obtain a squelch signal corresponding to the error rate of received data.
第１図は本発明のスケルチ信号発生回路の一実
施例を示す図、第２図は第１図の動作原理を説明
するためのタイムチヤート、第３図は第１図中に
使われている位相ジツタ測定回路３のタイムチヤ
ートである。
１……電界レベル測定回路、２……復調器、３
……位相ジツタ測定回路、４……判断回路、５…
…記憶回路、６，７及び１２……比較器、８……
クロツク再生回路、９，１１及び１３……排他的
論理和回路、１０……カウンタ、１４……トラン
スフアー・ゲート。
Fig. 1 is a diagram showing an embodiment of the squelch signal generation circuit of the present invention, Fig. 2 is a time chart for explaining the operating principle of Fig. 1, and Fig. 3 is used in Fig. 1. This is a time chart of the phase jitter measuring circuit 3. 1... Electric field level measurement circuit, 2... Demodulator, 3
... Phase jitter measurement circuit, 4 ... Judgment circuit, 5 ...
...Storage circuit, 6, 7 and 12...Comparator, 8...
Clock regeneration circuit, 9, 11 and 13...exclusive OR circuit, 10...counter, 14...transfer gate.
Claims (1)
ル測定回路、前記受信信号からベースバンド信号
を復調する復調器、前記復調器出力のベースバン
ド信号に含まれる位相ジツタを測定する位相ジツ
タ測定回路、前記位相ジツタ測定回路によつて測
定された位相ジツタが指定の値に達したか否かを
判断する判断回路、前記測定された位相ジツタが
前記指定の値に達したと、前記判断回路が判断し
た時、前記電界レベル測定回路によつて測定され
た電界レベルを記憶する記憶回路を有し、前記電
界レベル測定回路によつて測定された電界レベル
が、前記記憶回路の内容に比べて低いときに、ス
ケルチ信号を発生する事を特徴とするスケルチ信
号発生回路。1. An electric field level measuring circuit that measures the electric field level of a received signal, a demodulator that demodulates a baseband signal from the received signal, a phase jitter measuring circuit that measures phase jitter included in the baseband signal output from the demodulator, and A determination circuit that determines whether the phase jitter measured by the phase jitter measurement circuit has reached a specified value, and the determination circuit determines that the measured phase jitter has reached the specified value. and a storage circuit for storing the electric field level measured by the electric field level measuring circuit, and when the electric field level measured by the electric field level measuring circuit is lower than the content of the storage circuit. , a squelch signal generation circuit characterized by generating a squelch signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58152470A JPS6046155A (en) | 1983-08-23 | 1983-08-23 | Squelch signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58152470A JPS6046155A (en) | 1983-08-23 | 1983-08-23 | Squelch signal generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6046155A JPS6046155A (en) | 1985-03-12 |
| JPH0317263B2 true JPH0317263B2 (en) | 1991-03-07 |
Family
ID=15541215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58152470A Granted JPS6046155A (en) | 1983-08-23 | 1983-08-23 | Squelch signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6046155A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5408693A (en) * | 1991-12-24 | 1995-04-18 | Motorola, Inc. | Muting of radio-transmitter digital audio based on received signal strength |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5497311A (en) * | 1978-01-19 | 1979-08-01 | Nec Corp | Rodio transmitter-receiver |
| JPS55145461A (en) * | 1979-04-27 | 1980-11-13 | Nec Corp | Digital signal/noise ratio monitoring device |
-
1983
- 1983-08-23 JP JP58152470A patent/JPS6046155A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5497311A (en) * | 1978-01-19 | 1979-08-01 | Nec Corp | Rodio transmitter-receiver |
| JPS55145461A (en) * | 1979-04-27 | 1980-11-13 | Nec Corp | Digital signal/noise ratio monitoring device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6046155A (en) | 1985-03-12 |
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