JPS6025959U - Automatic sensitivity correction device for eddy current flaw detection - Google Patents
Automatic sensitivity correction device for eddy current flaw detectionInfo
- Publication number
- JPS6025959U JPS6025959U JP8469284U JP8469284U JPS6025959U JP S6025959 U JPS6025959 U JP S6025959U JP 8469284 U JP8469284 U JP 8469284U JP 8469284 U JP8469284 U JP 8469284U JP S6025959 U JPS6025959 U JP S6025959U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- sensitivity correction
- signal
- flaw detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Investigating Or Analyzing Materials By The Use Of Magnetic Means (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来の渦流探傷装置が配設された電縫鋼管製
造ラインの一部を示すブロック線図、第２図は、前記渦
流探傷装置における検出信号波形の一例を示す線図、第
３図は、本考案に係る渦流探傷装置の実施例の全体構成
を示すブロック線図、第４図は、前記実施例における自
動感度補正装置の構成例を示すブロック線図、第５図は
、前記自動感度補正装置のウィンドコンパレータの構成
例を示すブロック線図、第６図は、同じく前記自動感度
補正装置のデジタル減衰器の構成例を示す回路図、第７
図は、前記自動感度補正装置の動作を示す流れ図、第８
図は、前記自動感度補正装置の各部動作波形を示す線図
、第９図は、前記実施例における記録計上の表示状態を
示す線図である。
１２・・・探傷コイル、２１・・・発振器、２２・・・
平衡回路、２４・・・増幅器、２６・・・探傷感度調整
器、２−８・・・位相検波器、３０・・・位相器、３２
・・・フィルタ−、３４・・・リジェクタ−１３６・・
・自動感度補正装置、３８・・・直流増幅器、４０・・
・記録計、５０・・・ピークホールド回路、５２・・・
ウィンドコンパレータ、５４・・・クロックパルス発振
器、５６・・・ピーク検出回路、５８，６０．６２・・
・ＡＮＤ回路、６４・・・アップダウンカウンタ、６６
・・・デジタル減衰器、６８・・・設定−探傷切替スイ
ッチ。FIG. 1 is a block diagram showing a part of an ERW steel pipe production line in which a conventional eddy current flaw detection device is installed, and FIG. 2 is a line diagram showing an example of a detection signal waveform in the eddy current flaw detection device. FIG. 3 is a block diagram showing the overall configuration of an embodiment of the eddy current flaw detection device according to the present invention, FIG. 4 is a block diagram showing an example of the configuration of the automatic sensitivity correction device in the embodiment, and FIG. FIG. 6 is a block diagram showing a configuration example of a window comparator of the automatic sensitivity correction device, and FIG. 7 is a circuit diagram showing a configuration example of a digital attenuator of the automatic sensitivity correction device.
FIG. 8 is a flow chart showing the operation of the automatic sensitivity correction device.
The figure is a diagram showing the operation waveforms of each part of the automatic sensitivity correction device, and FIG. 9 is a diagram showing the display state of the recorder in the embodiment. 12... Flaw detection coil, 21... Oscillator, 22...
Balance circuit, 24... Amplifier, 26... Flaw detection sensitivity adjuster, 2-8... Phase detector, 30... Phase shifter, 32
...filter, 34...rejector-136...
・Automatic sensitivity correction device, 38...DC amplifier, 40...
・Recorder, 50...Peak hold circuit, 52...
Window comparator, 54... Clock pulse oscillator, 56... Peak detection circuit, 58, 60.62...
・AND circuit, 64...up/down counter, 66
...Digital attenuator, 68...Setting-flaw detection changeover switch.
Claims (1)
に対応する検出信号出力が、予め設定された指示値と一
致するよう探傷感度の補正を行なう渦流探傷の感度補正
装置において、対比試験片を探傷した際の人工欠陥検出
信号出力の最大値を保持するピークホールド回路と、該
ピークホールド回路に保持されている値が最大値である
ことを検出するピーク検出回路と、クロックパルス発振
器と、探傷感度を入力される感度補正信号に応じて所定
量変更するデジタル減衰器と、該デジタル減衰器により
減衰された前記ピークホールド回路出力の最大値を、予
め設定された指示値の上下限値と比較して、上限値以上
のとき減算指令信号を、下限値以下のとき加算指令信号
を、上下限値間のとき設定完了信号を出力するウィンド
コンパレータと、前記ピーク検出回路の出力と前記クロ
ックパルス発振器の出力との論理積を出力する第１のＡ
ＮＤ回路と、該ＡＮＤ回路出力と前記減算指令信号およ
び前記加算指令信号との論理積をそれぞれ出力する第２
および第３のＡＮＤ回路と、該第２および第３のＡＮＤ
回路から出力される減算および加算信号を計数積算し、
前記デジタル減衰器の感度補正信号として出力するアッ
プダウンカウンタとを設けるとともに、前記ピークホー
ルド回路は前記設定完了信号によりリセットされるもの
とにし、前記アップダウンカウンタは当該カウンタの計
数範囲内に積算しきれなかったときに設定不能警報を出
力するものとしたことを特徴とする渦流探傷の感度自動
補正装置。Comparative testing is performed in an eddy current flaw detection sensitivity correction device that detects a comparative test piece in which an artificial defect is formed and corrects the detection sensitivity so that the detection signal output corresponding to the artificial defect matches a preset indication value. A peak hold circuit that holds the maximum value of the artificial defect detection signal output when a piece is inspected, a peak detection circuit that detects that the value held in the peak hold circuit is the maximum value, and a clock pulse oscillator. , a digital attenuator that changes the flaw detection sensitivity by a predetermined amount according to an input sensitivity correction signal, and a maximum value of the peak hold circuit output attenuated by the digital attenuator, which is set as an upper and lower limit of a preset indication value. a window comparator that outputs a subtraction command signal when the upper limit is exceeded, an addition command signal when the lower limit is below, and a setting completion signal when between the upper and lower limits; and the output of the peak detection circuit and the clock. A first A that outputs a logical product with the output of the pulse oscillator.
an ND circuit, and a second circuit that outputs a logical product of the AND circuit output, the subtraction command signal, and the addition command signal, respectively.
and a third AND circuit, and the second and third AND circuits.
The subtraction and addition signals output from the circuit are counted and integrated,
An up/down counter is provided to output as a sensitivity correction signal of the digital attenuator, and the peak hold circuit is reset by the setting completion signal, and the up/down counter is configured to integrate within a counting range of the counter. An automatic sensitivity correction device for eddy current flaw detection, characterized in that a setting failure alarm is output when the sensitivity cannot be set.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8469284U JPS6025959U (en) | 1984-06-07 | 1984-06-07 | Automatic sensitivity correction device for eddy current flaw detection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8469284U JPS6025959U (en) | 1984-06-07 | 1984-06-07 | Automatic sensitivity correction device for eddy current flaw detection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6025959U true JPS6025959U (en) | 1985-02-21 |
| JPS6116524Y2 JPS6116524Y2 (en) | 1986-05-21 |
Family
ID=30214660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8469284U Granted JPS6025959U (en) | 1984-06-07 | 1984-06-07 | Automatic sensitivity correction device for eddy current flaw detection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6025959U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011149838A (en) * | 2010-01-22 | 2011-08-04 | Japan Atom Power Co Ltd:The | Internal defect evaluation method by eddy current method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5463766B2 (en) * | 2009-07-10 | 2014-04-09 | Ｊｆｅスチール株式会社 | Method for evaluating the workability of forged pipes |
-
1984
- 1984-06-07 JP JP8469284U patent/JPS6025959U/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011149838A (en) * | 2010-01-22 | 2011-08-04 | Japan Atom Power Co Ltd:The | Internal defect evaluation method by eddy current method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6116524Y2 (en) | 1986-05-21 |
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