JPH03171883A - Solid-state image pickup device - Google Patents

Solid-state image pickup device

Info

Publication number
JPH03171883A
JPH03171883A JP2011282A JP1128290A JPH03171883A JP H03171883 A JPH03171883 A JP H03171883A JP 2011282 A JP2011282 A JP 2011282A JP 1128290 A JP1128290 A JP 1128290A JP H03171883 A JPH03171883 A JP H03171883A
Authority
JP
Japan
Prior art keywords
potential
source region
charge
circuit element
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011282A
Other languages
Japanese (ja)
Other versions
JPH0549152B2 (en
Inventor
Yutaka Miyata
豊 宮田
Takao Chikamura
隆夫 近村
Takuo Shibata
柴田 卓夫
Shinji Fujiwara
慎司 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP485980A external-priority patent/JPS56102169A/en
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2011282A priority Critical patent/JPH03171883A/en
Publication of JPH03171883A publication Critical patent/JPH03171883A/en
Publication of JPH0549152B2 publication Critical patent/JPH0549152B2/ja
Granted legal-status Critical Current

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Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To prevent burning or flicker from being generated by increasing the potential of a channel area higher than a block potential between a source area under the gate electrode of an MOSFET and a circuit element. CONSTITUTION:A control pulse is impressed to a gate electrode 13. The polarity of this pulse is reverse to the polarities of transfer and read pulses and the block potential of a read part for a signal charge positioning just under the gate electrode 13 is made higher than that of the other part on a substrate, namely, higher than the block potential just under a source area 11. Therefore, the excess charge flowing out to a substrate 10 in a regular bias state is not read into the area 12 in a transfer step and an unnecessary pseudo signal is not outputted. Thus, the output of the unnecessary pseudo signal caused by the excess charge and latent image are prevented form being generated.

Description

【発明の詳細な説明】 本発明は、,固体撮像装置に関するもので、半導体基板
上に、電荷走査機能を有する回路素子と入射光により生
じる信号電荷を蓄積するソース領域(以下余白) 明細書の浄書(内容に変更なし) を形或した固体撮像素子において、上記ソース領域中の
余分な過剰電荷のみを半導体基板側に確実に流出させ、
走査回路部における電荷のオーバーフローや残像のない
固体撮像装置を提供するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device, in which a circuit element having a charge scanning function and a source region (hereinafter referred to as a blank space) that accumulates signal charges generated by incident light are provided on a semiconductor substrate. In a solid-state image sensor in the form of an engraving (no change in content), only the excess charge in the source region is reliably drained to the semiconductor substrate side,
The object of the present invention is to provide a solid-state imaging device that is free from charge overflow and afterimage in a scanning circuit section.

従来、電荷走査機能を有する固体撮像板には種種のもの
があるが、特に雑音の少ない電荷転送機能を有するもの
としては、CCD−iたはBBD等の自己走査機能をも
つ回路素子が提案されている(特開昭61−95721
号参照)。
Conventionally, there are various types of solid-state image pickup plates having a charge scanning function, but circuit elements with a self-scanning function such as CCD-i or BBD have been proposed as those having a charge transfer function with particularly low noise. (Japanese Unexamined Patent Publication No. 61-95721
(see issue).

しかしながら、上記のようなh或において、COD又は
BBDで構或される電荷転送段の取扱い電荷量が、入射
光によシ生成されソース領域に蓄積される電荷量よシ少
ない場合、強い入射光によシ生戒された過剰電荷は走査
回路部でオーバーフローが生じたシ光電変換部に印加さ
れる電圧が制限をうけ、焼きっけやフリッカ等が生じて
いた。
However, in some cases as described above, if the amount of charge handled by the charge transfer stage composed of COD or BBD is smaller than the amount of charge generated by incident light and accumulated in the source region, strong incident light The excess charge caused by overflow caused by overflow in the scanning circuit section caused the voltage applied to the photoelectric conversion section to be restricted, causing burnout and flickering.

本発明は、半導体基板に信号電荷を蓄積するソース領域
を設け、基板とソース領域でダイオードを形成し、この
ダイオードに電荷転送機能を有す明細書の浄書(内容に
変更なし) る回路素子の取扱い電荷量よシも多い信号電荷が生或し
たとき、ソース領域の電荷の回路素子への読み込みを防
止しつつダイオードを順バイアス状態とし、光電変換部
で生ずる余分な過剰電荷をンーヌ領域下の半導体基板に
流出させることによう、オーバーフローによる不要信号
の転送部へのもれによる疑似信号の発生ならびに残像等
の生じない固体撮像装置を提供するものである。
The present invention provides a circuit element in which a source region for accumulating signal charges is provided on a semiconductor substrate, a diode is formed by the substrate and the source region, and this diode has a charge transfer function. When a signal charge larger than the amount of charge to be handled is generated, the diode is put into a forward bias state while preventing the charge in the source region from being read into the circuit elements, and the excess charge generated in the photoelectric conversion section is transferred to the bottom of the non-nu region. It is an object of the present invention to provide a solid-state imaging device that does not generate false signals or afterimages due to unnecessary signals leaking to a transfer section due to overflow.

以下図面に従って本発明の一実施例にかかる固体撮像装
置を説明する。走査回路としては雑音の少ない電荷転送
型で説明する。電荷転送型としてのCOD又はBBDは
、電荷の蓄積が空乏層か、不純物領域かの差はあるが、
動作は本質的に同一である。従って今後BBDにて説明
する。
A solid-state imaging device according to an embodiment of the present invention will be described below with reference to the drawings. The scanning circuit will be explained using a charge transfer type which has less noise. COD or BBD as a charge transfer type differs in whether charge is accumulated in a depletion layer or an impurity region, but
The operation is essentially the same. Therefore, this will be explained in the future on BBD.

第1図は、Si基板上に形或したBBDとその転送段を
ドレインとじゲー}[!とソース領域を設けこれらの領
域上に光導電体と電極を形威した固体撮像装置の一単位
を示したものである。
Figure 1 shows a BBD formed on a Si substrate and its transfer stage connected to the drain. This figure shows one unit of a solid-state imaging device in which a photoconductor and an electrode are provided on these regions.

p型半導体基板10にソース領域となるn+型領域11
を形戒しダイオードを設ける。12はn+明nJ占の浄
a(内容に変更なし) 型領域で電位の井戸であbSt荷転送回路素子となる。
An n+ type region 11 serving as a source region is formed in a p-type semiconductor substrate 10.
A diode is provided to prevent this. 12 is a potential well in the n+A (no change in content) type region of nJ and becomes a bSt charge transfer circuit element.

13はゲー}[極であシ、n+型領域11と重なり部分
を有している。14は、半導体基板10とゲート電極1
3との間の絶縁体膜で、ゲート酸化膜である。16は、
第一t極16と半導体基板10訃よびゲート電1i13
とをN.気的に分離するための絶縁体層である。16は
第一電極で、n+型領域11と電気的に接続したダイオ
ードの電極であるとともに正孔阻止層17の電極ともな
っている。18は、(Zn1,Cd,To)1−y(I
n2To3),(ただしo(x(1,o(y≦0.3)
よシなる光導電体であシ、その上に透明電極(第二電極
)19が形威されておシ、透明電極19側よシ入射光わ
が照射される。
13 is a gate electrode and has an overlapping portion with the n+ type region 11. 14 is a semiconductor substrate 10 and a gate electrode 1
This is an insulator film between the gate electrode 3 and the gate oxide film. 16 is
First t-pole 16, semiconductor substrate 10 and gate electrode 1i13
and N. This is an insulating layer for gas separation. Reference numeral 16 denotes a first electrode, which is an electrode of a diode electrically connected to the n+ type region 11 and also serves as an electrode of the hole blocking layer 17. 18 is (Zn1, Cd, To)1-y(I
n2To3), (where o(x(1, o(y≦0.3)
A transparent electrode (second electrode) 19 is formed on the photoconductor, and incident light is irradiated from the side of the transparent electrode 19.

オず本発明を用いない場合の光情報読み込み動について
説明する。
First, the optical information reading operation when the present invention is not used will be explained.

上記第1図の構或に釦いて、第2図(.)に示すような
駆動パルスをゲー}[m13に印加する。時間t7に釦
いて電極16は、第2図(b)に示した如く(vcH−
vT)に設定される。ここでvTは、n+明IIB*の
浄書(内容に変更なし) 領域11,12訃よびゲートtFM13よb構或される
MOS型電界効果型トランジスタ( FET )のしき
い値電圧である。今入射光21があると光導電体18に
おいて電子・正孔対が生威し、それぞれ電Wi1 6 
j 1 9に到達してソース領域10に信号電荷が蓄積
され電極16の電位が低下する。
Pressing the button in the configuration shown in FIG. 1 above, a drive pulse as shown in FIG. 2 (.) is applied to the gate [m13]. At time t7, the button is pressed and the electrode 16 is turned on (vcH-
vT). Here, vT is the threshold voltage of a MOS field effect transistor (FET) constructed of n+IIB* (no change in content) regions 11, 12 and gate tFM13. Now, when there is incident light 21, electron-hole pairs are generated in the photoconductor 18, and each electric current Wi1 6
j 1 9, signal charges are accumulated in the source region 10, and the potential of the electrode 16 decreases.

さらに時間t2においてゲート電極13にvcHを印加
するとn+領域11からn+領域12に信号電荷の移送
が行なわれる。その結果n+ 領域11の電位は再び上
昇し(vCH−vT)となる。n+ 領域12に移送さ
れた信号電荷は、その後第2図(a)に示した転送パル
スv0によう出力部へ転送される。
Furthermore, when vcH is applied to gate electrode 13 at time t2, signal charges are transferred from n+ region 11 to n+ region 12. As a result, the potential of n+ region 11 rises again to (vCH-vT). The signal charge transferred to the n+ region 12 is then transferred to the output section in accordance with the transfer pulse v0 shown in FIG. 2(a).

以上が本発明を用いない場合の光情報読み込み動作であ
う、光導電体に印加される電圧は、第二電極19を接地
電位に保った場合(vcH−vT)となる。
The above is the optical information reading operation when the present invention is not used, and the voltage applied to the photoconductor is when the second electrode 19 is kept at the ground potential (vcH-vT).

しかしながら、転送回路素子であるCCD−1たはBB
Dで構或される電荷転送段の取扱い電荷量が光電変換部
である光導電体で生成する最大電荷明細書の浄書(内容
に変更なし) 量よシ少ない場合、光導電体に印加する電圧を小さくす
るしかなく、そうすると焼きっけ、フリッカ等が生じる
。一方、光導電体に十分な電圧を印加すると、一回の読
み込み動作では信号を読み込むことができず、発生した
過剰電荷(オーバーフロー電荷)が転送段にもれ込み、
不要な信号が出力され、残像も生じる。
However, the transfer circuit element CCD-1 or BB
If the amount of charge handled by the charge transfer stage constituted by D is less than the maximum charge specification generated by the photoconductor which is the photoelectric conversion unit (no change in content), the voltage to be applied to the photoconductor. There is no choice but to make it smaller, but doing so will result in burnt-out, flicker, etc. On the other hand, if a sufficient voltage is applied to the photoconductor, the signal cannot be read in one reading operation, and the generated excess charge (overflow charge) leaks into the transfer stage.
Unnecessary signals are output and afterimages also occur.

次に本発明の過剰電荷の流出の一例としての動作を説明
する。第3図は、半導体基板とソース領域で形或される
ダイオードを、順バイアス状態にし不要な電荷の読み込
みを生ずることなく基板に過剰電荷を流出させる方法の
一例として、第二電極19へのパルス印加およびゲート
wL極への制御、パルスを利用する方法を示したもので
ある。時間T1 において入射光による過剰電荷(転送
取扱い電荷量ようも多い生成電荷)が発生しダイオード
電位がVc以下になった場合、第二電lfA19に印加
する外部電圧すなわち負のパルス(−vc′)によりダ
イオード電位(ソース領域11の電位)は、基板に対し
てVc分負に引き下げられ順バイアス明細書の浄書(内
容に変更なし) 状態となシ、基板と同電位(接地電位)になるまで電荷
が基板に流出する。
Next, the operation of the present invention as an example of draining excess charge will be described. FIG. 3 shows a pulse applied to the second electrode 19 as an example of a method for forward biasing a diode formed by a semiconductor substrate and a source region and draining excess charge to the substrate without causing unnecessary charge loading. This shows a method of applying and controlling the gate wL pole and using pulses. At time T1, if excess charge (generated charge with a large amount of transferred charge) is generated due to the incident light and the diode potential becomes below Vc, the external voltage applied to the second voltage lfA19, that is, the negative pulse (-vc') As a result, the diode potential (potential of the source region 11) is pulled down to a negative value of Vc with respect to the substrate until it becomes the same potential as the substrate (ground potential). Charge flows out to the substrate.

このとき、ゲートi[m13には第3図(.)に示され
る制御パルス30が印加される。このバルス30は、転
送釦よびリードパルスとは逆極性であシ、当然ゲート電
極13直下に位置する信号電荷の読み込み部の障壁電位
が、基板の他の部分すなわちソース領域11直下の障壁
電位よシも高くなる。
At this time, a control pulse 30 shown in FIG. 3(.) is applied to the gate i[m13. This pulse 30 has a polarity opposite to that of the transfer button and the read pulse, and naturally the barrier potential of the signal charge reading portion located directly below the gate electrode 13 is higher than that of the other portion of the substrate, that is, the barrier potential directly below the source region 11. Shi will also be higher.

このような手段によシ、順バイアス状態で基板1oに流
出した過剰電荷は転送段の領域12には読み込1れす、
不要な疑似信号は出力されない。こうした流出の後、第
二電極19のパルスがoVに戻るとダイオード電位は、
vcに設定され、その後リートパk ,X Ic J:
シl(vCH−vT)−V(Hlo電位K相当する信号
電荷が転送段である領域12に読み込1れる。時間T1
 においてダイオード電位がVc以上の場合すなわち転
送取扱い電荷量以下の信号電荷の場合には、第二!極の
パルスによって、OV以下にはならず、ダイオードは順
バイアスとはならない。従ってダイオード電位がVc以
上の場明細書の浄長(内容に変更なし) 合、光情報は入射光強度に比例するが、vc以下の場合
、すなわち入射光強度がよb強い場合には、転送段に不
要な読み込みを生じることなく余分な過剰電荷を基板に
流出させることによシ、光情報はある値で一定(白クリ
ップ)となる。以上が本発明を用いた場合の光情報読み
込み動作の一例である。
By such a means, the excess charge flowing into the substrate 1o in a forward bias state is read into the region 12 of the transfer stage.
Unnecessary pseudo signals are not output. After such outflow, when the pulse of the second electrode 19 returns to oV, the diode potential becomes
vc, and then Leetpa k,X Ic J:
A signal charge corresponding to the potential K is read into the transfer stage region 12. Time T1
When the diode potential is above Vc, that is, when the signal charge is less than the transfer handling charge amount, the second! The polar pulse does not go below OV and the diode is not forward biased. Therefore, when the diode potential is above Vc (no change in the content), optical information is proportional to the incident light intensity, but when it is below vc, that is, when the incident light intensity is very strong, the optical information is transferred. By draining the excess charge to the substrate without causing unnecessary reading in the stage, the optical information remains constant at a certain value (white clip). The above is an example of the optical information reading operation when the present invention is used.

以上は光導電体としテ( ”1−xCdx” )1−y
 ( ”zT@3)yを用いた場合について説明したが
、光導電体としては、他の材料、例えばアモルファスシ
リコン等を用いたものでもか1わない。さらに、光電変
換部として半導体基板とソース領域で構威されるダイオ
ードを用いてもよい。さらには光導電体のかわシに絶縁
物を用いても同様の効果が得られる。
The above is a photoconductor ("1-xCdx")1-y
("zT@3)y has been described, but the photoconductor may also be made of other materials, such as amorphous silicon. Furthermore, a semiconductor substrate and a source may be used as the photoelectric conversion section. It is also possible to use a diode formed in a region.Furthermore, a similar effect can be obtained by using an insulator for the photoconductor.

以上述べて来たように、本発明の固体撮像装置は半導体
基板と信号電荷を蓄積するソース領域で構或されるダイ
オードを、順バイアスとすることが可能な機構を有し、
かつ信号電荷の読み込み部の障壁電位を高くする手段を
有するもので、本発明を用いるなら、CODまたはBB
Dで構成され明m書の浄書(内容に変更なし)′ る電荷転送段の取扱い電荷量が、光電変換部で生戒する
最大電荷量よb小さい場合でも、電荷転送段に過剰電荷
をオーバーフローさせることなく基板に確実に流出する
ことができ、過剰電荷による不要な疑似信号の出力が発
生せず、残像も防止でき、入射光に忠実な信号電荷を出
力することが可能となシ、高性能な固体撮像装置の実現
に大きく寄与するものである。
As described above, the solid-state imaging device of the present invention has a mechanism capable of forward biasing a diode formed of a semiconductor substrate and a source region that accumulates signal charges,
It also has means for increasing the barrier potential of the signal charge reading section, and if the present invention is used, COD or BB
Even if the amount of charge handled by the charge transfer stage consisting of D is smaller than the maximum amount of charge to be expected in the photoelectric conversion section, excess charge will not overflow to the charge transfer stage. This makes it possible to reliably flow out to the substrate without causing excess charge, eliminate the output of unnecessary spurious signals due to excess charge, prevent afterimages, and output signal charges that are faithful to the incident light. This will greatly contribute to the realization of high-performance solid-state imaging devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は電荷転送機能を有する回路素子上に光導電体を
設けた固体撮像装置の一単位の断面構造図、第2図は第
1図の固体撮像装置の動作を説明するための図でクロッ
クパルスの時間関係と光導電体の電位関係を示す波形図
、第3図は本発明の一実施例の固体撮像装置における半
導体基板とソース領域で摘成されるダイオードを順バイ
アス状態にする時の動作を説明するための電位波形図で
ある。 10・・・・・・p型半導体基板、11・・・・・・ソ
ース領域となるn+型領域、12・・・・・・電位の井
戸となる転明細書の浄書(内容に変更欠し) 11 ペーノ 送用n+型領域、13・・・・・・ゲート電極、14・
・・・・・絶縁体膜、15・・・・・・絶縁体層。
Fig. 1 is a cross-sectional structural diagram of one unit of a solid-state imaging device in which a photoconductor is provided on a circuit element having a charge transfer function, and Fig. 2 is a diagram for explaining the operation of the solid-state imaging device shown in Fig. 1. FIG. 3 is a waveform diagram showing the time relationship between clock pulses and the potential relationship of the photoconductor. FIG. 3 is a waveform diagram showing a state in which a diode formed in a semiconductor substrate and a source region in a solid-state imaging device according to an embodiment of the present invention is put into a forward bias state. FIG. 3 is a potential waveform diagram for explaining the operation of FIG. 10...P-type semiconductor substrate, 11...N+ type region which becomes a source region, 12...Engraving of a transfer specification which becomes a potential well (no changes are made to the contents) ) 11 Peno feeding n+ type region, 13... Gate electrode, 14...
...Insulator film, 15...Insulator layer.

Claims (2)

【特許請求の範囲】[Claims] (1)一方の導電型を有する半導体基板に他方の導電型
を有し入射光により生じる信号電荷を蓄積し、ダイオー
ドを形成するソース領域と、上記基板のソース領域以外
の部分に、信号電荷を転送する回路素子と、上記ソース
領域の信号電荷を上記回路素子に読み込むためのMOS
FETと、上記MOSFETのチャンネル領域の電位を
高くする障壁手段と、一方の電極が上記ソース領域と電
気的に接続された光導電体とを有し、上記障壁手段によ
り上記チャンネル領域の電位を上記MOSFETのゲー
ト電極下の上記ソース領域と上記回路素子間の障壁電位
より高くし、上記ダイオードを順バイアス状態とする固
体撮像装置。
(1) A semiconductor substrate of one conductivity type has the other conductivity type and accumulates signal charges generated by incident light, and the signal charges are transferred to a source region forming a diode and a portion of the substrate other than the source region. A circuit element to be transferred and a MOS for reading signal charges in the source region into the circuit element.
FET, barrier means for increasing the potential of the channel region of the MOSFET, and a photoconductor whose one electrode is electrically connected to the source region, and the barrier means increases the potential of the channel region to the above level. A solid-state imaging device in which the barrier potential is higher than the barrier potential between the source region under the gate electrode of the MOSFET and the circuit element, and the diode is placed in a forward bias state.
(2)一方の導電型を有する半導体基板に他方の導電型
を有し入射光により生じる信号電荷を蓄積し、ダイオー
ドを形成するソース領域と、上記基板のソース領域以外
の部分に、信号電荷を転送する回路素子と、上記ソース
領域の信号電荷を上記回路素子に読み込むためのMOS
FETと、上記MOSFETのチャンネル領域の電位を
高くする障壁手段と、一方の電極が上記ソース領域と電
気的に接続された光導電体とを有し、上記回路素子の取
り扱い電荷量よりを多い電荷が上記ソース領域に蓄積さ
れた時、上記障壁手段により上記チャンネル領域の電位
を上記MOSGETのゲート電極下の上記ソース領域と
上記回路素子間の障壁電位より高くし、上記ダイオード
を順バイアス状態とする固体撮像装置。
(2) A semiconductor substrate having one conductivity type has the other conductivity type and accumulates signal charges generated by incident light, and the signal charges are transferred to a source region forming a diode and a portion of the substrate other than the source region. A circuit element to be transferred and a MOS for reading signal charges in the source region into the circuit element.
FET, barrier means for increasing the potential of the channel region of the MOSFET, and a photoconductor whose one electrode is electrically connected to the source region, and has an electric charge larger than the amount of charge handled by the circuit element. is accumulated in the source region, the barrier means makes the potential of the channel region higher than the barrier potential between the source region under the gate electrode of the MOSGET and the circuit element, thereby putting the diode in a forward bias state. Solid-state imaging device.
JP2011282A 1980-01-18 1990-01-19 Solid-state image pickup device Granted JPH03171883A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011282A JPH03171883A (en) 1980-01-18 1990-01-19 Solid-state image pickup device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP485980A JPS56102169A (en) 1980-01-18 1980-01-18 Solid image pickup device
JP2011282A JPH03171883A (en) 1980-01-18 1990-01-19 Solid-state image pickup device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP485980A Division JPS56102169A (en) 1980-01-18 1980-01-18 Solid image pickup device

Publications (2)

Publication Number Publication Date
JPH03171883A true JPH03171883A (en) 1991-07-25
JPH0549152B2 JPH0549152B2 (en) 1993-07-23

Family

ID=26338710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011282A Granted JPH03171883A (en) 1980-01-18 1990-01-19 Solid-state image pickup device

Country Status (1)

Country Link
JP (1) JPH03171883A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5495116A (en) * 1978-01-13 1979-07-27 Toshiba Corp Solid image pickup unit
JPS54124480U (en) * 1978-02-20 1979-08-31
JPS551151A (en) * 1978-06-19 1980-01-07 Matsushita Electric Ind Co Ltd Photoconductive element
JPS56102169A (en) * 1980-01-18 1981-08-15 Matsushita Electric Ind Co Ltd Solid image pickup device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5495116A (en) * 1978-01-13 1979-07-27 Toshiba Corp Solid image pickup unit
JPS54124480U (en) * 1978-02-20 1979-08-31
JPS551151A (en) * 1978-06-19 1980-01-07 Matsushita Electric Ind Co Ltd Photoconductive element
JPS56102169A (en) * 1980-01-18 1981-08-15 Matsushita Electric Ind Co Ltd Solid image pickup device

Also Published As

Publication number Publication date
JPH0549152B2 (en) 1993-07-23

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