JPH03171757A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH03171757A
JPH03171757A JP31094189A JP31094189A JPH03171757A JP H03171757 A JPH03171757 A JP H03171757A JP 31094189 A JP31094189 A JP 31094189A JP 31094189 A JP31094189 A JP 31094189A JP H03171757 A JPH03171757 A JP H03171757A
Authority
JP
Japan
Prior art keywords
conductive film
insulating film
forming
film
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31094189A
Other languages
Japanese (ja)
Inventor
Hiroyasu Ishihara
石原 宏康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP31094189A priority Critical patent/JPH03171757A/en
Publication of JPH03171757A publication Critical patent/JPH03171757A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obviate the need for forming a conductive film by the photodetecting process, to eliminate the unetched part, to obviate the need for mask matching and to reduce failure rate for achieving miniaturization by selectively forming a second conductive film by the selective growth method. CONSTITUTION:An impurity region 5 is formed on a semiconductor substrate 1 with a second insulation film 4 and a conductive film 3 as masks. Then, a third insulation film 6 is formed. Then, a contact hole 7 is provided, thus exposing one part of the impurity region 5. After that, by performing crystal growth for the semiconductor substrate 1, a polycrystal silicon is allowed to grow selectively at the exposed impurity region 5 through the first contact hole 7 and then a second conductive film 8 is selectively formed by doping phosphor to it. Thus, since the second conductive film 8 is formed by the selective crystal growth, it is not necessary to use an etching using a photo mask when forming the second conductive film and the mask matching accuracy in this case does not produce any problem.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に自己整合コ
ンタクトを製造する方法に関する.〔従来の技術〕 第2図は従来の自己整合コンタクトを有する半導体装置
の縦断面図である。同図において、P型シリコン基板1
の表面を酸化して、酸化シリコンからなる第1の絶縁W
i!2を形成している。そして、この第1の絶縁11g
2上に燐を含む多結晶シリコンからなる第1の導電性y
I3を形戒している。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a self-aligned contact. [Prior Art] FIG. 2 is a longitudinal sectional view of a semiconductor device having a conventional self-aligned contact. In the figure, a P-type silicon substrate 1
by oxidizing the surface of the first insulating material W made of silicon oxide.
i! 2 is formed. And this first insulation 11g
2. A first conductive material y made of polycrystalline silicon containing phosphorus on
I am admonishing I3.

次に、第1の導電性膜3上に酸化シリコンからなる第2
の絶縁膜4を設け、フォトエッチング法を用いて第2の
絶縁膜4及び第1の導電性膜3を同一マスクでパターン
ニングする. 次に、第2の絶縁膜4及び第1の導電性膜3をマスクに
して半導体基板1に、砒素のようなN型の不純物を導入
して、不純物領域5を形成する.次に、全面に酸化シリ
コンからなる第3の絶縁膜6を形戒し、第1の導電性膜
3が露出しないように選択エッチングして第1のコンタ
クトホール7を開設し、不純物領域5の一部を露出させ
る。
Next, a second conductive film made of silicon oxide is placed on the first conductive film 3.
An insulating film 4 is provided, and the second insulating film 4 and the first conductive film 3 are patterned using the same mask using a photo-etching method. Next, using the second insulating film 4 and the first conductive film 3 as masks, an N-type impurity such as arsenic is introduced into the semiconductor substrate 1 to form an impurity region 5. Next, a third insulating film 6 made of silicon oxide is formed on the entire surface, and a first contact hole 7 is formed by selective etching so that the first conductive film 3 is not exposed. expose a part.

次に、第1のコンタクトホール7を含む領域に不純物領
域5と電気的に接続するように配線用の第3の導電性)
Ill IAを設け、フォトエッチング法によりパター
ンニングすることで自己整合コンタクトを完威する. 〔発明が解決しようとする課題〕 上述した従来の自己整合コンタクトでは、第3の絶縁膜
6の絶縁信頼性を高めるために、第3図に示すように第
3の絶縁膜6を厚く形成すると、第lのコンタクトホー
ル7を開設する際の第3の絶縁膜6のエッチングを制御
することが困難となり、第1のコンタクトホール7内に
第1の導電性lI!3が露出され易い.このため、第3
の導電性膜11と第1の導電性膜3が接触し、電気的短
絡が生じ易いという問題がある。
Next, a third conductive layer (for wiring) is applied to the region including the first contact hole 7 so as to be electrically connected to the impurity region 5.
A self-aligned contact is achieved by providing an IA and patterning it by photo-etching. [Problems to be Solved by the Invention] In the conventional self-aligned contact described above, in order to improve the insulation reliability of the third insulating film 6, it is necessary to form the third insulating film 6 thickly as shown in FIG. , it becomes difficult to control the etching of the third insulating film 6 when opening the l-th contact hole 7, and the first conductive lI! 3 is easily exposed. For this reason, the third
There is a problem in that the conductive film 11 and the first conductive film 3 are likely to come into contact with each other, resulting in an electrical short circuit.

このため、他の構造として、第4図に示す自己整合コン
タクトが提案されている。このコンタクトは、第3の絶
縁膜6At−薄く形成し、第1のコンタクトホール7を
開設した後、燐をドープした多結晶シリコンからなる第
2の導電性膜8Aを設け、フ1トエッチング法により第
1のコンタクトホール7を完全に覆い、かつ第1のコン
タクトボール7の周囲に多少延在するようにパターニン
グする。そして、十分に厚いBPSG (ボロン燐ガラ
ス)からなる第4の絶縁膜9を全面に形成し、リフロー
後、第2の導電性膜8Aの一部のみが露出するようにフ
ォトエッチング法により第2のコンタクトホール10を
形成する。この時、第2の導電性膜8Aがエッチングの
ストッパーになり、第1の導電性膜3が露出することは
ない。
For this reason, a self-aligned contact shown in FIG. 4 has been proposed as another structure. This contact is made by forming a thin third insulating film 6At, opening a first contact hole 7, and then providing a second conductive film 8A made of phosphorous-doped polycrystalline silicon and using a foot etching method. The patterning is performed so as to completely cover the first contact hole 7 and to extend around the first contact ball 7 to some extent. Then, a sufficiently thick fourth insulating film 9 made of BPSG (boron phosphorus glass) is formed on the entire surface, and after reflow, a second insulating film 9 is formed by photo-etching so that only a part of the second conductive film 8A is exposed. A contact hole 10 is formed. At this time, the second conductive film 8A acts as an etching stopper, and the first conductive film 3 is not exposed.

次に、第2のコンタクトホール10を介して第2の導電
性膜8Aと電気的に接続されるようにアルミニウムから
なる第3の導電性膜l1を設ける。
Next, a third conductive film l1 made of aluminum is provided so as to be electrically connected to the second conductive film 8A via the second contact hole 10.

しかしながら、この自己整合コンタクトでは、第3の絶
縁膜6が薄いために、平坦性が十分でなく、第2の導電
性膜8Aをパターンニングする際にそのエッチング残り
が生じ易い.また、第2の導電性膜8Aはフォトエッチ
ング法を用いてパターンニングすることが必要とされる
ため、マスク合わせの精度が問題となり、微細化を妨げ
るという問題もある. 本発明はこれらの問題を解消し、第1の導電性膜との短
絡を防止するとともに、微細化を可能にした半導体装置
の製造方法を提供することにある。
However, in this self-aligned contact, since the third insulating film 6 is thin, its flatness is not sufficient, and etching remains are likely to be left when patterning the second conductive film 8A. Further, since the second conductive film 8A needs to be patterned using a photoetching method, there is a problem in the accuracy of mask alignment, which impedes miniaturization. The present invention solves these problems and provides a method for manufacturing a semiconductor device that prevents short circuits with the first conductive film and enables miniaturization.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、半導体基板の表面に
設けた第1の絶縁膜上に第1の導電性膜及び第2の絶縁
膜を順次形成し、かつこれらを所要パターンにエッチン
グし、更に全面に第3の絶縁膜を形成し、かつ前記第1
の導電性膜が露出しないように第3の絶縁膜に第1のコ
ンタクトホールを開設して前記半導体基板の一部を露出
した後に、この露出された半導体基板上に選択威長法に
よって第2の導電性膜を選択形成している.その上で、
、全面に第4の絶縁膜を形成し、かつ前記第2の導電性
膜の一部が露出するように第4の絶縁膜に第2のコンタ
クトホールを形成し、かつ前記第2のコンタクトホール
を通して、前記第2の導電性膜と電気的に接続される第
3の導電性膜を形成している。
The method for manufacturing a semiconductor device of the present invention includes sequentially forming a first conductive film and a second insulating film on a first insulating film provided on a surface of a semiconductor substrate, and etching these into a desired pattern. Furthermore, a third insulating film is formed on the entire surface, and the first
After opening a first contact hole in the third insulating film to expose a part of the semiconductor substrate so as not to expose the conductive film, a second contact hole is formed on the exposed semiconductor substrate by a selective length method. A conductive film is selectively formed. Moreover,
, a fourth insulating film is formed on the entire surface, and a second contact hole is formed in the fourth insulating film so that a part of the second conductive film is exposed, and the second contact hole A third conductive film is formed to be electrically connected to the second conductive film through the conductive film.

〔作用〕[Effect]

この製造方法では、第2の導電性膜を選択或長法によっ
て選択形成しているため、第2の導電性膜を形成する際
に、フォトエッチング工程が不要となり、エッチング残
りが生じることはなく、しかもマスク合わせが不要とな
る. また、第4の絶縁膜を形成することで、十分な絶縁の信
頼性を得ることが可能となる.〔実施例〕 次に、本発明を図面を参照して説明する。
In this manufacturing method, the second conductive film is selectively formed by a selective or lengthening method, so there is no need for a photo-etching process when forming the second conductive film, and no etching residue is left. , moreover, there is no need for mask alignment. Furthermore, by forming the fourth insulating film, it becomes possible to obtain sufficient insulation reliability. [Example] Next, the present invention will be described with reference to the drawings.

第1図(a)乃至(C)は本発明の一実施例を工程順に
示す縦断面図である. 先ず、第1図(a)のように、P型シリコン単結晶から
なる半導体基板1の表面を酸化して200λ程度の厚さ
の酸化シリコンからなる第1の絶縁膜2を形成する.そ
して、この第1の絶縁膜2上に燐を含む多結晶シリコン
からなる第1の導電性膜3を2000人程度の厚さに形
成する.更に、この第lの導電性膜3上に、2000人
程度の酸化シリコンからなる第2の絶縁膜4を設ける.
そして、第2の絶縁膜4及び第lの導電性膜3を同一マ
スクを用いたフォトエッチング法によりパターンニング
する。
FIGS. 1(a) to 1(C) are longitudinal sectional views showing an embodiment of the present invention in the order of steps. First, as shown in FIG. 1(a), the surface of a semiconductor substrate 1 made of P-type silicon single crystal is oxidized to form a first insulating film 2 made of silicon oxide with a thickness of about 200λ. Then, on this first insulating film 2, a first conductive film 3 made of polycrystalline silicon containing phosphorus is formed to a thickness of about 2,000 layers. Further, on this first conductive film 3, a second insulating film 4 made of about 2,000 silicon oxides is provided.
Then, the second insulating film 4 and the first conductive film 3 are patterned by photo-etching using the same mask.

次に、第2の絶縁膜4及び第1の導電性膜3をマスクに
して半導体基板1に、砒素のようなN型の不純物を、7
0KeVのエネルギーテ4 XIQISc@−Z導入し
て不純物領域5を形成する。
Next, using the second insulating film 4 and the first conductive film 3 as masks, an N-type impurity such as arsenic is added to the semiconductor substrate 1.
An impurity region 5 is formed by introducing energy TE4XIQISc@-Z of 0 KeV.

次いで、同図(b)のように、全面に酸化シリコンから
なる第3の絶縁膜6を比較的に薄く、例えば2000入
程度の厚さに形成する。そして、第1の導電性膜3が露
出しないように第3の絶縁膜6をフォトエッチングし、
第1のコンタクトホール7を開設して不純物領域5の一
部を露出させる。
Next, as shown in FIG. 6B, a third insulating film 6 made of silicon oxide is formed over the entire surface to a relatively thin thickness, for example, about 2000 μm thick. Then, the third insulating film 6 is photo-etched so that the first conductive film 3 is not exposed.
A first contact hole 7 is opened to expose a portion of impurity region 5.

しかる上で、半導体基板lに対して結晶威長を施すこと
で、第1のコンタクトホール7を通して露出された不純
物領域5に多結晶シリコンを選択的に或長させ、かつこ
れに燐を燐をドープすることで第2の導電性膜8を選択
形成する.この第2の導電性M8の厚さは例えば1.2
μmとする。
Then, by performing crystal lengthening on the semiconductor substrate l, the polycrystalline silicon is selectively lengthened to a certain extent in the impurity region 5 exposed through the first contact hole 7, and phosphorus is added to the polycrystalline silicon. The second conductive film 8 is selectively formed by doping. The thickness of this second conductive M8 is, for example, 1.2
Let it be μm.

次に、同図(C)のように、BPSGからなる第4の絶
縁膜9を1μmの厚さで全面に形成し、かつリフローし
て表面の平坦化を図る。そして、第2の導電性膜8の上
面一部のみが露出するように第4の絶縁膜9に第2のコ
ンタクトホール10を開設する。更に、この第2のコン
タクトホール10を通して第2の導電性膜8と電気的に
接続するように配線用の第3の導電性膜11を設け、か
つこれをフォトエッチング法によりパターンニングする
ことで自己整合コンタクトが完威される。
Next, as shown in FIG. 2C, a fourth insulating film 9 made of BPSG is formed to a thickness of 1 μm over the entire surface, and is reflowed to planarize the surface. Then, a second contact hole 10 is formed in the fourth insulating film 9 so that only a part of the upper surface of the second conductive film 8 is exposed. Furthermore, a third conductive film 11 for wiring is provided so as to be electrically connected to the second conductive film 8 through this second contact hole 10, and this is patterned by photo-etching. Self-aligned contact is perfected.

したがって、このように製造される自己整合コンタクト
は、第3の絶縁膜6を薄くすることで第1のコンタクト
ホール7の開設に際してのエッチング制御を容易に行う
ことができ、このエッチングによって第1の導電性膜3
が露出されることはなく、コンタクトとの短絡を防止す
ることができる. また、この方法では、第2の導電性膜8を選択的な結晶
或長法で形成しているため、第2の導電性膜の形成に際
してフォトマスクを用いたエッチングを用いる必要はな
く、この際のマスク合わせ精度が問題となることもない
Therefore, in the self-aligned contact manufactured in this way, by making the third insulating film 6 thinner, it is possible to easily control etching when opening the first contact hole 7, and this etching makes it possible to easily control the etching when opening the first contact hole 7. Conductive film 3
The contacts will not be exposed and short circuits with contacts can be prevented. In addition, in this method, since the second conductive film 8 is formed by a selective crystal growth method, there is no need to use etching using a photomask when forming the second conductive film. There is no problem with the accuracy of mask alignment.

なお、第2の導電性膜8をタングステンで形成し、第4
の絶縁膜9をシリカ塗布膜としてもよい.このようにす
れば、第2の導電性膜8と第4の絶縁膜9を低温で製造
でき、不純物領域5等への高温による影響を無くすこと
ができる利点がある.〔発明の効果〕 以上説明したように本発明は、第2の導電性膜を選択威
長法によって選択形成しているため、この導電性膜をフ
ォトエッチング工程によって形成する必要がなく、エッ
チング残りが無くなるとともにマスク合わせが不要とな
り、不良率を低減して微細化が実現できる効果がある. また、十分に厚い第4の絶縁膜を形成することが可能と
なり、絶縁の信頼性を高めることができる効果もある.
Note that the second conductive film 8 is made of tungsten, and the fourth conductive film 8 is made of tungsten.
The insulating film 9 may be a silica coated film. This has the advantage that the second conductive film 8 and the fourth insulating film 9 can be manufactured at a low temperature, and that the effects of high temperature on the impurity region 5 and the like can be eliminated. [Effects of the Invention] As explained above, in the present invention, since the second conductive film is selectively formed by the selective lengthening method, there is no need to form this conductive film by a photo-etching process, and the etching residue is removed. This eliminates the need for mask alignment, which has the effect of reducing the defective rate and realizing miniaturization. Furthermore, it becomes possible to form a sufficiently thick fourth insulating film, which has the effect of increasing the reliability of insulation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)乃至第1図(c)は本発明の一実施例を製
造工程順に示す縦断面図、第2図は従来の自己整合コン
タクトの一例の縦断面図、第3図及び第4図はそれぞれ
従来の異なる製造方法における問題を説明するための縦
断面図である。 1・・・半導体基板、2・・・第1の絶縁膜、3・・・
第1の導電性膜、4・・・第2の絶縁膜、5・・・不純
物領域、6.6A・・・第3の絶縁膜、7・・・第1の
コンタクトホール、8,8A・・・第2の導電性膜、9
・・・第4の絶縁膜、10・・・第2のコンタクトホー
ル、11,IIA・・・第3の導電性膜。 第 l 図 第2 図
1(a) to 1(c) are longitudinal sectional views showing an embodiment of the present invention in the order of manufacturing steps, FIG. 2 is a longitudinal sectional view of an example of a conventional self-aligning contact, and FIGS. FIG. 4 is a longitudinal sectional view for explaining problems in different conventional manufacturing methods. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First insulating film, 3...
First conductive film, 4... Second insulating film, 5... Impurity region, 6.6A... Third insulating film, 7... First contact hole, 8,8A... ...Second conductive film, 9
... Fourth insulating film, 10... Second contact hole, 11, IIA... Third conductive film. Figure l Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基板の表面に設けた第1の絶縁膜上に第1の
導電性膜及び第2の絶縁膜を順次形成し、かつこれらを
所要パターンにエッチングする工程と、全面に第3の絶
縁膜を形成し、かつ前記第1の導電性膜が露出しないよ
うに第3の絶縁膜に第1のコンタクトホールを開設して
前記半導体基板の一部を露出する工程と、この露出され
た半導体基板上に選択成長法によって第2の導電性膜を
選択形成する工程と、全面に第4の絶縁膜を形成し、か
つ前記第2の導電性膜の一部が露出するように第4の絶
縁膜に第2のコンタクトホールを形成する工程と、前記
第2のコンタクトホールを通して前記第2の導電性膜と
電気的に接続される第3の導電性膜を形成する工程を含
むことを特徴とする半導体装置の製造方法。
1. A step of sequentially forming a first conductive film and a second insulating film on the first insulating film provided on the surface of the semiconductor substrate and etching them into a required pattern, and a step of forming a third insulating film on the entire surface. forming a film and opening a first contact hole in a third insulating film so as not to expose the first conductive film to expose a part of the semiconductor substrate; a step of selectively forming a second conductive film on the substrate by a selective growth method; and a step of forming a fourth insulating film on the entire surface, and forming a fourth insulating film so that a part of the second conductive film is exposed. The method includes the steps of forming a second contact hole in an insulating film, and forming a third conductive film electrically connected to the second conductive film through the second contact hole. A method for manufacturing a semiconductor device.
JP31094189A 1989-11-30 1989-11-30 Manufacture of semiconductor device Pending JPH03171757A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31094189A JPH03171757A (en) 1989-11-30 1989-11-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31094189A JPH03171757A (en) 1989-11-30 1989-11-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH03171757A true JPH03171757A (en) 1991-07-25

Family

ID=18011230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31094189A Pending JPH03171757A (en) 1989-11-30 1989-11-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH03171757A (en)

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