JPH03167592A - Image displaying system - Google Patents

Abstract

PURPOSE:To display one image by using plural display parts by storing an inputted image signal, making the speed at the time of storing the signal differ from the speed at the time of reading out and also controlling a read out part. CONSTITUTION:Plural image displaying devices 41 - 43 are connected in serial and then, connected with an image reader 40, the image signal and a synchronizing signal for forming the image on a recording medium are received by the plural displaying devices 41 - 43 so as to store the received image signal. And the signal on the prescribed part out of the received image signals is stored at a prescribed speed by the controlling means of the plural displaying devices 41 - 43 respectively, and the signal on the prescribed part is read out at the speed different from the speed at the time of storing. Thus, one image can be displayed by the plural displaying devices 41 - 43.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image display device that displays an image based on an input image signal.

(Background technology) FIG. 6 shows a display device on which the present invention is based.

1 is the main body of the device, which is placed on the stands 2 and 2'. 3 is the display section, which is the alphabet "A" in the figure.
is displayed on the front page. This image is formed with toner on a belt-shaped recording medium 4 that is an image carrier, and the recording medium 4 is supported by support rollers 5, 6, and 7.
, 8 in the direction of arrow A. The roller 6 is connected to a driving motor 9 by a belt. Further, 10 is a control board equipped with a microcomputer (not shown) for controlling the display device. Reference numeral 11 denotes a recording section for attaching one line of toner to the recording medium 4 in the horizontal direction. 12
is an erasing unit for erasing the image on the recording medium 4. FIG. 7 shows the state of the recording section 11.

The image forming method of this recording section 11 is
There is a method known from Publication No. 6707 and the like. In this method, as shown in FIG. 7, conductive magnetic toner 13 is conveyed over a non-magnetic cylinder 15 by a rotating magnet 14 and passed over a recording electrode 16 made of a magnetic material. Then, a voltage is applied between the conductive layer 17 of the recording medium 4 having an insulating layer on its surface and the recording electrode, and toner is adhered to the recording medium to form an image. Figure 8 shows details of the recording electrode section. A flexible printed circuit board 20 connects the recording electrode 16 and the drive circuit section 19 . The flexible printed circuit board 20 is in contact with or adhered to the non-magnetic cylindrical member 15 on the side near the recording electrode 16, and is bent in the middle to be separated from the non-magnetic cylindrical member 15, but the openings 17 are arranged in substantially this portion. The wiring is provided bypassing the opening 17 as shown in the figure. The rotation of a magnet containing toner for image formation causes the toner to circulate on the non-magnetic cylindrical member through this opening 17. When a signal voltage, for example, several tens of volts, is applied to the recording electrode 16 from the drive circuit 19, the toner 13 adheres to the recording medium 4, but does not adhere when the voltage is O volts.

Generally, such an image display device is connected to an image input or processing device, such as an image reader, as shown in the block diagram of FIG. However, the details of the connection from the image reader to the display device or from the display device to the image reader regarding the communication means for transmitting the status of each device and instructing the operation mode etc. are omitted.

101 is an image reader, 102 is a display device, and a READY signal 103 is a signal indicating that the display device 102 is in a state where it can receive an image signal from the image reader 101. A START signal 104 instructs the image reader 101 to the display device 102 to start moving the image carrier 4. When the display device 102 receives the START signal 104 from the image reader 101, if the READY signal is "1", it starts driving the belt 4 and keeps the moving speed of the belt 4 constant. Also, RE
When the ADY signal is "o", the START signal 104 is ignored, the belt 4 is not driven, and all other controls necessary for the display operation are not started. The HSYNC signal 105 is a pulse signal output from the display device 102 to the image reader 101 in order to synchronize the image formed on the belt 4 in the vertical direction, and is generally connected to a motor for driving the belt 4. A position detector such as a rotary encoder is generated based on the output pulses of the rotary encoder. image reader 10
1 sends out an image signal for one line upon receiving the HSYNC pulse signal 105.

106 is an image synchronization clock VCLK signal for horizontally synchronizing the image formed on the belt 4, and is sent from the image reader 101 to the display device 102 together with the image signal VIDEO 107.

Reference numeral 10B is an interface line for outputting instruction commands from the image reader 101 to the display device 102 and performing communication for importing the device status of the image reader 102 to the image reader 101. A timing chart for the above signals 103 to 107 is shown in FIG. (Problem to be solved by the invention) In the display device as described above, if a large image is to be displayed, a large image carrier is required, but the larger the image carrier, the greater the weight. , it becomes difficult to support and drive the image carrier.

Therefore, it is conceivable to form a display screen by connecting a plurality of image display devices as described above. FIG. 11 shows the state of the display screen in this case. This shows how the alphabet "A" shown in Figure 6 is displayed on three image display devices. In this case, the image reader and three display devices are connected in a 1:3 ratio as shown in FIG. 12. 10
2-a, 102-b, and 102-c are display devices, which are connected to the image reader 101 through interface cables 111, 112, and 113, respectively, and the image reader 101 has control units 114 and 1 for each display device.
15 and 116 are provided.

However, n display devices per image reader
The method of connecting the pedestals requires a drive section corresponding to each display device within the image reader, thus making the image reader expensive. Furthermore, a 1:n interface conversion device must be prepared separately.

(Means and effects for solving the problems) The present invention has been made in view of the above points, and it outputs a synchronizing signal for image formation on the image signal output side, and connects image display devices to each other. This structure allows the control section to be configured easily and at low cost.

In addition, it is also possible to display one screen using multiple display devices.

Furthermore, it also prevents inconveniences when displaying one page's worth of images on a plurality of display devices.

〔Example〕

FIG. 1 shows a block diagram of an image display device according to the present invention. Reference numeral 200 is a connector section connected to another upper display device or image reader, and 300 is a connector section connected to a lower display device. . The main signals are numbered the same as in Figure 9. In FIG. 1, the READY signal 103 is a READY signal from another image display device 300 connected to the lower level (on the right side of the figure).
Signal 103A and RDY signal 10 of main image display device 102
3B in the AND circuit 21 in the form of a product. 22 is a control unit for controlling image formation and display of the image display device. Reference numeral 9 denotes a motor for moving the belt 4, and is driven by an on/off signal from the control section 22. 23 is a switch for instructing the operator to skip the display operation by the image display device;
If 3 is pressed, the display operation will be skipped. That is,
The display device whose switch 23 is pressed does not operate, and can be displayed on other display devices. 24 is the recording electrode 16
This is an image processing section including a drive circuit section 19 that drives the.

The image processing section 24 receives various command settings for image display from the control section 22 via a control line 25. or,
The image processing unit 24 has an HSYNC signal (105) and a VCL signal.
The K signal (107) and VIDEO signal (107) are manually generated.

The main operation of the control unit 22 is to output a READY signal (103) indicating that the display device 102 is ready to display image data from the image reader 101. ), the motor 9 is rotated to rotate the recording medium 4 at a constant speed, and an image signal and a control signal (105
, 10B, 107) will be input. FIG. 2 shows an internal block diagram of the image processing section 24.

In FIG. 342, the same parts as in FIG. 1 are given the same numbers. 26 is VIDEO input from the higher-level device
It is a memory unit for temporarily storing the signal 107, and has a capacity of 2500 bits x 8 lines = 20 kb it.
memory. 27 is memory unit 26 (7) VI
DEO signal (107) is a write operation controller (hereinafter abbreviated as controller), and is an address signal 2 of a memory element to be subjected to a write operation for the memory unit 26.
8. Output a memory control signal 29 to enable that memory element. The write controller sequentially shifts the addresses of the memory unit 26 using the VCLK signal (106) after the HSYNC signal (tos) is input. Then, one line of VIDEO signal (107) is stored. When the next HSYNC signal (i05) is input,
The VIDEO signal (107) of the next line is stored.

After storing eight lines, the write operation to the memory address used in the first line is performed again. At this time, the previous data is deleted.

30 is a read operation controller (hereinafter abbreviated as read controller) for reading the VIDEO signal stored in the memory unit 26;
1 and outputs a memory control signal 32 that enables the memory device. The address signal 31 and memory control signal 32 from the read controller 3o are the VCLK signal 1.
06 and an internal HSYNC signal 34 (described later). Also, the VCLK signal (108) on the control line 25
For example, by setting the division ratio to twice, it is possible to output image data that is twice the data written in the memory unit 26. ．． 33 is the recording medium 4 in this image display device
This is a detector for detecting the moving speed of the motor, and the speed is detected by pulses from the rotary encoder installed on the shaft of the motor. Speed pulse signal 34 obtained by detector 33
is input to the read controller and used together with the CLK signal 106 for address switching during read operation.

In the read controller 30, HSYN from the host device
After 4 lines of image signals are stored from the time when the C signal 105 starts to be input (when the display data signal for one screen starts to be stored in the memory unit 26), the image signals are stored from the memory unit 26 in synchronization with the moving speed of the recording medium 4. Start reading out the image signal. FIG. 3 shows the state transition of access to the memory unit 26 by the write controller 27 and read controller 30. In Figure 3, “1→” indicates the memory write state 1@...
・・◆'' indicates a read state transition, and ・゜゜ indicates an access start point.The memory unit is composed of eight line memory groups, each of which is called LMI to LM8. This is written for the sake of simplicity, and may differ from the actual configuration of the memory unit.

First, with the write controller 27 selecting LMI, the VIDEO signal 107 is memorized by the pulse of the VCLK signal 106, and then when the HSYNC signal 105 is input, the write controller 27 sets the address to L.
Shift to M2 and transfer V to LM2 by VCLK signal 106.
IDEO signal 107 is stored. In this way, the line memories LM1 to LM8 are sequentially accessed, and when the line memory LM8 is reached, the process returns to LMI again. When the write state to the line memory LM4 is first completed and the write operation to the next line memory LM5 is started, the read operation to the line memory LMI is thereafter started. The address within each line memory during a read operation is changed by the VCLK signal 106, and shifting of the line memories is done by the internal HSYNC signal 34.

Returning to FIG. 2 again, the image signal 35 output from the memory unit 26 is manually input to the shift register 39, sent to the electrode drive section 19, and is formed into an image on the recording medium 4 by the recording electrode 16.

Now, FIG. 4 shows a configuration in which a plurality of the above-mentioned image display devices are connected in series and connected to an image reader in Mj.
40 is an image reader, 41, 42, and 43 are the above-mentioned image display devices, and the upper and lower relationships are 40>41>4.
2>43. Now, there are three image display devices 41, 42,
43 can all be displayed and the skip switch (FIG. 1 23) is not pressed. This state is detected by the image reader 40 through the interface line 108.
will be notified. There is a division instruction switch (not shown) on the image reader 4o, and the operator sets the division instruction switch to, for example, "3 division". This information is then notified from the image reader 4o to each of the display devices 41-43.

At this time, the division method and display address are also notified. For example, the division method is to divide a line in the horizontal direction, that is, in the main scanning direction, by three display devices, and specify which part of the image to display on each display device. In the case of 3 divisions, 1 line is 2400
Assuming that it is composed of pixels, the addresses for one line of each display device are "0" to "799" for display device 41, "800" to "1599" for display device 42, and "800" to "1599" for display device 43.
is assigned to "1600" to "2 3 9 9". When an image is stored in one line memory in the memory unit 26 shown in FIG. 2 (write state), the change in address 28 for one line is determined by the VCLK signal 106
It changes itself. However, in the read state, the change in address 31 from the read controller is VCLK.
It starts from a predetermined start address at a speed that is the frequency of the signal 106 divided by 1/3.

By performing the above control, one screen can be created using three display devices as shown in Figure 's11.

FIG. 345 shows a timing chart when three display devices of this invention are connected to display an image enlarged three times in the main scanning direction. Figure 5 shows the HSYNC signal 105 and VCL at the same time.
This is how image data is output in the first to third display devices when the K signal 106 and the V I DEO signal are sent.

On the first display device, the VC after HSYNC is sent.
The LK signal is counted from O, and the image data is stored in the memory 26 until it counts 799. The second display device changes the VCLK signal from 800 counts to 1599 counts, and the third display device changes the VCLK signal from 1600 counts to 1599 counts.
Image data from count to 2399 count are each stored in memory. When the data stored in the line memory corresponds to four lines and the fifth line enters the write state, reading from the LMI of the line memory is started using the VCLK signal received at that time.

At this time, the frequency of the VCLK signal is divided by one-third, and the address of the line memory is changed by a counter in accordance with the frequency of the divided VCLK signal. By doing so, if image data written in one clock is read out in three clocks, the image will be expanded three times in the horizontal direction.

As described above, the image data from address O to address 799 is enlarged by 3 times on the first display device, and 8 times on the second display device.
The image data from address 00 to address 1599 is expanded three times, and the image data from address 1600 to address 239 is enlarged three times on the third display device.
The image data up to address 9 will be enlarged three times. Further, in this case, since the write/read timing to the line memory is shifted by 4 lines, the sent image data is displayed with a delay of 4 lines.

In the above embodiment, the displayed image is divided and displayed in the main scanning direction, but when the division instruction from the host image reader is "1", the same screen can of course be displayed on three display devices. Needless to say, this is possible.

Further, the three display devices may be divided into two display devices and one display device, and two display devices may display one screen while the remaining one may be skimmed, and the number of divisions does not limit the content of the invention. In addition, the capacity of the memory unit and the method of accessing the memory unit are not limited to this embodiment.

For example, a memory unit having a capacity sufficient to store image data for one screen may be used to display different images on a plurality of connected display devices.

Further, in the above embodiment, the explanation has been made based on division of one screen in the main scanning direction, but it is also possible to perform division in the sub-scanning direction. For example, two display devices may be arranged vertically to display two lines of one line of image data received from an image reader in succession. As a result, an image enlarged twice in the sub-scanning direction can be displayed.

Of course, it is also possible to display one image by simultaneously enlarging the main scanning and sub-scanning directions.

By the way, when multiple image display devices are connected as described above to enlarge and display one page of images, a certain amount of space is created between the display sections of adjacent display devices.
When displaying figures, photographs, etc., the images are discontinuous, resulting in an unnatural display. A solution to this drawback will be explained below.

13 and 14 are diagrams showing the configuration of an image display device for explaining this embodiment, and FIG. 15 is a timing diagram. 201 is image data VIDEO;
Input from controller or host device. 202
A timing clock VCLK, 203, which is sent together with the image data, is a video enable signal VE indicating the valid period of the input image data VIDEO.

204 is a data division processing unit that divides image data into a plurality of display boards, and 205 to 216 are display boards.

Figure 13 shows a connection example when multiple display boards are connected, four in the row direction and four in the column direction, and for ease of explanation, a figure representing a circle is displayed. explain. V in FIG. The tv period of the E signal is a period corresponding to the effective image area to be displayed on the display board within the scanning period shown in FIG. Also, the tg period following tv is the gap g between boards that occurs when the display boards are arranged as shown in Figure 16.
It is determined from the image density and the frequency of the image readout clock. Furthermore, the gap gh in the sub-scanning direction is similarly generated in synchronization with image scanning. An example in which tg and tgh occur will be described below using FIG. 14. In FIG. 14, a clock counter 250 counts the number of video data by counting the video clock CLK. 251 is a digital comparator, and display board horizontal pixel number generator 268
Compare with the setting value from and output the result. 252 is a flip-flop which is triggered by the output of the digital converter 251. 253 is a gap correction counter, 2
54 is a decode counter, and 255 to 258 are AND circuits. For 259 to 267, the input is V instead of VCLK.
The configuration is the same as described above except that the E signal is used. First of all,
A clock counter 250 counts the video clock 202 in synchronization with the image signal. The count value is input to the converter 251 and compared with the output of the display board horizontal pixel number generator 268 set in advance. As a result, when the value of the clock counter matches the display board horizontal pixel number, the converter 251 outputs "1", sets the following flipflop 252, and at the same time resets and enables the g counter 253, and counts the video clock 202. Therefore, Fritub Flotub 2
The output of 52 generates tg shown in FIG. 15(a) during the period from when the g counter 253 counts up until the reset signal is output. The g counter inputs a numerical value corresponding to the gap g in advance to a g setting value generator 27 such as a date switch.
Load g counter 253 from 0, video clock 2
Count 02. Further, the clock counter 250 is also reset by the reset signal caused by the count up of the g counter, and the video clock is counted again.

Further, each time the comparator 251 outputs a matching output, the operation of sequentially setting the output line to "1" and setting it to "O" at the second input is repeated. Therefore, AND Kate 255-258
Decode counter output and flipflop 25 by
By performing A N D Km process on the output of 2, the first
Timing in the row direction can be generated on the display boards 205 to 208 as shown in FIG.

Next, display boards 205, 209, 21 shown in FIG.
3. Column direction timing can be generated.

That is, the VE counter 259 is a counter that counts one line of VE signals generated as described above. The count value is inputted to the comparator 260 and compared with the output of the display board vertical pixel number generator 269 set in advance. When the value of the VE counter matches the display board vertical pixel number, the comparator 260 outputs "1". At the same time, the gh counter 26-2 is reset and enabled, and the E signal is counted. Therefore, the output of the flipflop 261 generates tgh as shown in FIG. 15(b) during the period from when the gh counter 262 counts up until the reset signal is output. The gh counter inputs a count value corresponding to the gap gh in advance to a gh set value generator 2 such as a dip switch.
71 to the gh counter 262, and the VE signal is counted. Furthermore, the VE counter 259 is also reset by the reset signal caused by the count up of the gh counter.
Count the VE signal again.

Furthermore, by logically synthesizing the outputs of 255 to 258 and the outputs of 264 to 267, video enables VE(1.1) to VE(4.4) used for each individual display board can be generated.

VE signal VE (1.1) generated by the above operation
~VE When the VE signal is supplied to each individual display board according to (4.4), the main scanning period is distributed and scanning is performed with a signal corrected for the gaps g and gh between the boards, and as a result, the 16th As shown in Figure 16(a), a connected and easy-to-see image can be created.Figure 16(b) shows gaps g and g.
Although h is not corrected and all image signals are displayed as valid, it depicts a simple circle, but it is recognized as a polygon rather than a circle.

Through the above processing, it is possible to create a visually continuous and natural display by correcting gaps in the seams that occur when figures, photographs, etc. are divided and displayed on a plurality of display boards.

The time chart in FIG. 15 shows a case where four of the 16 display boards 205, 206, 209, and 210 are used for display.

In this example, in order to make the explanation easier and clearer, 16 display boards were arranged and explained, but it is obvious that the same processing means described above can be achieved even in a configuration with an increased number of display boards. Since there is, I will omit it here.

Furthermore, when displaying characters, it becomes difficult to see if the characters are missing, so the above-mentioned tg and tgh periods can be selectively eliminated. This can be done by setting the values set to the g counter and gh counter to O.

〔effect〕

As explained above, according to the present invention, an input image signal is stored, the speed at which the input image signal is stored is changed and the speed at which it is read is changed, and the reading portion is controlled. Images can be displayed.

Furthermore, by deleting part of the image signal, images such as figures can be displayed in a natural form.

[Brief explanation of the drawing]

Fig. 1...Block diagram of a display device according to the present invention, Fig. 2
Figures: Block diagram of the image processing section of the display device according to the present invention, Figure 3: Address access diagram of the memory unit, Figure 4: Connection diagram of multiple display devices, Figure 5...・
Tying chart, Figure 6: A perspective view of the display device, Figure 7: A diagram showing the principle of the recording method, Figure 8: A diagram showing details of the recording section, Figure 9...・Diagram showing the connection between the image reader and the display device, Figure 10... Display operation tying chart, Figure 11
Figure: A diagram showing an example of image display on multiple display devices. Figure 12: A diagram showing an example of conventional connection between an image reader and multiple display devices. Figure 13: Multiple display devices. Figure 14: Diagram showing the connection relationship between the
Fig. 5: A time chart of each I word when a plurality of display devices are used. Fig. 16: A diagram showing a display example. 3 is a display screen, 4 is a recording medium, 9 is a motor, 22 is a control unit, 24 is a screen processing unit, 26 is a memory unit, 27 is a write operation controller, 30 is a read operation controller, 35 is a shift register, 19 is a drive Department. ? Applicant Canon Inc.

Claims (3)

[Claims] (1) In a system having a plurality of devices that form an image on a recording medium based on an input image signal and display the formed image on a display section, the plurality of display devices use the image signal and form an image on the recording medium. means for receiving a synchronization signal for displaying the plurality of display devices; means for storing image signals received by the receiving means; and means for controlling storage and reading of image data in the storage means; Each of the control means stores a predetermined portion of the received image signal in the storage means at a predetermined speed, and reads out the predetermined portion of the signal at a speed different from the storage speed. system. (2) The image display system according to claim 1, wherein an image signal for one page is divided and enlarged and displayed on the plurality of display devices. (3) In a system that has multiple devices that display images on display units based on input image signals, when the input image for one page is divided and displayed on the multiple display devices, it is necessary to An image display system characterized in that a part of the image signal is deleted and displayed according to a gap with a display section.