JPH03163822A - Junction forming method on semiconductor substrate - Google Patents
Junction forming method on semiconductor substrateInfo
- Publication number
- JPH03163822A JPH03163822A JP30225089A JP30225089A JPH03163822A JP H03163822 A JPH03163822 A JP H03163822A JP 30225089 A JP30225089 A JP 30225089A JP 30225089 A JP30225089 A JP 30225089A JP H03163822 A JPH03163822 A JP H03163822A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- impurity
- ion implantation
- implanted region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims abstract description 30
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 238000002844 melting Methods 0.000 claims abstract description 11
- 230000008018 melting Effects 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 230000001678 irradiating effect Effects 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 238000000137 annealing Methods 0.000 abstract description 9
- -1 BF2 ions Chemical class 0.000 abstract description 4
- 238000001953 recrystallisation Methods 0.000 abstract 1
- 239000007787 solid Substances 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 5
- 230000004913 activation Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分町］ 本発明は、半導体基板への浅い接合形或方法に関する。[Detailed description of the invention] [Industrial use area] The present invention relates to a method of shallow bonding to semiconductor substrates.
本発明は、半導体基板上に不純物イオンをイオン注入し
、その後５５０ないし６００”Ｃの低温度で熱処理する
ことによって再結晶化させ、その後、再結晶化した領域
の融点（メルティング・ポイント）以内の高温度でのエ
キシマレーザ照射を行うことによって、不純物注入領域
の活性化をはかる。In the present invention, impurity ions are implanted onto a semiconductor substrate, and then recrystallized by heat treatment at a low temperature of 550 to 600"C. By performing excimer laser irradiation at a high temperature, the impurity implanted region is activated.
エキシマレーザの照射による半導体基板中への熱の分布
は高々４００入程度であるから、高濃度であって欠陥が
少なくかつ極めて浅い接合形或ができる。また、レーザ
照射のパワーが溶融温度以内であるから表面の平坦性が
保持される。Since the distribution of heat in the semiconductor substrate due to excimer laser irradiation is about 400 degrees at most, it is possible to form a highly concentrated junction with few defects and an extremely shallow junction. Furthermore, since the laser irradiation power is within the melting temperature, the surface flatness is maintained.
ＭＯＳＦＥＴを用いたメモリ装置は、微細加工技術の進
歩とともにますます大容量化の方向にある。大容里化を
実現するためには、平面的な微細加工技術と併せて、高
濃度で欠陥が少なくかつ極めて浅い接合の形成技術を確
立する必要に迫られている。Memory devices using MOSFETs are becoming increasingly larger in capacity as microfabrication technology advances. In order to achieve a large capacity, it is necessary to establish a technology for forming extremely shallow junctions with high concentration and few defects, in addition to planar microfabrication technology.
従来、Ｐ型の不純物を用いて浅い接合を形成するには、
硼素（Ｂ）や２弗化硼素（ＢＦ．）をイオン源として、
シリコン基板にイオン注入法によって注入し、電気炉ま
たはランプアニールによってその領域を活性化させてい
た。Conventionally, to form a shallow junction using P-type impurities,
Using boron (B) or boron difluoride (BF.) as an ion source,
It is implanted into a silicon substrate by ion implantation, and the region is activated by electric furnace or lamp annealing.
しかしながら、０．３５μ以下の短チャンネルＭＯＳＦ
ＥＴのような浅い接合を形成する場合には、ＢやＢＦ２
のようなＰ型の不純物は、砒素（Ａｓ）のようなＮ型の
不純物に比べて拡散定数が大きいため、不純物注入領域
の電気的活性化をはかるために必要なパワーを有するラ
ンプアニールにおい゛′ζは、２秒程境の短時間の”ノ
′Ｊ〜−ルになってしよい、安定性に欠ける問題があっ
た。However, short channel MOSF of 0.35μ or less
When forming a shallow junction such as ET, B or BF2
P-type impurities such as arsenic (As) have a larger diffusion constant than N-type impurities such as arsenic (As), so they can be used in lamp annealing with the power necessary to electrically activate the impurity implanted region. 'ζ had a problem of lack of stability, which could result in a short period of about 2 seconds.
また、イオン注入後、レーザによるアニールを用いる方
法として例えばＮｄ−’ＷＡＧレーザを用いたもの（特
開昭５５−７８５２７）や、ＸｅＣＩのエキシマレーザ
を用いたもの（＾ｐｐｌ Ｐｈｙｓ Ｌｅｔｔ １９８
２年９３８ないし９４０頁）のような短波長のパルスレ
ーザを用いてアニールを行い、欠陥の発生を少なくする
方法が提案されていた。Further, as a method of using laser annealing after ion implantation, for example, a method using a Nd-'WAG laser (JP-A-55-78527) and a method using an XeCI excimer laser (^ppl Phys Lett 198)
A method has been proposed in which annealing is performed using a short wavelength pulsed laser to reduce the occurrence of defects, such as in 2010, pp. 938-940).
〔発明が解決しようとする課題〕
イオン注入領域をレーザ照射して半導体基板を溶融させ
てイオン注入領域を活性化させることによって浅い接合
を形成するとき、液和から固相に変化するとき欠陥が発
生しやすく、また溶融するので表面の平坦化も損なわれ
でしまうおそれがあった。[Problems to be Solved by the Invention] When forming a shallow junction by irradiating the ion implantation region with a laser to melt the semiconductor substrate and activate the ion implantation region, defects occur when the ion implantation region changes from liquid to solid phase. This tends to occur, and since it melts, there is a risk that the flattening of the surface may be impaired.
本発明は、これらの課題を改善するための接合の形成方
法を提供するものである。The present invention provides a method for forming a bond to improve these problems.
本発明は、イオン注入後、５５０ないし６００゜Ｃの低
温度で熱処理して不純物注入領域の再結晶化を行い、し
かる後、短波長のパルスレーザを照射することによって
、高濃度で欠陥が少なく、かつ極めて浅い接合を形或す
ることを実現するものである。In the present invention, after ion implantation, the impurity implanted region is recrystallized by heat treatment at a low temperature of 550 to 600 degrees Celsius, and then irradiated with a short wavelength pulsed laser to achieve high concentration and fewer defects. , and it is possible to form an extremely shallow bond.
（作用〕
４
本発明のイオン注入後の低温度での熱処理によって不純
物注入領域を再結晶化させると、その領域の融点は、単
結晶シリコンの融点である１４１０゜Ｃしとなり、もと
の非晶質シリコンの融点である１１５０゜Ｃよりも高い
ので、その後のレーザ照射において、活性化に必要なパ
ワーをかけることができる。また、短波長のパルスレー
ザを用いることでシリコン基板中への熱の分布は極めて
表面だ４Ｊに限られて、浅い接合を形成することができ
る。(Function) 4 When the impurity implanted region is recrystallized by heat treatment at a low temperature after ion implantation according to the present invention, the melting point of that region becomes 1410°C, which is the melting point of single crystal silicon, and the original non-containing Since it is higher than the melting point of crystalline silicon, 1150°C, it is possible to apply the power necessary for activation in the subsequent laser irradiation.In addition, by using a short wavelength pulsed laser, the heat in the silicon substrate can be reduced. The distribution of 4J is extremely limited to the surface, making it possible to form shallow junctions.
本発明の実施例を、短チャンネルＭＯ Ｓ Ｆ ＥＴの
ソースおよびトレイン領域の浅い接合形或をｊＩう例と
して、第ｌ図ａないしｂを用いて説明する。Embodiments of the present invention will be described using FIGS. 1a and 1b as an example of a shallow junction type of source and train regions of a short channel MOSFET.
まず、第１図ａに示すように、単結晶のＮ型シリコン基
板１の表面に、イオン注入を選択的に行うためのマスク
２を設ける。このマスク２はＭＯＳＦＥＴのゲートとし
て用いる構造をなしている。First, as shown in FIG. 1a, a mask 2 for selectively implanting ions is provided on the surface of a single-crystal N-type silicon substrate 1. This mask 2 has a structure to be used as a gate of a MOSFET.
次に、Ｐ型の不純物源としてＢＦ２イオン３を用いてイ
オン注入を行い、Ｎ型シリコン基板ｌの極めて表面近傍
にのみＰ型の不純物注入領域４ａを形成する。イオン注
入条件は、ソースおよびドレイン領域として用いる場合
、低抵抗すなわち活性不純物濃度を高くする必要がある
ので、通常５×１０１ Ｓ ／ｃｍ ２程度の高ドーズ
量の注入を行う。チャンネリングテールΦ発生を抑制す
るために、あらかじめシリコンのイオン注入を行い、不
純物注入領域４ａを非晶質化しておいてもよい。この不
純物注入領域４ａは、イオン注入によるダメージによっ
て非晶質化しているので、再結晶化させるために５５０
ないし６００℃の低温度アニールを行えば、固相威長に
よって不純物注入領域４ａは再結晶化する。Next, ion implantation is performed using BF2 ions 3 as a P-type impurity source to form a P-type impurity implantation region 4a only in the very vicinity of the surface of the N-type silicon substrate l. Regarding ion implantation conditions, when used as source and drain regions, it is necessary to have low resistance, that is, high active impurity concentration, so implantation is usually performed at a high dose of about 5×10 1 S /cm 2 . In order to suppress the occurrence of channeling tail Φ, silicon ions may be implanted in advance to make the impurity implanted region 4a amorphous. This impurity implanted region 4a has become amorphous due to damage caused by ion implantation, so in order to recrystallize it,
When low-temperature annealing at a temperature of 600 to 600° C. is performed, the impurity implanted region 4a is recrystallized due to the solid phase length.
次に、第１図ｂに示すように、不純物注入領域４ａに例
えば波長が３０８ナノメートルであるＸｅＣｌエキシマ
レーザ５を照射すれば、不純物が活性化したＰ型領域４
ｂを形成することができる。このときのレーザ照射のパ
ワーは、再結晶化した不純物注入領域４ａの融点である
１４１０″Ｃ以内に設定すればよく、またイオン注入条
件に依存したＳｉ融点の変化も極めて小さくなるため、
安定したパワーで活性化が可能となり、再現性も向上ず
る。また、エキシマレーザの照射によるシリコン中への
熱の分布は、高ｈ４００入程度であるから、Ｐ型領域４
ｂの深さも同程度の横めて浅い接合を形成することがで
きる。また、溶融しない照射パワーで活性化を行うので
、Ｐ型領域４ｂの表面は平坦である。Next, as shown in FIG. 1b, if the impurity implanted region 4a is irradiated with a XeCl excimer laser 5 having a wavelength of 308 nanometers, the P-type region 4 where the impurity is activated
b can be formed. The power of the laser irradiation at this time may be set within 1410''C, which is the melting point of the recrystallized impurity implanted region 4a, and the change in the Si melting point depending on the ion implantation conditions will be extremely small.
Activation is possible with stable power and reproducibility is improved. Furthermore, since the distribution of heat in the silicon due to excimer laser irradiation is approximately h400, the P-type region 4
It is possible to form a horizontally shallow junction with the same depth b. Furthermore, since activation is performed with irradiation power that does not cause melting, the surface of the P-type region 4b is flat.
このような浅い接合形成方法を用いて短チャンネルＭＯ
ＳＦＥＴを実現することができる。Short channel MO using such a shallow junction formation method
SFET can be realized.
本発明の実施例において、Ｐ型の不純物源にＢＦ２イオ
ンを用いたがＢイオンでもよく、また、単結晶のＮ型シ
リコン基板へのＰ型領域の形或について説明したが、逆
の導電型であっても適用可能である。In the embodiments of the present invention, BF2 ions were used as the P-type impurity source, but B ions may also be used.Also, although the shape of the P-type region on a single-crystal N-type silicon substrate was explained, it is possible to use the opposite conductivity type. It is applicable even if
本発明による接合形成方法を用いれば、エキシマレーザ
のような短波長のパルスレーザによるアニールを用いて
、極めて浅く、低抵抗の接合を形成することができる。By using the junction forming method according to the present invention, an extremely shallow and low-resistance junction can be formed using annealing using a short wavelength pulsed laser such as an excimer laser.
また、あらかしめ低温度でのアニールによって不純物注
入領域を再結晶化しているので高い融点となり、アニー
ル条件が緩和され、溶融しない温度でのアニールが行え
るので表面の平坦性が保持される。In addition, since the impurity implanted region is recrystallized by preliminary annealing at a low temperature, it has a high melting point, the annealing conditions are relaxed, and the surface flatness is maintained because annealing can be performed at a temperature that does not melt.
第１図ａないしｂは本発明の接合形或を示す工程図であ
る。
１ −−−−−−−−−−−−− Ｎ型シリコン基板２
−−−一−−−一−−−マスク
３ ．−−−−−−−−−−−ＢＦ２イオン４ ａ−−
−−−−不純物注入領域
４ ｂ 一−−−−− Ｐ型領域
５ エキシマレーザFIGS. 1A to 1B are process diagrams showing a joining type of the present invention. 1 ------------- N-type silicon substrate 2
---1----1---Mask 3. ----------BF2 ion 4 a--
----- Impurity implantation region 4 b ---- P type region 5 Excimer laser
Claims (1)
純物注入領域を形成する工程と、非晶質半導体の融点の
温度以内の低温度で熱処理することによって前記不純物
注入領域を再結晶化させる工程と、短波長のパルスレー
ザを再結晶化した前記不純物注入領域の融点の温度以内
の高温度であるレーザパワーを用いて照射する工程とか
らなる半導体基板への接合形成方法。A step of forming an impurity implanted region on a semiconductor substrate by ion implantation of impurity ions, and a step of recrystallizing the impurity implanted region by heat treatment at a low temperature within the melting point of an amorphous semiconductor. 1. A method for forming a bond to a semiconductor substrate, comprising the step of irradiating a pulsed laser beam with a laser power at a high temperature within the melting point of the recrystallized impurity implanted region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30225089A JP2808749B2 (en) | 1989-11-22 | 1989-11-22 | Method of forming junction on semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30225089A JP2808749B2 (en) | 1989-11-22 | 1989-11-22 | Method of forming junction on semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03163822A true JPH03163822A (en) | 1991-07-15 |
| JP2808749B2 JP2808749B2 (en) | 1998-10-08 |
Family
ID=17906756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30225089A Expired - Fee Related JP2808749B2 (en) | 1989-11-22 | 1989-11-22 | Method of forming junction on semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2808749B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121120A (en) * | 1997-08-07 | 2000-09-19 | Nec Corporation | Method for manufacturing semiconductor device capable of flattening surface of selectively-grown silicon layer |
| KR100306434B1 (en) * | 1998-03-06 | 2001-09-24 | 윤종용 | Mask for selective growth of solid, manufacturing method thereof, and method for selectively growing solid using the same |
| WO2002099862A1 (en) * | 2001-06-04 | 2002-12-12 | Matsushita Electric Industrial Co., Ltd. | Annealing method, ultra-shallow junction layer forming method and ultr-shallow junction layer forming device |
| US6841814B2 (en) | 2002-01-11 | 2005-01-11 | Samsung Electronics Co., Ltd | Photodiode for ultra high speed optical communication and fabrication method therefor |
-
1989
- 1989-11-22 JP JP30225089A patent/JP2808749B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121120A (en) * | 1997-08-07 | 2000-09-19 | Nec Corporation | Method for manufacturing semiconductor device capable of flattening surface of selectively-grown silicon layer |
| KR100306434B1 (en) * | 1998-03-06 | 2001-09-24 | 윤종용 | Mask for selective growth of solid, manufacturing method thereof, and method for selectively growing solid using the same |
| WO2002099862A1 (en) * | 2001-06-04 | 2002-12-12 | Matsushita Electric Industrial Co., Ltd. | Annealing method, ultra-shallow junction layer forming method and ultr-shallow junction layer forming device |
| US6841814B2 (en) | 2002-01-11 | 2005-01-11 | Samsung Electronics Co., Ltd | Photodiode for ultra high speed optical communication and fabrication method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2808749B2 (en) | 1998-10-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |