JPH03163667A - Circuit diagram display method for lsi design - Google Patents

Circuit diagram display method for lsi design

Info

Publication number
JPH03163667A
JPH03163667A JP1304001A JP30400189A JPH03163667A JP H03163667 A JPH03163667 A JP H03163667A JP 1304001 A JP1304001 A JP 1304001A JP 30400189 A JP30400189 A JP 30400189A JP H03163667 A JPH03163667 A JP H03163667A
Authority
JP
Japan
Prior art keywords
signal lines
circuit diagram
bundled
line
bundle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1304001A
Other languages
Japanese (ja)
Inventor
Yumi Tanaka
由美 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP1304001A priority Critical patent/JPH03163667A/en
Publication of JPH03163667A publication Critical patent/JPH03163667A/en
Pending legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To discriminate the information of the number of bundle lines by a display by allowing the bundle line of a logic circuit diagram editor to have width or a color corresponding to the number of signal lines in the bundle line. CONSTITUTION:A bundle line 4 having eight pieces of signal lines, a bundle line 5 having five pieces of signal lines, and a bundle line 6 having three pieces of signal lines are displayed by thickness in accordance with the number of signal lines at every line kind. Or they are displayed in each separate color corresponding to the number of signal lines at every line kind. In such a way, by only looking at the circuit diagram, the number of signal lines of the bundle line is known, and at the time of connecting plural bundle lines in which the number of signal lines is different from each other, their trunk/branch relation can be discriminated immediately.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、論理設計支援システムに用いられる回路図表
示方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit diagram display method used in a logic design support system.

〔従来の技術〕[Conventional technology]

従来、この種の論理回路図エディタ上の束線の表現方法
は、束線中の信号線数とは無関係に一定の幅.色で表示
するものとなっていた。
Conventionally, the method of representing bundled lines on this type of logic circuit diagram editor was to have a fixed width regardless of the number of signal lines in the bundled line. It was supposed to be displayed in color.

第4図は従来の論理回路図エディタにおける束線の記述
方法を示すレイアウト図である。lは8本の信号線を有
する束線、2は5本の信号線を有する束線、3は3本の
信号線を有する束線であり、すべて同じ幅と″同じ色で
表示されている。
FIG. 4 is a layout diagram showing a method of describing bundled lines in a conventional logic circuit diagram editor. l is a bundled line with 8 signal lines, 2 is a bundled line with 5 signal lines, and 3 is a bundled line with 3 signal lines, all of which are displayed with the same width and the same color. .

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の論理回路図エディタにおける束線の表現
方法は、束線中の信号線数とは無関係にすべての束線1
〜3を一定の幅,色で表示するため、束線中の信号線数
が瞬時に解らない。そのため信号線数の異なる複数の束
線を接続する際に、それらの束線の信号線数を知るため
には束線の情報を記述した部分を取り出し調べなければ
ならず、それだけ工数がかかるという欠点があった。
The method of representing bundled lines in the conventional logic circuit diagram editor described above is to display all bundled lines 1 regardless of the number of signal lines in the bundled
~3 are displayed with a fixed width and color, so the number of signal lines in the bundle cannot be instantly determined. Therefore, when connecting multiple bundled wires with different numbers of signal wires, in order to know the number of signal wires in those bundled wires, it is necessary to extract and examine the part that describes the bundled wire information, which takes more man-hours. There were drawbacks.

本発明の目的は、このような欠点を除き、束線数の情報
が表示により識別できるようにしたLSI設計用回路図
表示方法を提供することにある. 〔課題を解決するための手段〕 本発明の横或は、論理回路設計支援システムに用いられ
るLSI設計用回路図表示方法において、前記回路中の
束線の信号線数の情報を抽出する第1のステップと、前
記抽出した信号線数の情報に応じて各束線に幅をもたせ
るかまたはその表示色を変えた表示データに変換する第
2のステップと、前記表示データを回路図表示手段上に
表示する第3のステップとを含むことを特徴とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for displaying a circuit diagram for LSI design, which eliminates such drawbacks and allows information on the number of bundled wires to be identified by display. [Means for Solving the Problems] In the method for displaying circuit diagrams for LSI design used in the horizontal or logic circuit design support system of the present invention, a first method for extracting information on the number of signal lines of bundled lines in the circuit; a second step of converting the display data into display data in which each bundled wire has a width or its display color is changed according to the extracted information on the number of signal lines; and a third step of displaying.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を工程順に説明するフロー図
である.本実施例は、論理回路図表示手段10上の各束
線毎の信号線数の情報の抽出する第1のステップ11と
、このステップ1lで抽出した各束線毎の信号線数の情
報の表示用データへの変換する第2のステップ12と、
その表示用データを論理回路図エディタに表示する第3
のステップ13との3過程から構成される。
FIG. 1 is a flowchart explaining an embodiment of the present invention step by step. This embodiment consists of a first step 11 of extracting information on the number of signal lines for each wire bundle on the logic circuit diagram display means 10, and information on the number of signal wires for each wire bundle extracted in step 1l. a second step 12 of converting into data for display;
The third section displays the display data in the logic circuit diagram editor.
It consists of three steps: Step 13.

第2図は本実施例の論理回路図エディタにおける幅によ
る束線の記述方法を示すレイアウト図である9本実施例
は、8本の信号線を有する束線4、5本の信号線を有す
る束線5、3本の信号線を有する束線6とが、各線種毎
に信号線数に応じた太さで表示されている。
Figure 2 is a layout diagram showing how to describe bundled lines by width in the logic circuit diagram editor of this embodiment. A bundled line 5 and a bundled line 6 having three signal lines are displayed with a thickness corresponding to the number of signal lines for each line type.

第3図は本実施例の論理回路図エディタにおける束線数
を色により異らせた記述方法を示すレイアウト図である
。このでは色の代わりに模様を用いて表現しているが、
8本の信号線を有する束線7を黄色、5本の信号線を有
する束線8を緑色、3本の信号線を有する束線9を赤色
で表示してあり、各線種毎に信号線数に応じた色別に表
示されている。
FIG. 3 is a layout diagram showing a description method in which the number of wire bundles is varied depending on the color in the logic circuit diagram editor of this embodiment. In this example, patterns are used instead of colors,
The wire bundle 7 with eight signal wires is shown in yellow, the wire bundle 8 with five signal wires is shown in green, and the wire bundle 9 with three signal wires is shown in red. They are displayed in different colors depending on the number.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明により、論理回路図エディタ
上の束線に、束線中の信号線数に応じた幅あるいは色を
もたせることができるので、回路図を見ただけで束線の
信号線数を知り、信号線数の異なる複数の束線を接続す
る際にそれらの幹枝関係を直ちに判別できるという効果
がある。
As explained above, according to the present invention, it is possible to give the bundled lines on the logic circuit diagram editor a width or color that corresponds to the number of signal lines in the bundled wires. By knowing the number of lines, it is possible to immediately determine the trunk-branch relationship between a plurality of wire bundles with different numbers of signal lines when connecting them.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を工程順に示したフロー図、
第2図,第3図は本実施例の束線記述方法を示したレイ
アウト図、第4図は従来の論理回路図エディタにおける
束線の記述方法を示したレイアウト図である。 1,4.7・・・信号線8本の束線、2.5.8・・・
信号線5本の束線、3,6.9・・・信号線3本の束線
、11〜14・・・処理ステップ。
FIG. 1 is a flow diagram showing an embodiment of the present invention in the order of steps;
2 and 3 are layout diagrams showing the bundled line description method of this embodiment, and FIG. 4 is a layout diagram showing the bundled line description method in a conventional logic circuit diagram editor. 1,4.7...Bundle of 8 signal lines, 2.5.8...
Bundled wires of five signal lines, 3, 6.9... Bundled wires of three signal wires, 11-14... Processing steps.

Claims (1)

【特許請求の範囲】[Claims] 論理回路設計支援システムに用いられるLSI設計用回
路図表示方法において、前記回路中の束線の信号線数の
情報を抽出する第1のステップと、前記抽出した信号線
数の情報に応じて各束線に幅をもたせるかまたはその表
示色を変えた表示データに変換する第2のステップと、
前記表示データを回路図表示手段上に表示する第3のス
テップとを含むことを特徴とするLSI設計用回路図表
示方法。
In a circuit diagram display method for LSI design used in a logic circuit design support system, a first step of extracting information on the number of signal wires in bundled wires in the circuit, and a second step of converting into display data in which the bundled lines are given width or their display colors are changed;
A circuit diagram display method for LSI design, comprising a third step of displaying the display data on a circuit diagram display means.
JP1304001A 1989-11-21 1989-11-21 Circuit diagram display method for lsi design Pending JPH03163667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1304001A JPH03163667A (en) 1989-11-21 1989-11-21 Circuit diagram display method for lsi design

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1304001A JPH03163667A (en) 1989-11-21 1989-11-21 Circuit diagram display method for lsi design

Publications (1)

Publication Number Publication Date
JPH03163667A true JPH03163667A (en) 1991-07-15

Family

ID=17927863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1304001A Pending JPH03163667A (en) 1989-11-21 1989-11-21 Circuit diagram display method for lsi design

Country Status (1)

Country Link
JP (1) JPH03163667A (en)

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