JPH0316111A - Semiconductor wafer and manufacture thereof and method of selection of semiconductor chip - Google Patents

Semiconductor wafer and manufacture thereof and method of selection of semiconductor chip

Info

Publication number
JPH0316111A
JPH0316111A JP3543190A JP3543190A JPH0316111A JP H0316111 A JPH0316111 A JP H0316111A JP 3543190 A JP3543190 A JP 3543190A JP 3543190 A JP3543190 A JP 3543190A JP H0316111 A JPH0316111 A JP H0316111A
Authority
JP
Japan
Prior art keywords
semiconductor
chips
wafer
chip
semiconductor chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3543190A
Other languages
Japanese (ja)
Other versions
JP2964522B2 (en
Inventor
Noboru Kusama
草間 昇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2035431A priority Critical patent/JP2964522B2/en
Publication of JPH0316111A publication Critical patent/JPH0316111A/en
Application granted granted Critical
Publication of JP2964522B2 publication Critical patent/JP2964522B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54406Marks applied to semiconductor devices or parts comprising alphanumeric information
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448Located on chip prior to dicing and remaining on chip after dicing

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To discriminate easily individual semiconductor chips which are manufactured in the same wafer by providing reference number patterns in individual semiconductor chips so that the semiconductor chips having the same forms are discriminated individually. CONSTITUTION:Semiconductor chips 2 are formed on a semiconductor wafer 1 and semiconductor chip identification patterns 30 which discriminate kinds of the semiconductor chips and marks of reference number patterns 20 which discriminate individual chips are provided respectively. The formation of the semiconductor chip identification patterns 30 and the reference number patterns 20, for example, allows the reference number patterns and the like to be formed at a mask which exposes the semiconductor wafer at a time and further, its formation is performed by transferring the above patterns onto the semiconductor wafer. Individual semiconductor chips 2 which are manufactured in the same wafer 1 are discriminated easily.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体ウェハー及びその製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor wafer and a method for manufacturing the same.

〔従来の技術〕[Conventional technology]

従来より、半導体装置の製造工程において、同一半導体
ウェハー上に同一種類又は、複数の種類の半導体チップ
を同時に製作されている。同一半導体ウェハー上に製作
された複数の半導体チップは、ウェハー状態のままで試
験が行なわれ、良否判定の結果、不良品に対して機械的
紅傷やインク等のマークをつけ、後工程において、この
マークを参照しながら良品が、抜き取られ、使用されて
いた。
Conventionally, in the manufacturing process of semiconductor devices, the same type or a plurality of types of semiconductor chips have been simultaneously manufactured on the same semiconductor wafer. Multiple semiconductor chips manufactured on the same semiconductor wafer are tested in the wafer state, and as a result of the pass/fail judgment, defective products are marked with mechanical red marks, ink, etc., and in the subsequent process, Good products were selected and used while referring to this mark.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体ウェハー上には同一種類の半導体
チップは特に個々に区別されることなく製造され、良品
と判定されたチップは一括して区別なく良品として使用
されていた。しかし、チ、ップをマイクロ波等の高周波
帯で使用したい場合や、チップ内の相互コンダクタンス
やドレイン・ソース飽和電流の値によりチップの用途を
区別してより効果的に使用したい場合、又、チップ内の
トランジスタの耐電圧の値を管理して使用することによ
り、特に耐電圧の高いものをより厳しい使用条件で用い
る場合等、個々の半導体チップについての検査結果や、
取扱いの履歴を明確に記録する必要が生じても、また色
々の特性を総合的に判断して、より良い物から順に使用
する必要が生じても、従来の半導体ウェハーではチップ
が個々に区別されていないため、このようなことは実際
上不可能であった。また高周波特性にすぐれたGaAs
半導体ウェハーの試験では不良品に対して機械的な傷を
付ける方法(スクラッチマーカー)を行なうと、試験後
に行なう個々のチップへの分割(スクライブ)時にその
傷かもとで良品チップにもチ、ソプに割れ2かけが生じ
てしまうといった欠点があった。またレザーにより傷を
付ける方法(レーザーマーカー)はGaAs基板中のヒ
素がじょうはつじ人体に有害であると言った問題とG 
a A s半導体ウェハーで一般的に配線材料として使
用される金がボール状に飛んで他のチ,ップをよごした
り試験に使用する針をよごしたりする問題があった。
On the above-mentioned conventional semiconductor wafer, semiconductor chips of the same type are manufactured without being particularly distinguished from each other, and chips determined to be non-defective are collectively used as non-defective products without distinction. However, if you want to use the chip in a high frequency band such as microwave, or if you want to use the chip more effectively by distinguishing the chip's purpose based on the value of mutual conductance or drain-source saturation current, or if you want to use the chip more effectively, By controlling and using the withstand voltage value of the transistors in the chip, it is possible to check the inspection results of individual semiconductor chips, especially when using those with high withstand voltage under more severe usage conditions.
Even if it becomes necessary to clearly record the handling history, or if it becomes necessary to comprehensively judge various characteristics and use the ones in order of quality, conventional semiconductor wafers do not distinguish between individual chips. This was practically impossible because there was no such thing. In addition, GaAs has excellent high frequency characteristics.
When testing semiconductor wafers, if mechanical scratches (scratch markers) are used on defective products, good chips may also be scratched under the scratches when they are divided into individual chips (scribe) after the test. There was a drawback that two cracks were generated. In addition, the method of making scratches with laser (laser marker) has problems such as the fact that arsenic in GaAs substrates is often harmful to the human body.
There has been a problem in that gold, which is commonly used as a wiring material in semiconductor wafers, flies off in the form of balls and contaminates other chips and the needles used for testing.

本発明の目的は、同一ウェノ)一内で作戒された個々の
半導体チップを容易に区別することができる半導体ウェ
ノ・一及びその製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor wafer and a method for manufacturing the same that allow easy differentiation of individual semiconductor chips made within the same wafer.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体ウェノ・一は、同一基板上に複数の半導
体チップが形或される半導体ウエl1−において、前記
複数の半導体チップがすべて個別に識別できるようなマ
ークを前記アドレスチップにそれぞれ設けたことを特徴
とする。
In the semiconductor wafer 1 of the present invention, in a semiconductor wafer l1- in which a plurality of semiconductor chips are formed on the same substrate, a mark is provided on each of the address chips so that all of the plurality of semiconductor chips can be individually identified. It is characterized by

または、上記半導体ウヱ)S−を製造するために、ウェ
ハー製造工程で使用されるマスクの中でウェハー全体を
一度に露出するマスクに識別マークを設けたことを特徴
とする。
Alternatively, the present invention is characterized in that an identification mark is provided on a mask that exposes the entire wafer at once among the masks used in the wafer manufacturing process in order to manufacture the semiconductor wafer S-.

または、検査データと識別マークとの関係を使用して希
望のチップを選択することを特徴とする。
Alternatively, the present invention is characterized in that a desired chip is selected using the relationship between inspection data and identification marks.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を説明するための半導体ウェ
ハーの平面図である。同図に示すように、半導体ウェハ
ー1上に半導体チップ2が形成されている。それぞれの
半導体チップ2には、本実施例の場合、半導体チップの
種類を区別する半導体チップ識別パターン30と、個々
のチップを区別するための照合番号パターン20のマー
クがそれぞれ設けられている。
FIG. 1 is a plan view of a semiconductor wafer for explaining one embodiment of the present invention. As shown in the figure, a semiconductor chip 2 is formed on a semiconductor wafer 1. In this embodiment, each semiconductor chip 2 is provided with marks such as a semiconductor chip identification pattern 30 for distinguishing the type of semiconductor chip and a reference number pattern 20 for distinguishing between individual chips.

このような半導体チップ識別パターン30や、照合番号
パターン20の形或は、例えば、半導体ウェハーを一度
に露光するマスクに照合番号パターン等を形或させてお
けば容易に半導体ウェハー上に転写することができる。
If the semiconductor chip identification pattern 30 or the reference number pattern 20 is formed in the form of such a semiconductor chip identification pattern 30 or the reference number pattern 20, or if the reference number pattern is formed on a mask that exposes the semiconductor wafer at once, it can be easily transferred onto the semiconductor wafer. I can do it.

又、照合番号パターン20形成専用のマスクを使用して
も可能である。更に、同一ロットで製造される半導体ウ
ェハーの数だけ照合番号を変えたマスクを用意すれば同
一ウェハー内だけではなく、同一ロットでの半導体チッ
プを全て個々に区別して管理する事が可能になる。
It is also possible to use a mask dedicated to forming the verification number pattern 20. Furthermore, by preparing masks with different identification numbers corresponding to the number of semiconductor wafers manufactured in the same lot, it becomes possible to individually distinguish and manage not only the semiconductor chips in the same wafer but also all the semiconductor chips in the same lot.

第2図は、第1図の部分拡大図である。同図に示すよう
に、個々の半導体チップ2上に設けられた保護膜、又は
、パシベーション膜に照合番号パターン20が形成され
る。
FIG. 2 is a partially enlarged view of FIG. 1. As shown in the figure, a reference number pattern 20 is formed on a protective film or a passivation film provided on each semiconductor chip 2.

このような構戊であれば、第1図及び第2図で示すよう
な半導体チップ識別パターンがAのもののような同一形
式の半導体チップを個別に区別することが容易にできる
。従って、例えば個々の低周波特性の差が半導体装置と
総合特性に影響する様なマイクロ波帯等の高周波で使用
する半導体装置においては、個々のチップの識別が可能
であるので、容易に低周波特性が一致させることが可能
になる。更に、チップ内の電界効果トランジスタの相互
コンダクタンスや、ドレイン・ソース飽和電流の個々の
チップの値の管理や、耐電圧のより高いものを選択して
使用することなどが可能となる。
With such a structure, semiconductor chips of the same type, such as the semiconductor chip identification pattern A shown in FIGS. 1 and 2, can be easily distinguished. Therefore, for example, in semiconductor devices used at high frequencies such as microwave bands, where differences in individual low-frequency characteristics affect the semiconductor device and overall characteristics, it is possible to identify individual chips, so it is easy to It becomes possible to match the characteristics. Furthermore, it becomes possible to manage the mutual conductance of field effect transistors within a chip and the drain-source saturation current values of each chip, and to select and use those with higher withstand voltages.

第3図は、本発明の他の実施例を説明するための半導体
チップの平面図である。同図に示すように、本実施例で
は、照合番号パターン20を半導体材料部3上に形或す
るため、半導体チップ2内の回路形成に利用できる領域
の面積が広くなる利点を有している。本実施例では、照
合番号パターン20を半導体材そのものに形或する他に
、保護膜やパシベーション膜,導体層,ポリイミド等を
半導体材部3上に適当な形状で残すことにより照合番号
パターン20を形成することも可能である。
FIG. 3 is a plan view of a semiconductor chip for explaining another embodiment of the present invention. As shown in the figure, in this embodiment, since the identification number pattern 20 is formed on the semiconductor material portion 3, there is an advantage that the area that can be used for circuit formation within the semiconductor chip 2 becomes larger. . In this embodiment, in addition to forming the identification number pattern 20 on the semiconductor material itself, the identification number pattern 20 is formed by leaving a protective film, a passivation film, a conductor layer, polyimide, etc. in an appropriate shape on the semiconductor material part 3. It is also possible to form

最近の微細パターンを有する半導体ウェハーの製造にお
いては、半導体ウェハーの部分的な露光を繰返す方法(
ステッパー)が使用されている。
In recent years, in the production of semiconductor wafers with fine patterns, a method of repeatedly exposing semiconductor wafers partially (
stepper) is used.

一方、半導体チップを電気的に接続するためには、端子
電極10の上の保護膜又はバシベーション膜4を除去し
なければならない。この時に使用される露光マスクとし
ては、露光すべきパターンが微細でないため、また識別
に使用するマークも見やすさのため太いマークとするた
めウェハー全体を一度に露光する方法(例えばコンタク
トマスクを用いた露光)を使用出来る。製造方法の一例
として、上述の様に保護膜又はパシベーション膜の開口
に使用するマスクをコンタクトマスクとし個々のチップ
を個別に識別できるマークを使用する方法がある。この
方法によれば、チップに付けるマークが最上層に位置す
るため見やすいと言った特長もある。
On the other hand, in order to electrically connect the semiconductor chips, the protective film or passivation film 4 on the terminal electrode 10 must be removed. The exposure mask used at this time is a method of exposing the entire wafer at once (for example, using a contact mask) because the pattern to be exposed is not minute and the marks used for identification are thick marks for easy visibility. Exposure) can be used. As an example of a manufacturing method, as described above, there is a method in which a mask used for openings in a protective film or a passivation film is used as a contact mask, and a mark is used to individually identify each chip. This method also has the advantage that the mark placed on the chip is located on the top layer, making it easy to see.

上述のような個々のチップに識別できるマークが付いて
いるためチップを個々に分割した後に、試験データを総
合的に判断し、チップを選択する方法が実現出来る。
Since each chip has an identifiable mark as described above, it is possible to divide the chips into individual chips and then comprehensively judge the test data to select the chip.

以上説明した両実施例では、照合番号パターン等のマー
クを文字で表したが、本発明はそれに限定されることな
く適当な記号又は文字と記号の組合せでも可能である。
In both of the embodiments described above, the mark such as the reference number pattern is represented by characters, but the present invention is not limited thereto, and may be any suitable symbol or a combination of characters and symbols.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は同一形式の半導体チップ
を個々に区別できるような照合番号パターンを個々の半
導体チップに設けることにより、同一ウェハー内で作成
された個々の半導体チッソを容易に区別することができ
るため個々半導体チップの詳細な特性の管理が可能とな
る。
As explained above, the present invention provides a reference number pattern on each semiconductor chip that allows semiconductor chips of the same type to be individually distinguished, thereby making it easy to distinguish between individual semiconductor chips manufactured on the same wafer. This makes it possible to manage detailed characteristics of individual semiconductor chips.

個々のチップに識別出来るマークが付いているため、チ
ップの試験後に行なうチップ分割ののちに、試験データ
を総合的に判断して、より良いチップを優先的に使用す
る事が可能となる。また、機械的にもろいGaAs半導
体ウェハーの場合にはチップ分割時に良品チップを含め
てのチップ割れ,欠けを生じさせる原因となるチップ表
面上のキズな付けないですむと言った効果も有る。
Since each chip has a mark that can be identified, it is possible to comprehensively judge the test data and use better chips preferentially after chip division after chip testing. In addition, in the case of mechanically fragile GaAs semiconductor wafers, there is also the effect that there is no need to create scratches on the chip surface, which would cause chip cracking and chipping, including good chips, when dividing the chips.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を説明するための半導体ウェ
ハーの平面図、第2図は第1図の部分拡大図、第3図は
本発明の他の実施例を説明するための半導体チップの平
面図である。 l・・・・・・半導体ウェハー 2・・・・・・半導体
チップ、3・・・・・・半導体材料部、4・・・・・・
保護膜又はパシベーション膜、20・・・・・・照合番
号パターン、30・・・・・・半導体チップ識別パター
ン。 菊1図
FIG. 1 is a plan view of a semiconductor wafer for explaining one embodiment of the present invention, FIG. 2 is a partially enlarged view of FIG. 1, and FIG. 3 is a plan view of a semiconductor wafer for explaining another embodiment of the present invention. FIG. 3 is a plan view of the chip. l...Semiconductor wafer 2...Semiconductor chip, 3...Semiconductor material part, 4...
Protective film or passivation film, 20...Verification number pattern, 30...Semiconductor chip identification pattern. Chrysanthemum 1

Claims (1)

【特許請求の範囲】 1、同一基板上に複数の半導体チップが形成される半導
体ウェハーにおいて、前記複数の半導体チップが、すべ
て個別に識別できるようなマークを前記半導体チップに
それぞれ設けたことを特徴とする半導体ウェハー。 2、チップの電極部分を開口するためのマスク内に個々
の半導体チップを識別できるマークを設け、当該マスク
を用いて製造することを特徴とする半導体ウェハーの製
造方法。 3、半導体ウェハーの試験データーを総合的に判断し、
個々の半導体チップを識別するマークを利用して、より
特性の良いチップを優先的に選んで使用する事を特徴と
する半導体チップの選別方法。
[Claims] 1. A semiconductor wafer in which a plurality of semiconductor chips are formed on the same substrate, characterized in that a mark is provided on each of the semiconductor chips so that each of the plurality of semiconductor chips can be individually identified. semiconductor wafer. 2. A method for manufacturing a semiconductor wafer, characterized in that marks for identifying individual semiconductor chips are provided in a mask for opening electrode portions of the chips, and manufacturing is performed using the mask. 3. Comprehensive judgment of semiconductor wafer test data,
A semiconductor chip sorting method characterized by using marks for identifying individual semiconductor chips to preferentially select and use chips with better characteristics.
JP2035431A 1989-03-03 1990-02-15 Semiconductor wafer, method of manufacturing the same, and method of selecting semiconductor chips Expired - Fee Related JP2964522B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2035431A JP2964522B2 (en) 1989-03-03 1990-02-15 Semiconductor wafer, method of manufacturing the same, and method of selecting semiconductor chips

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2491089 1989-03-03
JP1-24910 1989-03-03
JP2035431A JP2964522B2 (en) 1989-03-03 1990-02-15 Semiconductor wafer, method of manufacturing the same, and method of selecting semiconductor chips

Publications (2)

Publication Number Publication Date
JPH0316111A true JPH0316111A (en) 1991-01-24
JP2964522B2 JP2964522B2 (en) 1999-10-18

Family

ID=26362488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2035431A Expired - Fee Related JP2964522B2 (en) 1989-03-03 1990-02-15 Semiconductor wafer, method of manufacturing the same, and method of selecting semiconductor chips

Country Status (1)

Country Link
JP (1) JP2964522B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250650A (en) * 2006-03-14 2007-09-27 Sharp Corp Nitride semiconductor laser element and its manufacturing method
JP2010225934A (en) * 2009-03-24 2010-10-07 Mitsumi Electric Co Ltd Method of manufacturing wafer
WO2015000263A1 (en) * 2013-07-04 2015-01-08 京东方科技集团股份有限公司 Exposure device and exposure method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007250650A (en) * 2006-03-14 2007-09-27 Sharp Corp Nitride semiconductor laser element and its manufacturing method
US7804878B2 (en) 2006-03-14 2010-09-28 Sharp Kabushiki Kaisha Nitride semiconductor laser device and method of producing the same
JP4660400B2 (en) * 2006-03-14 2011-03-30 シャープ株式会社 Manufacturing method of nitride semiconductor laser device
US8059691B2 (en) 2006-03-14 2011-11-15 Sharp Kabushiki Kaisha Nitride semiconductor laser device and method of producing the same
US8124431B2 (en) 2006-03-14 2012-02-28 Sharp Kabushiki Kaisha Nitride semiconductor laser device and method of producing the same
JP2010225934A (en) * 2009-03-24 2010-10-07 Mitsumi Electric Co Ltd Method of manufacturing wafer
WO2015000263A1 (en) * 2013-07-04 2015-01-08 京东方科技集团股份有限公司 Exposure device and exposure method thereof

Also Published As

Publication number Publication date
JP2964522B2 (en) 1999-10-18

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