JPS61182214A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To enable to avoid a function test of chips by associating an improper recognition mark on a chip which might be defective in a pattern adjacent to the inner peripheral side of the chip of the outermost periphery of a wafer. CONSTITUTION:Integrated circuit pattern forming chips 2 are formed in a matrix in a semiconductor wafer 1. Improper recognition marks 3 are formed on the positions which might become defective in the pattern directly adjacent to the inner peripheral side. Thus, when a wafer is tested, the chip 3 with the mark is avoided for the function test to increase the efficiency of the test and to prevent an inspecting unit from damaging.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a formation form when a plurality of semiconductor integrated circuit element tips are formed in a checkerboard shape within one semiconductor wafer.

[Conventional technology]

Conventionally, semiconductor integrated circuit devices have a plurality of integrated circuit patterns arranged in a matrix on a semiconductor wafer, and as necessary, the finish of the wafer process is checked at several locations in the arrangement using electrical or other physical means. Usually, test patterns are arranged and arranged over the entire semiconductor wafer.

In the case of So-C1 high-performance semiconductor integrated circuit device, 7 to 1
After 0 photolithography steps, the necessary patterns are sequentially created on a semiconductor wafer. Therefore, it is well known that in photolithography, when ultraviolet rays or X-rays are used to transfer each pattern, an exposure mask is required, but when an electron beam is used, direct drawing can be performed without an exposure mask. It is as follows.

[Problem that the invention seeks to solve]

By the way, with the current technology, it cannot be expected that all the naps on a semiconductor wafer that have undergone the above-mentioned wafer process are of good quality.

Therefore, it is necessary to electrically check and sort out whether the individual chips are good or defective in the wafer state.

However, since wafers are usually circular, there are chips on the outermost periphery whose chip shape has been significantly deformed from the original rectangular shape, and these are naturally chips whose original circuit patterns have been damaged. When a chip is subjected to the same functional test as a normal chip, an abnormal current flows, damaging the test probe and even damaging the expensive integrated circuit testing equipment.

This invention has been made to solve the above-mentioned problems, and provides a method that can easily avoid functional testing of chips on the outer periphery of a wafer, improve inspection efficiency, and prevent damage to inspection equipment. The purpose is to

[Means for solving problems]

In the semiconductor wafer/% according to the present invention, an integrated circuit pattern is not formed from the beginning on the chips existing on the outermost periphery and the chips directly adjacent to the inner periphery that may cause defects in the formed pattern. A defect recognition mark is incorporated into the chip so that it can be optically easily recognized as a defective chip.

[For production]

As described above, by incorporating the chip Ktli defect recognition mark that is directly adjacent to the tip and the inner circumference of the outermost periphery of the semiconductor wafer, which may cause defects in the formed pattern, it is possible to detect defects during wafer testing. By recognizing the defect recognition mark, it is possible to avoid functional testing for that chip.

〔Example〕

FIG. 1 is a plan view showing an embodiment of the present invention. As shown in the figure, integrated circuit pattern forming chips (2) are formed in a matrix (checkerboard shape) on a semiconductor quadrant (1). However, defective gw & mark forming chips (3) are formed at the outermost periphery of the wafer (1) and directly adjacent to the inner periphery of the wafer (1) at locations where defects may occur in the formed pattern.

FIGS. 2(a) to 2(f) are cross-sectional views showing the main stages of the electron beam direct lighting method used for pattern formation, taking the electrode wiring work 8 as an example. As shown in FIG. 2(b), on one side of the semiconductor wafer (1) which has completed the predetermined manufacturing process before the electrode wiring process as shown in FIG. (Ae) layer (4) is formed by sputtering. Next, as shown in FIG. 2(c), an electron beam photosensitive resin layer (5) is coated on the negative side of the M layer (4). Continued "C1 As shown in FIG. 2(d), the electron beam E is selectively irradiated according to the desired electrode wiring pattern or defect recognition mark pattern. After the electron beam exposure light r, development is performed, as shown in FIG. 2(d). As shown in e), a desired electron beam photosensitive resin pattern (5a) is formed.

When the A1 layer (4) is etched using this as a mask, a desired M pattern (4a
) is completed.

Specific examples of the integrated circuit (electrode wiring) pattern and defect recognition mark pattern obtained by the above steps are shown in FIGS. 3(a) and 3(b), respectively. The integrated circuit pattern (6) of the integrated circuit pattern forming chip (2) is usually wired vertically and horizontally on the chip (2) with a width and spacing of about 2 μm, and is a very complicated pattern, with no defect recognition marks. The defect recognition mark pattern (7) of the formed chip (3) can be a pattern clearly different from the integrated circuit pattern (6).

Therefore, during the Ueno test, the functional test for the defect recognition mark forming chip (3) can be avoided, and the efficiency of the test can be improved and damage to the testing device can be prevented.

In the above embodiment, the I/1AI three electrode wiring process was described, but it goes without saying that the defect recognition mark pattern may be formed in the polysilicon patterning process.

〔Effect of the invention〕

As explained above, in the present invention, in a semiconductor wafer in which a plurality of semiconductor integrated circuit element tips are formed in a checkerboard pattern, a pattern is formed directly adjacent to the outermost chip of the wafer and the inner peripheral side thereof. Instead of an integrated circuit pattern, we have formed a defect recognition mark pattern that can be easily distinguished from the integrated circuit pattern on chips that are likely to have defects, so during wafer testing, we can recognize this mark pattern and eliminate unnecessary chips. It can also be omitted to improve testing efficiency0 It also has the effect of preventing damage to inspection equipment caused by testing imperfectly formed integrated circuit device chips.Additionally, separating the wafer into chips Even in practical pancaging, if chips with the defect recognition mark pattern are mixed in, they can be immediately removed, which has the effect of increasing work efficiency.

[Brief explanation of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention, and FIG.
) to (f) k′i Cross-sectional views showing the state a at the main stage to explain the electron beam direct exposure method used for pattern formation in this example, FIGS. 3(a) and (
b) is a plan view showing specific examples of an integrated circuit pattern and a defect recognition mark pattern used in the present invention; In the figure, (1) is a semiconductor wafer, and (2) is a semiconductor integrated circuit element chip (integrated circuit pattern forming chip).
, +3) is a defective recognition mark forming chip, (6) is an integrated circuit pattern, and (7) is a defective recognition mark pattern. Agent Ken Hayase - Figure 1 I, Semiconductor Uyuha 2, '$-# Turning part \0 Turn shape to hand 0J, defective chopsticks 7# Betotsufu. Figure 2 (0)l

Claims (1)

[Claims] (1) In a semiconductor wafer in which a plurality of semiconductor integrated circuit element chips are formed in a checkerboard pattern, defects may occur in the formed pattern directly adjacent to the outermost chip and its inner peripheral side. A semiconductor wafer characterized in that a defect recognition mark pattern that can be easily distinguished from the integrated circuit pattern is formed on the chip instead of the above-mentioned integrated circuit pattern.