JPH03160533A - Memory display trace system - Google Patents

Abstract

PURPOSE:To easily execute fault analysis by displaying the contents of a designated memory at real time and monitoring an operating state. CONSTITUTION:A time interruption processing part 6 is activated for each interrupting signal 20 to be outputted by a timer 3. At first, the timer interruption processing part 6 discriminates whether a trace mode is set or not. When the trace mode is set, address set caused by plural switches 1 is made effective and with the setting state as a memory address, the contents of the corresponding memory are read out and displayed. Then, the processing is finished. Thus, during the operation of a device to which attention is paid, the contents of the memory are displayed at real time. Thus, the fault analysis is made easy and since the time of the processing caused by interruption is short, the operation of the device is not affected by the processing.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a memory display tracing method, and aims to monitor the operating status by displaying the contents of a specified memory in real time. This is a memory display trace method that displays the memory contents in real time while the device is operating in an input/output device that has an operation panel, and includes a timer that generates an interrupt signal at predetermined intervals, and a timer that is activated by the interrupt signal and enters trace mode. If set, the setting state by the switch is used as a memory address to read and display the memory contents and the process ends; if the setting state by the switch is not set to trace mode, it is determined whether the setting state by the switch is a trace mode instruction or not. and a timer interrupt processing section that sets the trace mode and terminates processing if the trace mode is specified, and refers to the memory addresses set by the plurality of switches for each interrupt signal generated at predetermined time intervals. It is configured to read and display the corresponding memory contents.

[Industrial application field]

The present invention relates to a memory display tracing method for displaying the contents of a designated memory in real time while a device is operating.

[Prior Art and Problems to be Solved by the Invention] In data processing devices, a tracing method is widely used in which operating states are stored in a memory for tracing one by one, and output when a failure occurs for use in failure analysis.

In this method, when the number of data items to be traced increases, a large capacity trace memory is required, which increases the cost of input/output devices such as printers, and there is a risk that trace processing may affect the operation of the device. be.

Another problem is that it takes time to track and analyze the data of interest from the output list.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a simple memory display tracing method that specifies a memory address and displays the memory contents in real time.

[Means to solve the problem]

In order to achieve the above object, the memory display tracing method of the present invention is applied to a human output device having an operation panel equipped with a plurality of switches 1 and a display 2, as shown in the configuration diagram of an embodiment in FIG. , a timer 3 that generates an interrupt signal 20 at predetermined intervals, and a timer 3 that is activated by the interrupt signal 20, and if set to trace mode, reads and displays the contents of the corresponding memory using the setting state of switch l as address information. After completing the processing, if the trace mode is not set, the timer interrupt processing unit 6 determines whether the setting state of the switch 1 indicates the trace mode instruction or not, and if the trace mode instruction is specified, sets the trace mode and terminates the processing. and.

[Effect]

The timer interrupt processing unit 6 is activated every time the timer 3 outputs an interrupt signal 20.

The timer interrupt processing unit 6 first determines whether the trace mode is set.

As a result, if the trace mode is not set, the setting state by the switch 1 is determined, and if the trace mode is specified, the trace mode is set and the process ends. Further, if the trace mode is not specified, the process is immediately terminated.

If set to trace mode, multiple switches 1
The address setting becomes effective, the setting state is used as the memory address, the contents of the corresponding memory are read and displayed, and the process ends. As described above, the operator first sets the state of the switch 1 to trace mode instruction, and then sets the memory address to be traced to the switch 1, and thereafter the predetermined memory contents are read and displayed at predetermined time intervals.

This makes failure analysis easier because the memory contents of the target device are displayed in real time while the device is operating.
Furthermore, since the processing time due to the interrupt is short, it does not affect the operation of the device.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram of one embodiment, and FIG. 2 is an operation flowchart.

FIG. 1 shows the main parts of an input/output device such as a printing device, and shows an example in which a part of a panel switch built into the device is shared as a plurality of switches l. In the figure, reference numeral 1 indicates six return type switches, six of which are used to set a 24-bit width memory address, and one of them is used to set a trace mode.

Reference numeral 2 denotes a 16-character display, which is composed of an LCD display element or the like, and displays the contents of the display register l1.

A timer 3 outputs an interrupt signal 20 to the MPII 4 at every time set in a timer setting register 9.

5 is a 32-bit wide memory; 6 is a timer interrupt processing unit which is activated every interrupt signal 20 generated by the timer 3 and performs trace mode setting and display processing of memory contents.

Reference numeral 7 is a flag, an area of which is provided in the memory 5, and is set to "1" in the trace mode.

8 is a memory area designated as a trace target, and this figure shows the contents of address [003000] (in hexadecimal notation).

Reference numeral 9 denotes a timer setting register in which data for a predetermined period of time is set during initial setting or the like.

Reference numeral 10 denotes a switch register, which is composed of an independent 4-bit counter corresponding to each switch of the switch 1, and performs a count amplification when the corresponding switch 1 is pressed. Further, the value of each counter is converted into a hexadecimal character code and set in the upper six digits of the display register 11.

Reference numeral 11 denotes a display register in which the memory address and the memory contents expressed in hexadecimal are set by the timer interrupt processing unit 6.

Reference numeral 4 denotes a 32-bit microprocessor MPU, which controls input/output as well as the above-mentioned parts.

Among the panel switches built into input/output devices such as printing devices, the six switches l are those that are unnecessary during normal operation, such as "buzzer reset". Use switches such as "cancel" and allocate six of them for setting a 24-bit wide address, and one of them for specifying a trace mode.

The six switches 1 for address setting each have a width of 4 bits, corresponding to each digit in hexadecimal notation, and the value corresponding to the number of times the switch is pressed is set in the switch register 10, and the value is in hexadecimal notation. Displayed in the upper six digits of display 2.

Note that the address setting using switch 1 becomes effective after the trace mode is set. When displaying a trace of the memory contents during device operation, the operator presses the trace mode setting switch, then sets the address by setting the value of each digit according to the number of times each switch 1 is pressed while looking at display 2. I do.

Trace display control by the interrupt processing unit 6 will be explained below.

(1) Refer to flag 7 to determine whether the mode is trace mode.

(2) In trace mode, read the switch register 10 (in the example shown, address 0030001), read the contents of the memory 5 using that data as a memory address, convert it to hexadecimal display (4E56 FFCC), and display it in the display register. Set it to the last 9 digits of l1 and end the process.

As a result, the contents of the display register 11 are displayed on the display 2 together with the set memory address.

(3) If not in trace mode, switch register l
It reads the contents of O and determines whether or not it is a trace mode instruction. If it is not a trace mode instruction, it ends the process as is. If it is a trace mode instruction, it sets flag 7 to "1" and sets the trace mode. Finish the process.

The above processing is performed every time an interrupt occurs, so after instructing the trace mode and setting a memory address, the memory contents at that memory address are displayed in real time.

Since the entire address space can be specified as a memory address, not only flag information controlled by each program but also the contents of hardware registers can be referenced in real time.

It should be noted that the address setting method is not limited to the above embodiment, and it goes without saying that it can be applied within the scope of the invention.

As described above, arbitrarily focused memory contents can be displayed in real time using a simple method without using trace memory, making failure analysis easy.

Furthermore, each path of interrupt processing is designed to shorten the processing time, so it does not affect input/output operations.

〔Effect of the invention〕

The present invention provides a memory display trace method 2 that specifies a trace mode using a plurality of switches and then specifies an address, and reads and displays the contents of the specified memory for each interrupt that occurs at a predetermined time interval. ■The memory contents of interest are displayed in real time, making it easy to analyze the cause of failures.■All memory contents can be specified without using large trace memory.■Trace processing time is reduced. Since it is short, it has the great effect of not affecting the operation of the device.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one embodiment, and FIG. 2 is an operation flowchart. In the figure, 1 is a switch, 2 is a display, 3 is a timer, 4 is a microprocessor MPU, 5 is a memory, 6 is a timer interrupt processing unit, 7 is a flag, 8 is a current memory area to be traced, and 9 is a timer setting. 10 is a switch register, l1 is a display register, and 20 is an interrupt signal. Figure l Senta flowchart diagram Figure 2

Claims (1)

[Scope of Claims] A memory display tracing method for displaying memory contents in real time during device operation in an input/output device having an operation panel equipped with a plurality of switches (1) and a display device (2), the method comprising: A timer (
3) is activated by the interrupt signal (20), and if the trace mode is set, the setting state by the switch (1) is used as the memory address to read and display the memory contents, complete the process, and switch to the trace mode. If it is not set, the timer interrupt processing unit (1) determines whether the setting state of the switch (1) is a trace mode instruction or not, and if it is a trace mode instruction, sets the trace mode and terminates the process.
6) A memory display tracing method characterized in that the memory address set by the plurality of switches is referenced for each interrupt signal generated at predetermined time intervals, and the corresponding memory contents are read and displayed.