JPH03157065A - Synchronizing signal generator - Google Patents

Abstract

PURPOSE:To prevent malfunction due to noise of a frequency divider by discriminating whether or not a pulse width of an input synchronizing signal for a pre-hold period represents a regular width or noise, detecting the noise depending on a discrimination signal and initializing the frequency divider with a regular signal. CONSTITUTION:A period signal generator 10 inputs an initial synchronizing signal J and outputs a command signal K applying preholding to a skew and a period scheduling in the vicinity of skew jump production period and operates a discrimination device 9 by using an output L for a period estimating skew and a period after skew jump in the period of the output K. A recovered horizontal synchronizing signal A is inputted to the discrimination device 9, in which the signal is compared with a pulse width in the inside and when the pulse width is regular, it is regarded to be a normal signal and no output is caused, and when the pulse width is not normal, it is regarded as noise and an output I is generated and an output of a delay device 7 is reset. Thus, malfunction of initial operation due to noise is prevented and the phase of a frequency divider 2 is transferred momentarily to the phase of the recovered horizontal synchronizing signal A.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to the time discontinuity of playback synchronization signals, that is, skinny and The present invention relates to a synchronization signal generator suitable for skinny jump correction.

[Conventional technology]

Conventional video signal recording and reproducing devices include video tape recorders (hereinafter referred to as %VTR), video floppy recorders, and video disk recorders (hereinafter referred to as OvDR).
etc.

First, in V'l'H, the magnetic tape on which information is recorded is brought into contact with the surface of a rotating drum (rotation angle of 180 degrees or more) and run at a constant speed. C magnetic tape is mounted diagonally, and two Vc video heads are installed at 180 mm.
It is set up at a certain level.

The video head alternately contacts the surface of the magnetic tape at a constant speed by the rotation of a rotating drum. During recording, a recording current flows through the video head according to the information, and depending on the strength of the current, a magnetic tape is applied to the surface of the magnetic tape. ◎ During playback, the reverse operation is performed, and the video head detects the magnetic strength as a minute change in current, and the recorded information is reproduced.Moreover, in detail, one of the two video heads records the video signal. On the one hand, one field is recorded or reproduced, and on the other hand, the remaining one field is recorded or reproduced.

Therefore, in order to reproduce one frame of a video signal, it is necessary to connect the reproduction signals of two video heads.
The playback signal of the video head is switched based on the tack signal that detects the rotational position of the rotating drum.0 At this time, if the video head mounting position is several micrometers away from the normal position, the playback signal may change. A skinny of several μs occurs.

This skinny has the problem that the write timing generator of the video storage device that temporarily stores the playback video signal malfunctions, and the output playback image from the video signal storage device is distorted. When playing recorded tracks, several tracks are traversed.

At that time, a 0.5H skinny jump may occur. A 0.5H skinny jump correction circuit is used to correct this, but the flywheel oscillation 1iH'V
2H cross delay line or 1/2HCOD (1/2Hz
! Since it is made up of thickets, it is expensive and complicated.

In a video floppy KC, identical circular recording tracks are provided on a magnetic sheet, the magnetic sheet is rotated at a constant speed, and one video head records one field of a video signal on the same circular recording track. 〇 During the playback, 0.5H of squeege young may occur at the end of 1 field.
As a correction for this, the above-mentioned 0.5H difference in VTR is used.
A jump correction circuit is used.

Next, in %0VDfl, groove-like tracks for recording information are formed in advance on an optical disk in a concentric or spiffle shape, and the optical disk with a photosensitive material (recording member) deposited on the groove-like tracks is rotated. From this perspective, optical Changes in reflectance, etc. can be recorded on the groove-like tracks of the disk, and the recorded information can be reproduced by detecting changes in the optical characteristics.
The mark signal from the one-rotation position indicating mark provided on the inner circumference of the optical disk is synchronized with the vertical synchronization signal of the video signal.
Since it is configured to be installed at a certain angle from the optical pickup, there is no possibility of hole play (eccentricity) in the optical disc.
Therefore, the one-rotation position indication mark apparently varies with respect to the optical pickup that records the video signal. Therefore, when the currently recorded video signal and the previously recorded video signal are played back consecutively, , when transitioning from the previous video signal to the current O video signal, a large time discontinuity (skinny jump) occurs.@ This skinny jump amount may reach up to 40 μ8, and the above-mentioned VTR etc. .The 5H skinny jump correction circuit cannot deal with the large fluctuations in the skinny jump amount.Furthermore, at 0VDH, a time pace corrector (hereinafter referred to as TeBC) is used to correct the amount of time axis fluctuation caused by disk eccentricity and distortion. ) is used for this skinny jump? There is a problem that the BC cannot fully respond and the reproduced image is distorted.0 Below, a video signal storage device that temporarily stores video signals will be described.

T! FIG. 46 is a block diagram showing an example of a conventional video signal storage device, in which the video signal output from the video signal recording and reproducing device described above is input to the input terminal 50.The input video signal is A/D converted. 51 and the reproduced horizontal synchronization signal detection section 32.

The playback horizontal synchronization signal detection section 52 outputs a playback horizontal synchronization signal, and the output signal is input to the 7A locked loop (hereinafter referred to as PLI) 33. In the PLL 3B, the playback horizontal synchronization signal is synchronized with the playback horizontal synchronization signal. A signal q having a frequency several times higher than that of the synchronization signal and a memory write start signal k having a period of the horizontal synchronization signal are output and input to the memory control unit 54 .

Furthermore, a one-mesh write clock signal q is input to the A/D converter 51.

The A/D converter 51 converts the analog amount of the video signal into a digital amount using the memory write clock signal QFC, and inputs the digital amount to the memory (storage element) 55.

The memory control unit 34 uses the output of the PLL 55 to
On the other hand, the read clock generator 56 is a reference signal generator using a high-precision, highly stable signal oscillator such as a crystal oscillator 57. The memory control unit 54 and the D/A converter input a reference signal from the memory controller 58 and generate a read clock signal approximately equivalent to the write frequency and a read start signal approximately equivalent to the frequency of the write start signal. In the memory controller 34, the read clock generator 5
6, the information written in the memory 55 is read out in order, and the digital signal is converted to an analog signal through the D/A converter 59, thereby reproducing the reproduced video signal.

In this case, the video can be temporarily stored and reproduced at a required time, and gradual temporal fluctuations in the video signal can be corrected.

However, in the skinny and skew jumps described above, since the amount of time axis variation is step-like, the PL
L55 cannot respond instantly; on the other hand, PLL5! It takes several frames for S to reach a stable state. Therefore, there is a problem that the reproduced image is distorted during that period.In order to solve this problem, conventional PL
In L, PI; while the input signal Kc1 of L is not turned on,
To stop the operation of the phase comparator, generate a free-running frequency output from the voltage controlled oscillator, and lock it,
The frequency divider in the PLL is reset and canceled by the input signal, and the phase comparator is started to operate.
I and L are made to respond instantaneously to input signals.As the PLf of this provision, for example, JP-A-58-1506
Examples include the one described in Publication No. 29. [Problem to be solved by the invention] In the above-mentioned conventional technology, no consideration is given to whether the signal that locks the PLL is a regular one, and the problem is caused by noise. If there is a possibility that the frequency divider is set to the initial value (To)), the PLL will malfunction at that point, and the reproduced image will be distorted over several frames, making continuous reproduction impossible.

An object of the present invention is to provide a synchronization signal generator that prevents malfunctions due to noise in a reproduced synchronization signal. Means for Solving a Problem] The above object is achieved by adopting the following configuration.

It is activated for a certain period of time based on the edge information of the input signal, and receives the input signal within this activation time.

A self-gating device whose activation time is controlled by an external signal, a phase comparator which inputs the output of this self-gating device to the input signal, and a pulse width of the input signal which is determined and inputted to the pre-hold device. A discriminator that outputs a discrimination output within a period of an external signal or a part of this signal, and inputs this discrimination output as one of the external signals of the self-gating device, and uses this discrimination output to delay the input signal. an initial value generator that generates an initial value signal based on the output from this delay device, a frequency divider that is set to an initial value by the output from this initial value generator, and this frequency divider. By inputting the output from the phase comparator to the phase comparator,
Prevent malfunction of the initial value operation of the frequency divider due to noise.

Further, a first and second decoder decodes the output of the frequency divider, and a reading device that reads the output of the self-gating device using the output of the first decoder and resets the read content using the output of the second decoder. In addition, by inputting the output of the initial value generator and using it as an external signal for the self-gating device, malfunctions of the self-gating device due to noise can be prevented. , by inhibiting external signals to the discriminator and pre-hold device, the initial value operation of the frequency divider is minimized and P
The normal operating range of I, I can be expanded and the response time can be accelerated.0 [Operation] A self-gating device starts for a certain period of time from the edge of the input signal, and a delay device delays the edge of the input signal for a certain period of time. do.

The discriminator also compares the pulse width of the input signal with the set value,
For regular input signals.

Since it does not produce an output, the delay device produces an output.

This output passes through the initial value generator and sets the frequency divider to its initial value. At this time, the phase of the frequency divider instantly shifts to the phase of the normal input signal. Also, the output of the self-gating circuit operates normally. Then, when the input signal is noise, the pulse width of the input signal is narrow and is less than the set value, so the output of the discriminator determines the self-gating circuit. Stop starting.

Furthermore, since the operation of the delay device is stopped and its output is not generated, the frequency divider is not set to its initial value, so that malfunction of the frequency divider due to noise can be prevented.

On the other hand, the self-gating device has stopped activating and is in a state where it accepts input of a regular input signal.

Therefore, in the case of noise, the self-gate operation is stopped and a normal input signal is waited for. Immediately after the pre-hold is released, the input signal can be detected instantly, and P! , L operation timing can be advanced.Next, after the pre-hold is released, the initial value operation is stopped and the self-gating device continues to operate.

Furthermore, PLr operates to match the phase of the input signal.

Therefore, the output of the first decoder is generated with a delay of several hundred naeo from the edge of the input signal, input to the reader, and the output of the self-gating device is read.・The input signal is generated at the regular timing. In this case, since the self-gating device has already started, the output at this time is read and output, and the self-gating device continues to operate.

The second decoder generates the signal several hundred naec before the next regular input signal, resets the reader, and shifts to the operation of reading the output of the self-gating device by the next input signal.

When the cell 7 gater is not activated at the time of output from the first decoder, this occurs when the input signal is lost due to dropout, and ε means that the subsequent self-gaters are activated due to noise. .

Therefore, the reader reads that the self-gating device is not activated, stops the operation of the self-gating device, and cancels the stoppage of the operation with the output of the second decoder.

Therefore, even if noise is input during the period from stopping the operation to canceling, the self-gating device will not operate, so malfunctions due to noise can be prevented. ◎Immediately, the operating period due to noise of the self-gating device is extremely narrowed. to reduce malfunctions caused by noise.

Furthermore, a flip-flop is set by the first pulse of the output of the initial value generator, and this set signal inhibits external signals to the pre-hold device, the discriminator and the initial value generator;
Release prefix hold.

As a result, it is possible to shift to steady operation at an earlier timing than before, to quickly follow the phase of the input signal, and to transmit information more accurately.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the synchronizing signal generator according to the present invention, and is a block diagram corresponding to the PLL 53 in FIG. 6. 1 is a voltage that controls the oscillation frequency by the DC level The controlled oscillator (VCO) 2 is composed of several stages of clock pulses, counts the input clock using a BCD code, and when it reaches a set value, generates an output signal, and either sets itself to the initial value or uses an external signal to generate an output signal. 3 is a trapezoidal phase comparator that compares the phases of two inputs and outputs a DC level according to the comparison amount; 4 is a trapezoidal phase comparator that becomes the initial value; 5FiPL is a pre-hold device that holds the input DC level immediately before input, and outputs the input signal as is during periods when there is no external signal.
A phase compensator compensates the phase of the loop in order to maintain the stability of L, and 6 is a self-gate device that is activated for a certain period of time depending on the edge of the input signal, accepts the input signal outside of that period, and then stops activation by an external signal. , 7 delays the edge information of the input signal for a certain period of time, and further uses an external signal to
8 is an initial value generator that outputs a short pulse from the edge information of the input signal and whose output is controlled by an external signal; 9 determines the pulse width of the input signal and outputs it according to the external signal; is controlled, 10 is a period signal generator that inputs a composite synchronization signal and generates a pulse width of a certain period, 11.12 decodes the kakunta output of frequency divider 2, and outputs it when it reaches a set value. 1st. The second decoder, 15, is a reader that reads an input signal and outputs it accordingly, and 14 and 15 are two-manual OR devices.

FIG. 2 is a time chart of signals A to A corresponding to A to A shown in FIG. 1. The operation will be explained using FIGS. 1 and 2.

The reproduced horizontal synchronizing signal a is sent to the cell 7 gate device 6. The self-gating device 6, which is input to the delay device 7 and the discriminator 9, starts from the rising edge of the reproduced horizontal synchronizing signal, stops several hundred n5ec before the generation of the next reproduced horizontal synchronizing signal, and inputs the input signal during that time. The output of the self-gate device 6 is input to one side of the phase comparator 3. The output of the frequency divider 2 is input to the other input of the phase comparator 5. , the rise of two input signals> outputs a DC level signal according to the phase difference of the edges, and outputs a DC level signal according to the edge phase difference, and
Manpower.

The output of the pre-hold device 4 is controlled depending on the presence or absence of an external signal; if there is an external signal, it is pre-held; if not, it passes the phase comparator SO ratio output.

The output of the pre-hold device 4 is phase compensated by the phase compensator 5 and input to the VCOl. The VCOl controls the output oscillation frequency according to the input DC level, and the output O is the output voltage of the frequency divider 2. The frequency divider 2 serves as a clock input and generates an output signal when the specified frequency division number is reached.
Input to phase comparator 5.

The above loop is the operation of a PLL that is normally performed. The period signal generator 10 inputs the initial synchronization signal and outputs an instruction signal to pre-hold a period scheduled around the occurrence of skim and jump jumps. And within the period of further output! The discriminator 9 is operated according to the output of the scheduled period after the skim jump and the skim jump.

Is the reproduced horizontal synchronization signal a a discriminator? IC input, discriminator 9
Compared with the internal pulse width, if it is the specified pulse width,
It is regarded as a regular signal and no output is output, and if the pulse width is outside the specified pulse width, it is regarded as noise, an output failure is generated, and the output of the delay device 7 is turned off.

Like the discriminator 9, the delay unit 7 receives the reproduced horizontal synchronizing signal A, delays the input edge information for a certain period of time, and generates an output signal.

Here, the timing of the output of the discriminator 9 and the timing of the output of the delay device 7 are 1 because the output occurs later than the output timing of the delay device 7.
The output of the discriminator 9 can be used to control malfunctions of the output.The output is input to the initial value generator 8, a short pulse is generated from the edge of this input, and this output is used to set the frequency divider 2 to the initial value. Make it.

This prevents malfunctions in the initial value operation due to % noise, and allows the phase of the frequency divider 20 to be instantaneously shifted to the phase of the reproduced horizontal synchronizing signal A.

The output of the discriminator 9 passes through the logical adder 15 to stop the activation of the 7-lua gate device 6, stop the operation due to noise, and accept the input of the normal signal.The output of the self-gate device 6 passes through the reader 11: Also, the reading device 15 reads the input level by the first output signal of the frequency divider 2, generates an output signal, and controls the output of the self-gating device 6 through the OR device 15.

Furthermore, the output of the second decoder 12 and the period signal generator 1
The output of 0 is input to the OR gate 14, and the output of the reader 15 is controlled by the output of the OR gate 14. By this operation, if the reproduced horizontal synchronization signal A is within a predetermined range, , the signal is regarded as a normal signal, and any other signal is regarded as noise, and the output of the gate circuit 6 is not output, thereby preventing malfunction of the PLL.

The above operation will be explained in more detail using the time chart of FIG.

During the logically high level period of the output of the period signal generator 10, there is a pre-hold period (To), during which a skim-jump occurs.

When a jump occurs in the reproduced horizontal synchronizing signal A, the output of the period signal generator 10 is also logically at a high level, so the pulse St of the signal A is determined by the discriminator 9 and the pulse width is determined to be the normal pulse width. Therefore, the output of the delay device 70 is generated after a certain delay from the signal A, which causes the output of the initial value generator 8 to be generated, and the frequency divider 2 is set to the initial value. The phase of the frequency divider 20 is shifted to the phase of the output A after the jump.

At this time, since the output of the 1-phase comparator 25 is pre-held, the input signal of Vlol does not fluctuate, and furthermore, the reader 1S does not operate.

If there is noise in the reproduced horizontal synchronizing signal A while the output of the period signal generator 10 is logically high, the self-gating device 6 is activated at the edge of the noise, but the discriminator 9 detects the pulse width of the noise. A short pulse with a logically high level is generated, and this pulse is input to the delay device 7 and the self-gating device 6 to stop the delay operation due to noise and the activation of the self-gating device 6.

As a result, the output of the delay device 70 does not occur, so malfunction of the initial value of the frequency divider 2 can be prevented.
Set to wait for input signal.

Next, when the previous one hold period ends, the outputs of the period signal generator 10 logically become low level υ, and the outputs of the phase comparator 5 are inputted to the VCOl through the phase compensator 5.

At the end of the pre-hold period, the output A is a case in which the normal signal is lost due to dropout, and then there is noise, and the logical low level of the output of the self-gating circuit 6 is set to the output of the first decoder. The upper part is read into the reader 15 by the edge.

Since the output of the reading device 15 is not normal, it outputs a logically high level, and during the period when this output is logically 1, the self-gating device 6 is reset so that it does not start up due to noise. The D output outputs a logic high level at a point before the next regular signal A is input, and the logic level on the output of the reader 15 becomes low.

This is K>, the self-gating device 6 receives the input signal A.

1st. The output signal of the second decoder, the phase of
Since the phase matches the phase of signal A due to the previous initial value operation, the normal generation timing of signal A can be set in advance.

Therefore, during steady operation, the operation of the self-gating device 6 can be limited, which is considered a drawback of the self-gating device.
It is possible to prevent startup malfunctions due to noise before startup. Also, is the self-gate device 6 a 1 discriminator during the pre-start period? Ilc detects noise and controls startup based on its output, so if there is noise before the pre-hold is released, the startup is stopped in a short time, so after the pre-hold is released, the normal input signal A is immediately applied. ), the response of the PLL can be accelerated accordingly◎ Fig. 5 is a block diagram showing another embodiment according to the present invention.
The same symbols as in FIG. 1 have the same functions, and 2
1.22 is a logical multiplier, 25 is a logical negator, and 24 is a 70-tube tree.

FIG. 4 is a time chart of the signals shown in FIG.

Next, the operation will be explained.

During the pre-hold period, the output of the period signal generator 10 is at a logical high level and is inverted through the logic negator 25 and input to one of the ANDs 22.

The output of the first decoder 11 is inputted to the other input of the AND gate 22, and the output resets the 7 lip-flop 24. The tree 70 and the knob 24 are set by the output of the second decoder and output the output nu. do.

From this point, during the pre-hold period, the operation is as explained in FIG. 1.

Next, the operation after the pre-hold is released will be explained.

The flip 70 knob 24O output N outputs the logic high period of the logic level and the logic high level of the input signal A to the AND gate 2.
1, generates an output A', blocks noise in the input signal A, and prevents malfunctions of the Seltz gate circuit due to noise.Moreover, the tritub flop 24 is initialized to the phase of the input signal A. There is. Therefore, the generation timing of the input signal A can be set in advance, and the normal input signal A can be obtained by ANDing it with the set output N.In addition, the reader 13 in FIG. 1 and the flip-flop 24 in FIG. The output is cleared by the pre-hold signal from the signal generator 1o for one period, but even when the pre-hold signal is not used, the output from the second decoder 12 of the frequency divider 2 is always input. Therefore, the operation of the self-gating device 6 due to noise can be reduced.

FIG. 5 is a block diagram of still another embodiment of the present invention, in which the same symbols as those described above have the same functions, 25 is a tree flop, and 26 and 27 are logical multipliers.

Te)? The flip-flop 25 is set by the logic high level of the output during the pre-hold period and the initial output of the initial value generator 8, and its output varies from the logic high level to the low level. 26 and 27.

The output of the pre-hold period is input to the other input of the AND gate 26, and this output is inhibited by the output cover and the pre-hold is released by the output cap.
7, the operation of the discriminator 9 and the initial value generator 8 is prohibited. When the output of the period signal generator 10Q becomes a logical low level, the operation of the clip clip 25 is prohibited. It is cleared and waits for the input of the initial value operation to be performed in the next cycle. Therefore, the initial value operation of frequency divider 2 is not performed many times, but only once, and normal PLL is performed instantly, so it is faster. It is possible to get close to the true phase.

As described above, according to the present embodiment, the pulse width of the reproduced horizontal synchronizing signal A after the occurrence of a jump or jump is determined by the discriminator 91, and the output of this discrimination is used to determine the pulse width of the reproduced horizontal synchronizing signal
and control the output of the cell 7 gate device 6 to prevent initial value malfunction due to noise in the divider/frequency divider 2.
By stopping the activation due to noise, and instantaneously starting it with a regular signal A when the pre-hold is released, p, PL
Start moving L.

In addition, the operation timing of the self-gate device 6 is adjusted by the frequency divider 2.
No. 1. It is limited by the second decoder It, 12, the reader 1s, and the 7-lip 7c2 tube 24 to prevent malfunctions due to PLL noise.

j! By detecting the first pulse of the initial value of frequency divider 2 at [V4O Effect] As explained above, according to the present invention, the skinny and jump generation timing is set within the pre-hold period, and the pulse of the input synchronization signal within the pre-hold period is set.
is normal or noise, detects noise based on this discrimination signal, and sets the frequency divider to the initial value using the normal signal, so malfunctions due to frequency divider O/noise can be prevented. The discrimination signal prevents the self-gating device from malfunctioning due to noise, and the operation of the self-gating device immediately after pre-hold release can be started with a regular input synchronization signal.
, can be activated without malfunction. ・Furthermore, the output of the first decoder of the 1 frequency divider is used to check the self-gating device and the input synchronization signal, and if it is not a regular synchronization signal, the noise is removed until it is close to the synchronization of the input synchronization signal. This makes it possible to prevent malfunctions caused by noise.0 By the above, it is possible to prevent malfunctions caused by noise and to prevent disturbances in the reproduced video information. Can provide functional synchronization signal generator

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the synchronization signal generator according to the present invention, FIG. 2 is a time chart of signals A to G corresponding to 7 to G shown in FIG. 4 is a time chart of the signals shown in FIG. 3, FIG. 5 is a block diagram of still another embodiment of the present invention, and FIG. 6 is a conventional video signal storage device. It is a block diagram showing an example of 2... Frequency divider, 6... Self gate device, 7... Delay device, 8... Initial value generator, 9... Discriminator, 11...
...First decoder, 12...Second decoder, 13
...Reader, 21, 26.27... Logical product,
24.25...Clip flop. 2nd Power Buo 11-------1---------------------1--Se No. 5 Fig.

Claims (1)

[Claims] 1. A voltage controlled oscillator, a frequency divider that divides the output, a phase comparator that compares the phase of the output of the frequency divider and an input signal, and an output of the phase comparator. a pre-hold device that pre-holds the voltage controlled oscillator using an external signal, and a synchronization signal generator that controls the oscillation frequency of the voltage controlled oscillator using the output of the pre-hold device. Input signals outside the startup time are not accepted, and the output from the self-gating device that controls the startup time using an external signal is input to the phase comparator, edge information of the input signal is delayed, and the output is controlled by the external signal. an initial value generator that generates an initial value signal from the output of the external delay device; and inputting the output of the initial value generator to the initial value terminal of the frequency divider to determine the pulse width of the input signal. a discriminator whose discrimination signal is controlled by an external signal of the pre-hold device or a part of the signal, and an output of the discriminator as an external signal for the self-gating device and the delay device; A synchronization signal generator characterized in that it is configured to prevent malfunctions due to input signal noise. 2. In claim 1, a first decoder that decodes the output of the frequency divider and outputs the output when it reaches a set value; and a second decoder that outputs the output after the output of the first decoder;
A reader that reads the output of the self-gating device with the output of the first decoder and clears the read content with the output of the second decoder, and a reader that reads the output of the self-gating device with the output of the second decoder, and a The present invention is characterized in that it is configured to include an OR device for summing, and to control the output of the self-gating device by using the output of the ORing device as an external signal of the self-gating device to prevent malfunctions due to noise in the input signal. Synchronous signal generator. 3. In claim 1, a flip-flop whose output is set by the output of the first decoder and reset by the output of the second decoder, and a logic which ANDs the output of the flip-flop and the input signal. 1. A synchronizing signal generating device comprising: a multiplier; and an output from the AND multiplier is connected to an input of the self-gating device to prevent malfunctions due to noise in the input signal. 4. In claim 1, 2 or 3, the output of a flip-flop inputs the output of the initial value generator to set the output and resets the output by an external signal, and the pre-hold device, the initial value generator and A discriminator is provided to inhibit external signals from the discriminator, the initial value operation time of the frequency divider is shortened, and the steady operating region of the phase-locked loop is widened to speed up the response time. Characteristic synchronization signal generator.