JPH03156793A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To select a semiconductor memory having a marginal preamplifier by increasing the precharge capability of a precharge circuit in the test mode more than that in the normal mode. CONSTITUTION:Transistors (TRs) 1 and 2 are turned on to precharge I/O and the inverse of I/O lines to a level Vco-Vth (power supply voltage - threshold voltage of the TR 1). Then the input signal Y goes to an H level from L, the TR 2 is turned on, the level of a bit line and inverse of bit line amplified by a sense amplifier is sent respectively to the I/O and inverse of I/O lines, then a level difference is caused between the I/O and inverse of I/O lines. Then a level difference at a time T when the preamplifier is started is a level DELTAVT, which is smaller than a level DELTAVn in the normal mode because the capability of the preamplifier is high. Since the level difference between the I/O and inverse of I/O lines when the preamplifier is in operation in the test mode is smaller than that in the normal mode, a tight test is conducted to the preampli fier. Thus, a semiconductor memory having a marginal preamplifier is selected out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, particularly during testing thereof (hereinafter referred to as test mode).

[Conventional technology]

Fig. 4 is a circuit diagram of a conventional F0 line precharge circuit of a semiconductor memory device, and Fig. 6 shows each input signal 'h' in Fig. 4.
It is a voltage waveform diagram of Al 4y#, I/O line, and Ilo line.

Next, we will explain the operation.At the time of 0 reading and operation,
First, input signal A is %7. ow I (hereinafter referred to as below) becomes 4H1gh” (hereinafter referred to as H), transistor (1) is turned on, and the I/O line and I/O line are changed to 4H1gh” (hereinafter referred to as H).
Precharge to Vth (power supply voltage - threshold voltage of transistor (1)). This precharge ability does not change between normal operation (hereinafter referred to as normal mode) and test mode.0 After that, the input signal! changes from L to H, and the potentials of the b-line and bit line amplified by the sense amplifier become I/O. 1111 and the I/O line, and the I
A potential difference occurs between the /O line and the Ilo line. Then, the potential difference at time T when the preamplifier starts to operate is ΔV, and this ΔV
is the same in normal mode and test mode.

[Problem to be solved by the invention]

Since the conventional semiconductor memory device is configured as described above, in the normal mode and test mode, the Ilo line and I
Another problem is that semiconductor memory devices with marginal preamplifiers cannot be selected in test mode because no difference is seen in the potential difference ΔV of the lo line.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to select semiconductor memory devices having a preamplifier that is insignificant during a test mode.

[Means to solve the problem]

The semiconductor memory device according to the present invention has a high ability to precharge the I10 line and the I/O line during the test mode.

[Effect]

An I/O line of a semiconductor memory device according to the present invention.

In the I/O line precharge circuit, the preamplifier is subjected to a severe test in the test mode, and a semiconductor memory device having a marginal preamplifier can be selected. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an I/O of a semiconductor memory device which is an embodiment of the present invention.
FIG. 3 is a circuit diagram of a line precharge circuit.

In the figure, (1) is a transistor that precharges the I/O and 5ItI10 lines in normal mode and test mode, and (2) is an I10 gate that transmits the potential of the bit Is and tels lines to the I/O line and I10 line, respectively. Transistor, (3) is I10 line *x only in test mode
This is a transistor that precharges 101a.

Figure 2 shows the input signal percentage in normal mode in Figure 1.
A evening%2B$4y# and I/O line, I/O#! FIG.

Figure 3 shows the input signal percentage in test mode in Figure 1)
, I%Tzl%yN and I/O failure, which is a voltage waveform diagram of the I10 line.

Next, the operation will be explained.

First, the read operation in normal mode will be explained.

The input signal becomes H from L and transistor (1) becomes '0'.
Nt(,,x7o line and I/OIIIA as Tco -v
Precharge to th. After that, the input signal r changes from L to R, transistor (2) changes to %□N, and the bit line amplified by the sense amplifier and 1) it! The potential of i& is transmitted to the I10 line and the xyo line, respectively, and a potential difference is generated between the I/O line and the I/O line. Then, when the preamplifier starts moving - t - the potential difference at time T becomes Δvn.

Next, the read operation in the test mode will be explained. In the test mode, the input signal TN also changes from L to H at the same time as the input signal A (l in the input signal at this time is generated by voltage application to the external test mode bin or timing control). (t) t (
2) is 0NLI/111 and I/O@”0O-7th
Precharge to. The precharge capability at this time is higher than in the normal mode because the transistor (3) is turned on. After that, the input signal τ is changed from B to E.
Then, the transistor (2) turns on, and the potentials of bit fl and bit+li amplified by the sense amplifier are transmitted to the I/O #I and I/O lines, respectively, and the I/O line and xy
A potential difference occurs in the o line. Then, the potential difference at time T when the preamplifier starts operating is ΔVτ. ΔV! is smaller than Δvn in the normal mode because the preamplifier has a high ability.

As mentioned above, when the preamplifier operates, the X70 line xy
Since the potential difference between the o lines is smaller in the synast mode than in the normal mode, severe tests can be performed on the preamplifier.

〔Effect of the invention〕

As described above, according to the present invention, the I/O
By increasing the precharge capability of the line in the 7-maμ mode in the comparison test mode, the preamplifier can be subjected to severe testing, and semiconductor memory devices with marginal preamplifiers can be selected.

[Brief explanation of the drawing]

FIG. 1 shows I of a semiconductor memory device according to an embodiment of the present invention.
The circuit diagram of the 10-wire precharge circuit, Figure 2 shows the input signal ゞA'ゞTll1' command of Figure 1! evening and I/O line, I/
The waveform diagram of the O line in normal mode, Figure 3 shows the input signal %AI%11 of Figure 1, the input signal Y', the I/O line, and the I/O line.
4 is a circuit diagram of a conventional I/O line precharge circuit of a semiconductor memory device, and FIG. 5 is a waveform diagram of the input signal SA#1! of FIG. 4 in the line test mode.夛 and I/O line,
It is a waveform diagram of the F-o line. In the figure, (1) to (3) indicate transistors. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A semiconductor memory device characterized in that during testing of the semiconductor memory device, the precharge capability of an I/O line and a line is made higher than during normal operation.