JPH03154980A - Chrominance signal covnerting circuit - Google Patents

Abstract

PURPOSE:To reduce the overall scale of a color signal converting circuit by using a 1st means and a cumulative adder to apply the serial conversion to the input signals. CONSTITUTION:A ROM 5 is provided as a 1st means together with a cumulative adder 6, and a ROM 7 serving as a 2nd means. The ROM 5 multiplies the data (a) by a conversion coefficient of each component with use of the control signals C6 - C9 and outputs the result of this multiplication as the data (b). The adder 6 receives the data (b) and adds this data cumulatively in the order of R, G and B and outputs the data (c). Then the ROM 7 receives the data (c) limits the values where the data (c) exceeds the fixed upper and lower limit levels and outputs the values of signals Y, Cb and Cr. In such the constitution, the overall scale of a color signal converting circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color signal conversion circuit for an image processing device, and particularly to a color signal conversion circuit before image compression or after image expansion.

[Conventional technology]

Conventionally, this type of color signal conversion circuit has been constructed using human-powered three primary colors (R
, G, B) signal is multiplied by a fixed conversion coefficient and added to calculate luminance (Y) and color difference (C, , C,
) Luminance (Y) converted into a signal and output, or manually generated
・Color difference (C,,C.

) has been proposed as a device that multiplies each component of a signal by a fixed conversion coefficient and adds the signals to convert them into three primary color (R, G, B) signals and output the signals.

In the above-described apparatus, when converting three primary color (R, G, B) signals into luminance (Y) and color difference (C, Cr) signals, each component (R, G, Cr) of the three primary color signals is converted.

For B), the following equation (1) is used.

Here, Y is a luminance signal, C,, C, is a color difference signal,
Further, R, G, and B are each component of the input three primary color signals, and further, Ry, GY, BY, and Rcb.

G cb+ "Lb+ Rr=, G'rb+ Br
b is a conversion coefficient corresponding to each component.

In addition, in the above-mentioned device, luminance (Y), color difference (
When converting a Cb, C,'') signal into a three primary color (R, G, B) signal, the following equation (2) is used for the luminance (Y) and color difference (cbCr) signals.

...... (2) Here, Y, l, Yc, YB, Cci,
CcG, CcB.

Crl+CrG and CrB are conversion coefficients corresponding to each component.

As can be understood from equations (1) and (2), this device multiplies equations (1) or (2) by the human input signal and the conversion coefficient of each component, and then calculates the result of the calculation. This is realized by calculating with three storage means and then adding the outputs from these means with a two-stage adder. and,
This device converts the three primary color signals into luminance and color difference signals, or converts the brightness and color difference signals into three primary color signals and outputs them.

[Problem to be solved by the invention]

According to the conventional color signal conversion circuit described above, in order to convert the three primary color signals to luminance/chrominance signals or from the luminance/chrominance signals to the three primary color signals, three means for performing multiplication and storing the results are required. Moreover, two stages of adders are required, which is very disadvantageous in reducing the scale of the entire circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a color signal conversion circuit that eliminates the disadvantages of the prior art described above and has a reduced circuit scale.

[Indispensable means to solve problems]

The color signal conversion circuit of the present invention multiplies each component of the input three primary color signals by a fixed conversion coefficient and adds them to convert them into luminance/color difference signals and outputs them, or each component of the luminance/color difference signals is manually input. The color signal conversion circuit that multiplies and adds a certain conversion coefficient to convert into three primary color signals and outputs the signal has a conversion coefficient for each component of the human input signal, and the input signal of each component has a conversion coefficient for each component. a first means for multiplying by a conversion coefficient and temporarily holding the result of this multiplication; a cumulative addition means for cumulatively adding the data from the first means a predetermined number of times; and an output result from the cumulative addition means. The present invention is characterized by comprising second means for applying a limiter and outputting a conversion completion signal when the value exceeds a predetermined upper limit value or lower limit value.

The present invention consists of a first means, an accumulative addition means thereof, and a second means, and the conversion of each signal is executed serially, so that the overall circuit scale can be reduced.

〔Example〕

Next, one embodiment of the present invention will be described.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, the color signal conversion circuit includes three primary colors (R, G,
B) Bidirectional signal path registers 1 to 4, ROM 5 as a first means, cumulative adder 6, ROM 7 as a second means, control section 8, luminance (Y), color difference (C)
, , Cl bidirectional path registers 9 to 11, and a clock generator 12. Bidirectional path registers 1-4 and bidirectional path registers 9-11 are connected by a path line 13 capable of transmitting 8-bit signals. R.O.M.
The input of 5 is connected to the pass line 13, and data from the pass line 13 is input to the ROM 5. The output of 5012 bits of ROM is sent to cumulative adder 6.
is man-powered. The 10-bit output of the cumulative adder 6 is stored in the ROM 7. The 8-bit output from the ROM 7 is output to the pass line 13. Further, the control signal output C1 from the control section 8 is connected to the input terminals C1 of the bidirectional path registers 1 to 4, the ROM 5, and the bidirectional path registers 9 to 11.

Control signal outputs C2, C3, C4, Cs of the control unit 8 are input terminals C2, C3 of the bidirectional path registers 1.2, 3.4.
, Ca, and Cs, respectively. Control unit 8
Control signal outputs 06 to C9 are connected to the ROM5. The control output CO of the control section 80 is connected to the input terminal CIO of the cumulative adder 6. Control signal output C of control unit 8
+ + , CI 2 , CI 3 are respective input terminals C + + C of bidirectional path registers 9, 10.11.
l 2 and C+ 3, respectively. Outputs s, , s2 . of the clock generator 12 . Sj is
Input terminals of each component S+, S2, S3
It is connected to the.

Next, the operation of the embodiment configured as described above will be explained.

FIGS. 2 and 3 are timing charts shown to explain the operation of the embodiment of the present invention, in which the horizontal axis shows time and the vertical axis shows the signal state of each part, respectively. Further, FIG. 2 shows the operation of converting the three primary color signals into luminance/color difference signals, and FIG. 3 shows the operation of converting the luminance/color difference signals into the three primary color signals.

First, the three primary color (RGB) signals are converted into luminance/color difference (YCb,
Cr) Regarding the operation of converting to a signal, Figures 1 and 2
This will be explained with reference to the figures.

The 8-bit RGB signal is input to one of bidirectional pass registers 1-4. This input RGB signal is held in the bidirectional path register 1, for example, and is shown in FIG.
As shown in a), pass line 1 in the order of RlG and H.
3 is output. This signal is input to ROM5.

In the ROM5, data (a
) by the conversion coefficient of each component, and output the multiplication result as data (b). The cumulative adder 6 to which the data (b) is input, as shown in data (C) in FIG.
Data (b) is cumulatively added in the order of RSG and B, and data (C) is output. ROM7 into which data (C) is input
applies a limiter to the value in which the data (C) exceeds the upper and lower limits of -, and outputs the values of y, Cb, c, and signals. This output is output to the path line 13 as data (d) and held in the bidirectional path registers 9 to 11 at the timing of the control signal from the control section 8. The signals are then output from the bidirectional path registers 9 to 11 to the outside.

(Conversion operation to Y, cb, Cr-R, G, B) Next,
Luminance/color difference (Y, cb, C,”) signals are converted into three primary colors (
Figures 1 and 3 regarding the operation of converting to RGB) signals.
This will be explained with reference to the figures.

The Y, C, ,C, signals are held in bidirectional path registers 9-11. From these bidirectional path registers 9 to 11, y,
Cb, c, and signals are the data in Figure 3 (a), respectively.
As shown in the figure, the signals are output in the order of Y, C, and Cr. The ROM 5 to which the data (a) has been input multiplies the data (a) by the conversion coefficient of each component using the control signals C6 to C9 shown in FIG. 3, and outputs the multiplication result as data (b). Data (b) is stored in the cumulative adder 6 as
As shown in data (C), data (b) is cumulatively added in the order of y, Cb, cr, and data (C) is output. This data (C) is subjected to a limiter in ROM7 for values exceeding a certain upper limit value and lower limit value, and RGB
It is output as data (d) as a signal. The RGB signals are selected and held in, for example, the bidirectional pass register 1 via the pass line 13 by control signals 02 to C5 from the control unit 8. As a result, the signals are output from the bidirectional path register 1 as RGB signals, for example.

In this way, this embodiment operates as described above to convert RGB signals to y, Cb, c signals, or y, Cb signals.
, c, signals are converted into RGB signals.

As explained above, in this embodiment, it is possible to serially convert signals manually generated using the ROM 5 and the cumulative adder 6. Therefore, the ROM 5 can be reduced to 1/3 of the conventional one, and the circuit size can be reduced to 1/3. can be made significantly smaller.

〔Effect of the invention〕

As explained above, the present invention enables serial conversion processing of input signals by using the first means and an accumulative adder, and therefore has the advantage that the scale of the entire circuit can be significantly reduced. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are timing charts for explaining the operation of the embodiment. 1 to 4... Bidirectional path register, 5...
・ROM (first means), 6...cumulative adder, 7...ROM (second means), 8...
・Control unit, 9 to 11... Bidirectional path register,
I2...Clock generation section.

Claims (1)

[Claims] Each component of the input three primary color signals is multiplied by a fixed conversion coefficient and added to convert it into a luminance/chrominance signal and output, or each component of the input luminance/chrominance signal is multiplied by a fixed conversion coefficient and added. The color signal conversion circuit that converts the signal into three primary color signals and outputs the signal has a conversion coefficient for each component of the input signal, and multiplies the input signal of each component by the conversion coefficient of each component, a first means for temporarily holding the result of the multiplication; a cumulative addition means for cumulatively adding the data from the first means a predetermined number of times;
and second means for applying a limiter and outputting a conversion completion signal when the output result from the cumulative addition means exceeds a predetermined upper limit value or lower limit value.