JPH03154116A - Power-on reset circuit - Google Patents

Abstract

PURPOSE:To surely reset other circuit even if a time constant of the rise of a power source is varied by detecting a power supply voltage by which an element comes to completely a stable state, after a power source is turned on, and outputting a reset signal. CONSTITUTION:By a resistance split voltage by MOS transistors 1, 2 and a resistor 5 by the voltage of a voltage source 8, and in the same way, by a resistance split voltage by MOS transistors 3, 4 and a resistor 6 by the voltage of the voltage source 8, an R-S flip-flop (R-SFF) 7 is transferred from a set state to a holding set, and to a reset state and a reset signal is outputted. Subsequently, by setting suitably the size or resistance value of the MOS transistor, a power supply voltage by which the R-SFF 7 outputs the reset signal is set to a power supply voltage by which an element comes to completely a stable state. In such a way, the reset signal can be sent surely to other circuit without being influenced by a time constant of the rise of a power source.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power-on reset circuit, and particularly to a power-on reset circuit using a MOS type semiconductor integrated circuit.

[Prior Art] First, a conventional power-on reset circuit will be described with reference to FIG.

In the illustrated power-on reset circuit, one end of a resistor 10 is connected to one end of a capacitor (capacitance) 11 and an input terminal of an inverter logic element 12. Furthermore, resistor 1
The other end of the capacitor 11 is connected to the voltage source 8, and the other end of the capacitor 11 is grounded.

The output end of the inverter logic element 12 is connected to the output terminal 9. In this power-on reset circuit, resistor 1
0 and the time constant of the capacitor 11 is set larger than the time constant of the rise of the voltage source 8.

Here, referring also to FIG. 4, when the voltage of voltage IX8 changes as shown by curve C in FIG. It changes as shown by curve a in Figure (a). At this time,
When the input voltage a of the inverter logic element 12 exceeds a predetermined threshold voltage.

The output terminal 9 receives an inverted signal of the previous state, that is, the signal shown in FIG.
), a reset signal indicated by b is output.

[Problems to be Solved by the Invention] In the conventional power-on reset circuit described above, the reset time is determined by the time constant of the resistor 10 and the capacitor 11 and the time constant of the voltage source 8. Therefore, if the time constant of the rise of the voltage source becomes larger than the time constant determined by the resistor 10 and the capacitor 11, there is a problem that the reset cannot be applied.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power-on reset circuit that can perform reset regardless of the voltage source rise time constant.

[Means for Solving the Problems] In the present invention, a first resistance value and a second resistance value less than or equal to the first resistance value are provided.
first and second variable resistance means having a resistance value selectively set, the first variable resistance means being connected to a power source via the first resistor by a first contact; Second
variable resistance means is connected to the power source and to a second resistor by a second contact;
and a second contact are connected to a flip-flop, and the flip-flop sends out a reset signal based on the first and second contact voltages.

Specifically, the first variable resistance means includes first and second MOS transistors whose gates and drains are connected, and the source of the first MOS transistor is connected to the drain of the second MOS transistor. , the drain of the first MOS transistor is connected to the first contact, and the second variable resistance means has third and fourth MOS transistors whose gates and drains are connected, respectively.
an OS transistor, the source of the third MOS transistor is connected to the drain of the fourth MOS transistor, the source of the fourth MOS transistor is connected to the second contact, and 4 MOS
The transistor is turned on when the gate-source voltage exceeds a predetermined threshold voltage, and the first resistance value is set when the first to fourth MOS transistors are off, and the first resistance value is set when the first to fourth MOS transistors are off. The second resistance value is set when the first to fourth MOS transistors are in the on state, and the second resistance value is set when the first to fourth MOS transistors are in the on state.
The resistance value changes depending on the gate-source voltage. This changes the first and second contact voltages.

[Example] The present invention will be explained below with reference to Examples.

Referring to FIG. 1, M with the gate and drain connected
The source of the OS transistor 1 is connected to the drain of a MOS transistor 2 whose gate and drain are connected. The source of MOS transistor 2 is grounded, and one end of resistor 5 is connected to the gate and drain of MOS transistor 1.

Furthermore, it is connected to the second input terminal of an R-S flip-flop (R-8FP) 7. Further, the source of the MOS transistor 3 whose gate and drain are connected is
MOS transistor 4 whose gate and drain are connected
connected to the drain of

The source of the MOS transistor 4 is connected to one end of the resistor 6 and roughly connected to the first input terminal of the R-8FF 7. The other end of the resistor 6 is grounded, and the resistor 5
The other end and the gate and drain of the MOS transistor 3 are connected to a voltage source 8.

The output of R-9FF 7 is connected to output terminal 9.

The operation of the power-on reset circuit described above will now be described with reference to FIGS. 2(a), 2(b), and 5.

The current-voltage characteristics of a MOS transistor whose gate and drain are connected are shown in Figure 5, and VGS (
The off-on state changes at the point where the gate-source voltage) exceeds the VT1 threshold voltage). In other words, it is equivalent to high resistance in the off state.

In the on state, it has an on-resistance value that changes depending on the gate-source voltage.

In FIG. 2(a), y indicates the power supply voltage at which the MOS transistors 1 and 2 are turned on.

(2) indicates the power supply voltage at which the MOS transistors 3 and 4 are turned on. ■2. , is a power supply voltage at which the R-9PP 7 enters a reset state and outputs a reset signal.

The second input terminal of the R-8PP 7, that is, the contact potential between the gate and drain of the MOS transistor 1 and the resistor 5 is the voltage between the MOS transistor 1 and the resistor 5 at the power supply voltage V.
Since the OS transistor 2 is turned on, the state shown in FIG.
) changes like curve a.

The first input terminal of R-3FF 7, that is, the contact potential between the source of MOS transistor 4 and resistor 6 is as follows.

At the power supply voltage V, MOS transistor 3 and MOS
Since the transistor 4 is turned on, the curve changes as shown in FIG. 2(a). On this occasion.

The threshold voltage of the R-3FP 7 changes as shown in FIG. 1 as the power supply voltage d increases. For this reason, Figure 2 (
As shown by the solid line e in b), in section A it enters a reset state and outputs a logical value "0", and then in section B it enters a holding state and outputs the same logic value "0°" as in the set state.Then, for one section C In this case, the logic value “1” is set because it is in the reset state.
” is output.

In this way, in the power-on reset circuit of the present invention, the voltage of the voltage source 8 is used to create the resistance divided voltage of the MOS transistor 1, the MOS transistor 2, and the resistor 5, which is equivalent to a variable resistor, and the voltage of the voltage source 8. R-
The 8PP 7 is caused to transition from the set state to the hold state and then to the reset state to output a reset signal.

As described above, in the power-on reset circuit of the present invention,
The power supply voltage v, and the power supply voltage V can be determined by appropriately setting the size or resistance value of the MOS transistor. Therefore, the power supply voltage V, which outputs the reset signal.

, can be easily set, and the power supply voltage V,. By setting , to a power supply voltage at which the element is in a completely stable state, it is possible to reliably send a reset signal to other circuits without being affected by the time constant of the rise of the power supply.

[Effect of the invention] As explained above, in the present invention, after the power is turned on.

Detects the power supply voltage at which the element becomes completely stable.

Since a reset signal is output, it has the effect of reliably resetting other circuits even if the time constant of power supply rise changes.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the power-on reset circuit according to the present invention, and FIGS.
Figure 3 is a circuit diagram showing a conventional power-on reset circuit, and Figures 4(a) and 4(b) are conventional power-on reset circuits. A diagram for explaining the operation of the circuit, Figure 5 is MO
FIG. 3 is a diagram showing current-voltage characteristics of an S transistor. 1, 2. 3.4...MOS transistor, 5.6
...Resistor, 7...R-8FP, 8...Voltage source, 9...Output terminal. 10...Resistor. 11... Capacitor (capacitance) 12... Inverter logic element. Figure 2 (Q) Figure 3 Figure 4 Figure 5 (a) Figure 5

Claims (1)

[Claims] 1. First and second variable resistance means are provided in which a first resistance value and a second resistance value that is less than or equal to the first resistance value are selectively set; variable resistance means is connected to a power source via a first resistor by a first contact, and said second variable resistance means is connected to said power source and to a second resistor by a second contact. and the first and second
A power-on reset circuit characterized in that a contact is connected to a flip-flop, and the flip-flop outputs a reset signal based on the first and second contact voltages. 2. In claim 1, the first variable resistance means includes first and second MOS transistors whose gates and drains are connected, and the first variable resistance means
The source of the S transistor is connected to the drain of the second MOS transistor, the drain of the first MOS transistor is connected to the first contact, and the second variable resistance means has a gate and a drain, respectively. comprising third and fourth MOS transistors connected to
The source of the third MOS transistor is connected to the fourth MOS transistor.
connected to the drain of the S transistor, and the fourth MO
A power-on reset circuit characterized in that a source of the S transistor is connected to the second contact. 3. In claim 2, the first to fourth
The MOS transistor is turned on when the gate-source voltage exceeds a predetermined threshold voltage, and the first resistance value is set when the first to fourth MOS transistors are off, A power-on reset characterized in that the second resistance value is set when the first to fourth MOS transistors are in an on state, and the second resistance value changes according to the gate-source voltage. circuit.