JPH03151735A - Data communication system - Google Patents

Abstract

PURPOSE:To send data of plural channels serially through a single signal line by sending a specific header in a duty of a preceding pulse in each data channel and sending an optional data in a duty of a succeeding pulse. CONSTITUTION:For example, 3 data channels A, B, C are set to send 3 kinds of data. HA, HB, HC are headers of each channel and DA, DB, DC are data. Although the data DA-DC are set optionally in a range of a period T, the data has a larger value than a maximum value M of the header in order to distinguish it from the header actually and set in a range below the period T. In this case, a lower limit margin alpha and an upper limit margin beta are used and a margin alpha is added further to a transmission data longer than the M and the value is set to be T-beta or below. Thus, when the data of plural channels are sent serially, one each of a signal line 3 and ports P1, P2 in use is enough.

Description

[Detailed Description of the Invention] [Summary] To enable serial transmission of data of multiple channels (or steps) using a single signal line, regarding a data communication system that transmits data with a duty of pulses of a constant period. The purpose is to allocate two consecutive pulses of a constant period pulse train to multiple data channels, and each data channel transmits a unique header with the duty of the preceding pulse, and transmits arbitrary data with the duty of the subsequent pulse. Configure it to do so.

[Industrial application field]

The present invention relates to a data communication system that transmits data with a pulse duty of a constant period.

When transmitting multiple types of data in communication between CPUs, it is difficult to install signal lines for each channel and transmit them in parallel.
This is undesirable because it reduces the efficiency of using the boat and signal line.

[Conventional technology]

If a serial port is used for data communication between CPUs, l data can be transmitted as a multi-bit digital value. However, since the number of serial ports having communication functions is limited, it becomes necessary to use a port other than the serial port for data communication. In this case, a method of setting the duty of a pulse with a constant period T in accordance with the data to be transmitted is attracting attention as a relatively simple and useful data communication method.

[Problem to be solved by the invention]

However, even with the above-mentioned pulse duty type data communication method, the data type (channel or step)
When the number of ports increases, there is a problem that the number of ports and signal lines used increases.

The present invention enables serial transmission of a plurality of types of data even through a single signal line in a pulse duty type data communication system.

[Means to solve the problem]

FIG. 1 is a block diagram of the present invention, where l is a transmitting side CPU, 2 is a receiving side CPU, and 3 is a single signal line laid from the boat PL of CPU1 to the boat P2 of CPU2. A timer match output port is used for the sending port Pi, and an edge interrupt port is used for the receiving port P2.

[Effect]

The CPUI transmits a pulse train with a period T from the boat P1. In this pulse train, two consecutive pulses are used as a set, and each set is assigned to a plurality of data channels. In each data channel, a unique header is transmitted with the duty of the first pulse, and arbitrary data is transmitted with the duty of the subsequent pulse. The duty in the header section is a unique value indicating to which data channel the subsequent data belongs. On the other hand, the duty of the data part is variably set depending on the data value to be transmitted.

Figure 2 shows an example in which three data channels A, B, and C are set up to transmit three types of data: HA, HB, and H.
C is the header of each channel, DA.

DB and DC are data. - For example, T=5m
s, HA=1ms, HB=1.5ms, I
C=2.0LIls.

Data DA-DC can be set arbitrarily within the period T, but in reality, to distinguish it from the header, the maximum value M (
In this example, it has a value larger than 2m5) and is set within a range less than the period T so as not to be integrated with the header of the next channel. At this time, the lower limit margin α and the upper limit margin β
may be used to add α to the transmission data longer than M, and to set the value to be less than or equal to (T−β).

When data of a plurality of channels is transmitted serially in this manner, only one signal line 3, one baud 1-Pl, and one baud P2 are used.

〔Example〕

3 and 4 are flowcharts showing one embodiment of the present invention, and are adapted to the system configuration of FIG. 1.

FIG. 3 is a flowchart of the transmission process by the transmitting side CPUI, in which the edge counter C counts the number of edges (rising and falling) of the pulse sent from the output port P1.
NT, a pulse width register D in which the width of the H (high) level and L (low) level of each pulse is set, a conveyor register CPR7 for timer coincidence interrupt, and a timer TM indicating the current time.

In this routine, the value of timer TM is set to conveyor register CP.
It is activated every time the value of R matches, and first steps 310 to
The value of the counter CNT is determined at Sin. This example is the second
Since it is assumed that three data channels A to C are repeated as shown in the figure, the value of counter CNT is 0 to 11.
Varies within the range of .

CNT=O refers to the falling edge of the first data channel A's Herada HA. Therefore, if it is determined that CNT=O in step SIO, header II is stored in register D in step S20.
Set the width of A to 1ms. Then, since this header HA is at the L level, data "1" for raising the port PI from L to H after llll1s is set in the register for the port PL in step S31, and then the process moves to step S33. In this step S33, the value of the counter CNT is determined, and if CNT≧11, the value of the counter CNT is determined in step S34.
NT is cleared, and if not, the counter CNT is incremented in step S35, and then the process moves to step S36. In this step 336, the value of register D and the current value of timer TM are added and the result is set in conveyor register CPH.

In this way, 1 ms after the timer TMO value coincides with the conveyor register CPRO value, baud P1 rises from L to H, and this routine is restarted.

At this time, since CNT=1, the process moves from step Sll to step S21, and register D is now set to (51) ms.
is set.

This is from the pulse period T = 5ms to the header HA width of 1ms.
This is the width of the remaining H level after subtracting . At this time, it is necessary to lower the boat P1 from H to L, so set "0" in the register for the boat P1 in step S32.Next, in step S33, if CNT≧11, Since the determination is made, the counter CN is set in step S35.
T is incremented so that CNT=2), and in step S36, the conveyor register CPR is set to the next value (D+T
Set M) and finish. D at this time is (51)
It is ms.

Eventually, when the timer ticks down, this is the falling edge of the pulse in the header section of data channel A, so next we move on to the configuration of that data section. In this case, CN T =
2, the process branches from step SL2 to step S22, where data DA is set in register D. At this time, the aforementioned data extension α is added as a margin to improve the distinguishability from the header. Since this data DA and the extension α are all at the L level, the process moves to step S31 and is set to P1←l. Below, steps 333 to S
36 and ends in the same manner as in the case described above.

Eventually, when the timer ticks down, since it is CNT-3, the process branches from step 313 to step S23, where the remaining H level width (5-DA-α) is stored in register D.
is set to At this time, in step S32, Pi←0
, and the process moves to step S33.

As described above, when the timer ticks next, the boat Pl falls from H to L, so that the entire waveform of data channel A is completed. Steps S14 to S1
n, S24~S2 n is data channel B, C
A similar process is shown for . In other words, CNT=
4-7 are for channel B, CNT=8-1
1 is for channel C.

FIG. 4 is a flowchart of the reception process by the receiving side CPU 2, in which, in addition to the pulse width register D and timer TM, the interrupt occurrence time register R and header identification flags FA, FB, and FC are
use.

This routine is started every time the input level of boat P2 changes, and first, in step S41, the input level of boat P2 changes.
or rising (L-H). If it is a falling edge, the timer TMO value at the time of interrupt is set in register R in step S42, and then the interrupt edge is inverted in step 343. On the other hand, when the rising edge occurs, register D is stored from the current interrupt time TM to the previous interrupt time R in step 351.
Set the value after subtracting , that is, the width of the L level. In steps 352 to S54, the value of D is set to 1ms and 1.5ms.
, 2ms to determine the headers HA, HB, and HC. At this time, if it is determined that the header is one of the headers, the corresponding header identification flag FA-
Set one of the FCs.

If all of the determinations in steps 352 to 354 are N (no), the value of D in step S51 is not the headers HA to HC, in other words, it is any of the data DA to D'C, so the process branches to step S61. do. Step 561-3
At 63, it is determined which channel the data belongs to from the values of flags FA to FC. If FA=1, data DA is calculated in step S64. This process is an operation of subtracting the data extension α added on the transmitting side from the value of register D. Similarly, if FB=1, data DB is calculated in step S65, and if FC=1, data DC is calculated in step 366. After that, flag FA is set in steps 367 to S69.
~F” After clearing C, the process moves to step S43.

In this system, the interrupt occurrence time register R on the receiving side is L.
SB is lμs and the margin on the transmitting side is α=β−0.5m
s, data can be transmitted with a resolution of 1/7000.

〔Effect of the invention〕

As described above, according to the present invention, there is an advantage that a plurality of types of data can be transmitted using only a single port of each CPU and a single signal line between the two.

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[Brief explanation of the drawing]

FIG. 1 is a block diagram of the present invention, FIG. 2 is a transmission waveform diagram of the present invention, and FIGS. 3 and 4 are flowcharts showing embodiments of the present invention. In the figure, 1 is a transmitting side CPU, and 2 is a receiving side CPU. 3 is a signal line, PL and P2 are ports, HA-IC is a header, and DA-DC is data. Applicant Fujitsu Ten Ltd.

Claims (1)

[Claims] 1. Assign each two consecutive pulses of a pulse train with a constant period (T) to multiple data channels (A, B, C), and each data channel has a unique header (HA, HB, HC) based on the duty of the preceding pulse. A data communication method characterized by transmitting arbitrary data (DA, DB, DC) with the duty of subsequent pulses.