JPH03150797A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the working ratio and the reliability of a semiconductor memory device even with a defective bit that is produced during application of a memory system by providing a spare memory to relieve the defect of a main memory and a defect storage part to store the defect of the main memory. CONSTITUTION:A defect of a data line 12 is detected in the data line direction when a main memory 2 is scanned in the data line direction. In such a case, a data line defect detection signal 106c and a data line defect position signal 106d are written in binary numbers into the input/output bits of a defect storage part 14' against a defective address. Then a read line defect detection signal 106a and a word line defect position signal 106b are read out of the part 14' at a high speed and a multi-bit output system. Therefore an input/output switch circuit 100' switches an input/output signal terminal 104 of the memory 2 in response to the signal 10 and selects a spare ward line W1 of a spare memory 18 for relief of defects.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to defect relief in semiconductor memories, and particularly to a semiconductor memory device suitable for extremely large capacity memories.

[Conventional technology]

First, a conventional semiconductor memory device will be explained in order to explain the basic functions of the present invention. Conventionally, a defect relief method as shown in FIG. 2 has been used in semiconductor memory devices.

This figure is described in Japanese Patent Application Laid-Open No. 1-133298, in which a well-known memory is used for address conversion and a method is proposed for repairing defective word lines and bit lines. An address conversion circuit is provided for each line or data line.

The presence or absence of a defective address in the main memory relative to the external address and the new address are written in each. Therefore, when the external address reaches such a defective address, a new address is applied from the address conversion circuit to the spare memory, and the input/output signal terminal is connected to the spare memory side.
This is a redundant configuration and method for reading and writing normal bits.

Also, Special Publication No. 46-25767, Special Publication No. 47-653
As described in Section 4, there is a redundancy method in which the address of a defective bit is stored in an associative memory device, a match is detected between the stored contents of the external address and the defective bit address, a new address is output to a spare memory, and the normal bit is read out. It has been proposed.

[Problem to be solved by the invention]

The problem with the above-mentioned prior art is that an address conversion circuit is used when accessing the spare memory. This address conversion operation time and the access time of the spare memory become the access time of the memory device.

Therefore, if the main memory and the spare memory have the same level of access time, it is difficult to obtain the same level of access time as the main memory for the memory device as a whole. On the other hand, as a solution to this problem, it is conceivable to increase the speed of the address conversion circuit and also increase the speed of the backup memory. However, this requires advanced circuit technology and process technology, resulting in a high price.

Therefore, the basic object of the present invention is to provide a large-capacity semiconductor memory device with a simple method for repairing defective bits, simple hardware for realizing this repair, and fast access time. It is to provide.

[Means to solve the problem]

According to one embodiment of the present invention, the above object is solved as follows.

When replacing a defective address in main memory with spare memory, instead of converting the external address and accessing the spare memory with the new address as described above, activate the main memory, spare memory, and defective memory at the same time with the external address, While the main memory is being accessed, the defective input/output signal terminal is switched at high speed based on the information in the defective storage section, thereby relieving the defective bit. This makes it possible to achieve high-speed access time for the entire memory device.

[Effect]

An external address is applied to the main memory, a spare memory, and a defective memory section, and a word line defect detection signal indicating the presence or absence of a word line defect in the main memory and the location of the defective word line is output from the second output of the first defective memory section. is generated. When a word line defective location signal is actually generated, one of the plurality of spare memory cells of the first spare memory responds to the external word line address and data line address, and also responds to the input of the main memory. The output signal terminal is switched to the input/output signal terminal of the first spare memory by the word line defect detection signal and the word line defect position signal, and as a result, the defect related to the word line of the main memory is relieved by the first spare memory. Ru.

Similarly, a data line defect detection signal indicating the presence or absence of a data line defect in the main memory and the position of the defective data line is generated from the second output of the second defective memory section. When a data line defective position signal is actually generated, one of the plurality of spare memory cells of the second spare memory responds to the external data line address and the word line address, and also responds to the external data line address and word line address. The output signal terminal is switched to the second spare memory by the data line defect detection signal and the data line defect position signal, so that defects related to the data lines of the main memory are relieved by the second spare memory.

In the above operation, the main memory, spare memory, and defective storage section are simultaneously accessed using an external address, that is, data is prepared in advance up to the input/output terminal, and the input/output signal terminal is switched according to the defective bit. The capacity of this defective storage section may be three to four orders of magnitude smaller than that of the main memory or spare memory.

It can be faster than main memory or spare memory.

Therefore, the access time of a memory device is determined by the access time of the main memory or spare memory, excluding the delay in input/output terminal switching time, which is insignificant compared to the access time of the entire device, since the speed of the defective memory section can be increased. . Therefore, the semiconductor memory device of the present invention can speed up the access time compared to the conventional defect repair method using an address conversion circuit.

Further, the first defective memory section that generates a word line defect detection signal and a word line defective position signal in response to a word line address is a general semiconductor memory with a multi-bit output format, such as a non-volatile semiconductor memory (E PROM). , EEPRO
It is composed of a semiconductor memory (SRAM, etc.) with a battery backup.

Similarly, a second defect memory section that generates a data line defect detection signal and a data line defect position signal in response to a data line address is a general semiconductor memory with a multi-bit output format, such as a non-volatile semiconductor memory (E PROM, EEP
ROM, 7! ROM, etc.) or battery-backed semiconductor memory (SRAM, etc.). Furthermore, an associative memory device using the above semiconductor memory may be used.

As described above, main memory defect relief can be realized at high speed and with a very simple method and hardware.

Other objects and novel features of the present invention will become apparent from the examples detailed below.

【Example〕

Embodiments of the present invention will be described in detail below with reference to one drawing.

FIG. 1 is a block diagram showing the principle of a semiconductor memory device according to the present invention. In the figure, 40 is a memory block chip that stores information, 2 is a main memory with a multi-bit input/output configuration which is a set of multiple memory block chips 40, 18 is a spare memory, and 108 is an external input/output signal terminal (I
110 is an external address signal, 112 is an external control signal such as memory chip activation and IF writing, 102 is an input/output signal terminal (Ilo) of the main memory 2, and 104 is an input/output signal terminal (Ilo) of the spare memory 18. 6 indicates the word line address direction of the memory block chip 40 or the spare memory 18, and 4 indicates the data line address direction of the memory block chip 40 or the spare memory 18.

Further, 26a, 26b, 26c indicate defective bits, 8,
Reference numeral 10 indicates defective word lines in which the defective bits are present in the word line direction, and each is designated as Wl.

Let it be Wk. On the other hand, wl in the spare memory 18 is a defective word line Wl in the main memory 2, and wk is a defective word line @W in the main memory 2.
k, respectively, and are activated after main memory relief is applied.

Reference numeral 8' indicates a good word line of another memory block chip 40 that is selected at the same time as the defective word line 8.

10' indicates a good word line of another memory block chip 40 that is selected at the same time as the defective word line 10.

Furthermore, 106a is a word line defect detection signal indicating that there is a word line defect in one of the memory block chips 40 of the main memory 2 having a multi-bit input/output configuration, and 106b is an input signal of the memory block chip 40 in which the word line defect exists. A word line defective position signal indicating the position of the output signal terminal 102 (Ilo).

Reference numeral 14 denotes a defect memory section having a multi-bit input/output configuration for storing the word line defect detection signal 106a and word line defect position signal 106b, and T W 1 '' T W n indicates the input/output signals 106 a and 106 b of the defect memory section 14 . Furthermore, 100 is a word line defect detection signal 10 of the defective storage section 14 when the main memory 2 is defective.
6a, each input/output signal (Ilo
) 102 as the input/output signal terminal (Ilo) of the spare memory 18
This is an input/output switching circuit that switches to 104. 120 is a decoder circuit which receives the word line defective position signal 106b, is activated by the word line defective detection signal 106a, and generates a signal for switching between the input/output signal terminal (Ilo) 102 and the input/output signal terminal (Ilo) 104; be.

In addition, SW 1 "" SW of the input/output switching circuit 100
n is a changeover switch between the input/output signal terminal (Ilo) 102 and the input/output signal terminal (Ilo) 104;
22 a-, 22 bx to 22 b are respective terminals of the changeover switches 5W-t to SWn. This switch typically consists of a two-power, single-output multiplexer. These 22a1 to 22a are connected to the input/output signal terminal 102 of the main memory 2, while 22b1 to 22b are commonly connected to the input/output signal terminal 104 of the spare memory 18,
The decoder circuit 120 connects the input/output signal terminal 102 of the main memory 2 and the input/output signal terminal 10 of the preconditioning memory 18.
4 connection status is controlled.

Next, the operation of this block diagram will be explained. In the same figure,
The defective line has defective bits 26a and 26b.

26c are respectively 8 and 10 defects in the word line direction (wi, wk in the figure).

That is, in the block chip 40 of the main memory 2, at least two memory cells 26a and 26b become defective bits in relation to the word line (Wl) 8, so these memory cells 26a and 26b are defined as word line defects. And it is relieved by two spare memory cells related to the spare word line (wl) of the spare memory 18. Furthermore, the memory cell 26c having a defective bit is not defined as a defect in the word line direction or a defect in the data line direction, but is defined as a defect in the bit nature. However, for convenience, this defective bit memory cell 26c is regarded as defective in the word line direction, and the spare word line (w k
) is saved by one spare memory cell related to the memory cell.

The memory capacity of the defective storage unit 14 in the above repair operation is, for example, in a 4M byte semiconductor memory device with an 8-bit input/output signal configuration using 8 chips of address multi-input type 4M bit (4M word x 1 bit configuration) DRAM. , the word line address is 2 bits, the word line defect detection signal 106a is 1 bit, and the word line defect position signal 106b for decoding 8 bits of input/output signals is 3 bits, so it can be configured with a small memory capacity of 2K x 4 bits. .

In this embodiment, the spare memory 18 is also activated at the same time as the main memory 2 is activated by the address signal 110 and the control signal 112, and the defective storage section 14 is also activated at the same time.

Therefore, the output of the small-capacity defect storage section 14, that is, the word line defect detection signal 106a, the word line defect position signal 10
The input/output signal terminal 102 of the main memory 2 and the input/output signal terminal 104 of the spare memory 18 in the input/output switching circuit 100 are switched based on the activation time of 6b and these signals.
The sum of the switching times becomes the access time of the memory device.

The switching time of the latter is insignificant compared to the overall access time, and the output activation time of the former defective switching circuit is sufficiently faster than the time of accessing the large capacity main memory 2. Therefore, the main memory 2. Spare memory 18. The defective storage unit 14 operates in parallel and simultaneously, and the input/output signal (I 10
) to confirm the terminal.

There is no reduction in the access time of the entire semiconductor memory device, and the device can operate at high speed. As a result, the access time of the semiconductor memory device is reduced by the added input/output switching circuit 100. Defective storage unit 14. It is determined by the original access time of the main memory 2 without being influenced by the delay time of the relief circuit by the spare memory 18.

Further, in this embodiment, there is only one spare memory 18 and two main memories.
When replacing n memory block chips 40, unless the defective addresses of each of the memory block chips 40 match among the plurality of memory block chips 40, that is, the word line defect is replaced by another memory block chip 4.
As long as it is not zero, l/n of the total memory capacity of the main memory 2 can be saved.6 For example, if the input/output signal of the main memory 2 is 8 bits, 1 bit of it is replaced with the spare memory 18. However, since the defective memory section 14 stores all word line addresses, by increasing the spare memory 18, in principle, even if all of the main memory 2 has defective bits, the main memory 2 can be saved 100%. It is possible to do so.

Note that this memory inspection and a defect relief method by writing defective bits into the defective storage section 14 based on the inspection results will be explained in detail later.

Based on the semiconductor memory device of the present invention shown in FIG. 1, FIG.
A second embodiment will be shown in which data line defects can also be relieved.

In the figure, 2 is a main memory consisting of a set of a plurality of memory block chips 40, and 14' is a defective storage section.

18 and 20 are spare memories for relieving word line defects and data line defects, respectively, and 108 is an external input/output signal terminal (Il
o), 110 is an external address signal.

112 is an external control signal such as memory chip activation or writing, 6 is the word line address direction of the memory block chip 40 or the spare memory 18.20, and 4 is the data line address direction of the memory block chip 40 or the spare memory 18.20. show.

Also 26a, 26b, 26c, 28a, 28b.

28c and 28d indicate defective bits, and defective bit 26a
, 26b and 26c become word line defects 8 and 10 as described in FIG. 12 is the defective bit 28a, 2
Defective data line with 8b.

13 also indicates a defective data line with the defective bits 28c and 28d, while 12' and 13' indicate good data lines of another memory block chip 40 that are selected at the same time as the defective data line.

Further, 106a is a word line defect detection signal, 106b is a word line defect position signal, 106c is a data line defect detection signal, and 106d is a data line defect position signal. Also T W
1 to TB11 are memory arrays for storing the signals 106a, 106b, 106c, and 106d of the defective storage section 14.14' composed of memory blocks. 120, 120' are decoder circuits that generate signals for switching between the input/output signal terminal (rlo) 102 and the input/output signal terminal (Ilo) 104° 114 of the spare memory 18.20.

The above defect detection signal and position signal 106a-106d
is connected to the input/output signal terminal 102 of the block chip 40 and the input/output signal terminal 104 or 11 of the spare memory 18 or 20 via the decoder circuits 120, 120'.
Controls the switching of 4.

Further, 50 receives the outputs of the decoder circuits 120 and 120', and when a word line address and a data line address are defective at the same time on the same memory block chip 40, priority is given to a defective address for preferentially relieving a defective word line, for example. This is a judgment circuit.

Furthermore, 100' is the memory block chip 4 of the main memory 2 in accordance with the switching instruction of the signals 106a to LO6d.
This is an input/output switching circuit that switches and connects the input/output signal terminal 102 of 0 and the input/output signal terminal 104 or 114 of the spare memory 18.20 to the external input/output signal terminal 108. -8Ws' to S W,' of the input/output switching circuit 100' are the input/output signal terminal (Ilo) 102 and the input/output signal terminal (I
lo) 104, 114 changeover switch, and is generally composed of a three-man power, one-output multiplexer. 22a
x~22a,.

22b1 to 22bn, 22cl to 22c, and l are terminals of changeover switches SW1' to swn', respectively.

22as to 22a are the input/output signal terminals 10 of the main memory 2
2, 22b1 to 22bn are connected to the input/output signal terminal 104 of the spare memory 18, and 22cl
~22cn is connected to the input/output signal terminal 114 of the spare memory 20. That is, the memory block chip having a defective word line or defective data line in the main memory 2 is determined by the input/output switching circuit 100' based on the information of the word line defective position signal 106b and the data line defective position signal 106d which are output from the defective memory section 14'. 40 input/output signal terminals 102 are determined, and activated by the word line defect detection signal IQ6a and the data line defect detection signal 106c, the spare memory 18 or 20 is activated.
Controlled by switching between input and output signal terminals.

In addition to the embodiment shown in FIG. 1, a spare memory 20 for relieving data line defects is added, and a defect storage section 14' is used to control the data line.
and by changing the input/output switching circuit 100'.

Furthermore, when a defective word line address and a defective data line address cross each other in the same bit in one memory block chip 40, priority is given to repairing defects in the word line direction by the priority determination circuit 50. This priority determination circuit 50 activates the spare memories for both the word line and the data line due to the cross failure, so the spare memories for the word line and the data line are simultaneously activated at one input/output (Ilo) terminal. This is because data collision may occur depending on the access time difference between the input and output signals of the spare memories 18 and 20. Since this is not desirable for the memory device, priority is given to, for example, word line relief and connection to one input/output terminal. This word line relief priority is given to DRA
In the case of DRAM, RAS (Row A
The word line address called CA S (Colo
+mn AddressSignal) The data line address of the address is input. Therefore, by prioritizing the word line that is input first, it is possible to avoid the circuit delay time in which the data line address that is input later is input and prioritized, and as a result, the relief circuit system is Speed-up can be achieved. On the other hand, in memory devices of single address input format, such as SRAM.

Generally, a word line address and a data line address are input at the same time, and in this case, either the word line address or the data line address may be given priority processing depending on the defective mode of the word line/data line.

Next, the operation of the block diagram shown in FIG. 3 will be explained.

In the same figure, as explained in FIG.
are replaced with spare word lines Wl and wk. On the other hand, 28a
, 28b, 28c, and 28d are defective in the data line direction and are replaced with spare data lines di and dk of the data line spare memory 20.

In other words, as shown by the word line failure in Figure 1, the main memory 2
In the memory block chip 40, at least two memory cells 28a, 28b become defective bits in relation to the data line 12, so these memory cells 28a, 2
8b is defined as data line failure and spare memory 2
It is relieved by two spare memory cells related to the spare data line (dl) of 0. Similarly, 28c and 28d are relieved by the spare data line (dk). Also defective bit cell 2
6c is repaired as a word line defect in FIG. 1, but it can also be treated as a defect in the data line direction and repaired.

As mentioned above, in this embodiment, the spare memory is 18.2
Since there are 0 and 2 chips, defective bits in the word line direction and data line direction can be repaired between all the chips of the memory block chips 40 of the main memory 2. At this time, each defective address can be repaired either when the memory block chips 40 overlap or when there is a cross defect within the memory block chips 40.

Therefore, in this embodiment, as in FIG. 1, n memory block chips 40 of the main memory 2 can be repaired for word line defects and data line defects. As long as each defective word line address or data line address does not overlap between multiple memory block chips 40, up to one of each can be repaired, so 2/n of the total memory capacity of the main memory 2 can be repaired.
capacity can be saved. Furthermore, by increasing the spare memories 18 and 20 as in FIG. 1, even if all of the main memory 2 has defective bits, 100% relief is possible.

Next, a detailed explanation will be given of a defect relief method by inspecting the main memory 2 to determine whether it is good or defective and writing word line/data line defect detection signals and defective position signals 106a to 106d to the defective memory section 14' based on the inspection results. do.

The defective memory section 14' in the figure is a 4M bit (4M word x 1 bit configuration) DRA with the above-mentioned address multi-input format.
In the case of a 4M byte semiconductor memory device with an 8-bit input/output signal configuration using M, the word line address or data line address is 2 bits, the word line/data line defect detection signal 106a is 1 bit each, and the input/output signal is 8 bits. word line/data line defective position signal 106 for decoding
Each b is 3 bits, and the memory is composed of 5 total 2K x 8 bits.

Next, defect relief is carried out as follows.

That is, when a defect in the word line direction is detected for the word line 8 (Wl) by scanning the main memory 2 in the word line direction, the input/output bits (TW5 to TWn ) is the word line defect detection signal 106a.

The word line defective position signal 106b is written in binary. Furthermore, when a defect in the data line direction is detected regarding the data line 12 by scanning the main memory 2 in the data line direction, the defect storage section 14' for the address of this defect is detected.
The data line defect detection signal 106c and data line defect position signal 106d are 2 in the input/output bits (TBs to TB,) of ! !
! Written in numbers.

Here, when an external address corresponding to the selection of the defective word line 8 (Wl) of the main memory 2 in FIG. is read out quickly in multi-bit output format. Therefore, in response to the word line defect detection signal 106a and the word line defect position signal 106b, the input/output switching circuit 100' switches the input/output signal terminal 1 of the main memory 2.
02 and the input/output signal terminal 104 of the spare memory 18, select the spare word line w1 of the spare memory 18,
Defect relief is performed.

Furthermore, when an external address corresponding to the selection of the defective data line 12 (Di) of the main memory 2 is supplied, a data line defect detection signal 106c and a data line defect position signal 106d are simultaneously output from the defect storage section 14' in a multi-bit format. is read out quickly. Therefore.

The data line defect detection signal 106c, the data line defect position signal 106. In response to i, the input/output switching circuit 100' switches between the input/output signal terminal 102 of the main memory 2 and the input/output signal terminal 114 of the spare memory 20.

The spare data line d1 of the spare memory 20 is selected and defect repair is performed.

Therefore, in FIG. 3, the input/output switching circuit 100
' is a switch S Ws' ~S connected to the main memory 2
The terminals 22ax to 22a of Wn' are selected and connected to the external input/output signal terminal 108.

When a defective bit in the main memory 2 is selected, a word line or data line defect detection signal 106a is generated.

106c and a decoder that responds to defective position signals 106b and 106d.
1' to SWn' terminals 22bt to 22bn or 22
01-22cn was selected.

Spare memory 18.20 input/output signal terminals 104°114
Select.

That is, 108 is an external input/output signal terminal of the entire semiconductor memory device, and digital information of the memory cell is written into the main memory 2 or the spare memory 18 or 2o via this input/output signal terminal 108. On the other hand, reading of digital information from the memory cells of the main memory 2 or the spare memory 18.20 is executed via this input/output signal terminal 108.

Next, the above operation will be explained for the word line failure and data line failure shown in FIG. 3 based on the state diagram of the failure storage section 14' shown in FIG. T W 1 to T W4 in the same figure. T B t〜T
B a is the input/output signal/○ bit of the defective memory section 14', and the word line defect detection signal 106a is T W a
, the data line defect detection signal 106C is TB4°, and the word line defect position signal 106b is T W t = T W a .

The data line defective position signal 106d is written to TBL to TBa, respectively. The present invention will be explained below using specific examples.

The defective address value is expressed in hexadecimal, and the word line defective position signal 106b (T W 1 to T W a
) *Data line defective position signal 106d (T B 1-
T B s) is the input/output signal terminal 1 of the defective main memory 2.
The location of 02 is indicated by a binary number.The semiconductor memory device of this embodiment is assumed to have a capacity of 4M bytes using 4M DRAM of 4M words x 1 bit, and both the word line address and data line address are (7FF). It becomes rs. Furthermore, the X mark in the figure indicates that the value is a don't care, and indicates that any of the ``0'' and ``1'' levels may be used.

First, as shown in example (1) in the figure, in normal operation without defect relief, the spare memory is in a non-selected state, and the word line defect detection signal 106a (TW4)- and the data line defect detection signal 106c (TBa) The information for both is “1” level. When relieving a word line defect, the word line defect detection signal 106a goes to the "OI+" level, and the spare memory becomes a selected state. Also, when relieving a data line defect, the data line defect detection signal 106C goes to #O11.
Similarly, the spare memory becomes the selected state.

For example, in the case of a defective word line, as shown in example (2) in the figure, the defective word line 8 (Wl) in FIG. ) as IB.

Write 8-bit data "1 x x x OO00" to address (22A) 1B of defective memory section 14'. As a result, the word line address of the external address becomes (22A).
11! When the input/output switching circuit 100' reaches the external input/output terminal 108, the spare memory 1 for word line relief is connected to the external input/output terminal 108.
Eight input/output signal terminals 104 are connected. In other words, each of the input/output 8-bit switches (SW' to SWa'
), the terminal 22b1 of the switch SWI' is connected to the external input/output terminal 108, selects the spare word line W1 of the spare memory 18, and selects the spare word line W1 of the spare memory 18, and the other switches (SWz' to SWa'
) are connected to the input/output terminals 102 excluding the 0th bit of the defective input/output signal I10 of the main memory 2, and the normal bits on the spare memory 18 side are read and written. At this time, the address of the other spare memory 20 is also input and selected, but by controlling control signals such as write signals to the inactive state, there is no possibility of erroneous writing to the spare memory 20. Also, when reading from the spare memory Since the 20 input/output terminals 114 are not connected, there are no reading errors.

On the other hand, on the input/output terminal 102 side of the memory block chip 40 of the main memory 2, the defective input/output signal I10 of the main memory 2
Terminal 22a of switch SWi connected to the Oth bit of
Since t is not connected to the external input/output terminal 108, the information written to the defective address of the O bit of the input/output signal I10 will not be read out to the external input/output signal terminal 108. Therefore, in the write operation, the information written to the defective address of the O bit of the input/output signal I10 will not be There is no problem even if the defective memory block chip 40 is in the write activation state.

If the data line is defective, as shown in example (3) in the figure,
The defective data line (Dl) in FIG.
12) In the case of xs, the (
112) Write 8-bit data "0OOIIXXX" to 16. As a result, when the data line address of the external address reaches (112)1°, the input/output switching unit 100' writes the input of the spare memory 20 for data line relief. The output signal terminal 114 is switched and connected to the input/output signal terminal of the first bit of the input/output signal of the main memory 2. That is, switch s w
Terminal 22C7 of 11' is connected to external input/output terminal 108, selects spare data line d1 of spare memory 20, performs defect relief, and reads and writes normal bits.

If the word line and data line are defective at the same address, the word line defect detection signal 106a is sent.

In the case of two defective lines in which the data line defect detection signals 106c are both information 11011, it is conceivable that the same address on one chip is defective or that the defect occurs between different chips. First, let us explain the former defect.1 For example, as shown in example (4) in the figure, the input/output signal I10 of the main memory 2 in FIG.
7th bit defective data line address = (2ff) 1o
7-bit defective word line address of the same signal I10 = (
In the case of 2f flss, 8-bit data “01110111” is placed at (2ff)1° of the defective storage unit 14′ address.
As a result, when the word line address of the external address reaches (2ff)xi, the input/output switching unit 100
The external input/output terminal 10B is connected to the input/output signal terminal 104 of the spare memory 18 at the switch SWν of '.
That is, the external input/output terminal 108 is switched from 2288 to 22b8 of the switch SWa' connected to the input/output signal terminal 102 of the 7th bit of the input/output signal I10 of the main memory 2. On the other hand, the data line address of the external address is (2
When ff)re is reached, the external input/output terminal 108 is connected to the input/output signal terminal 114 of the spare memory 20 at the switch SWa' of the input/output switching section 100'. That is, the external input/output terminal 108 receives the input/output signal I10 of the main memory 2.
The switch SWa connected to the input/output signal terminal 102 of the 7th bit is switched from 2288 to 2208. Furthermore, when a word line defect and a bit line defect reach the same address (2ff) 1a on one chip, in order to process the word line preferentially, the external input/output terminal 108 is connected to the switch S.
It is connected to 22b6 of Wa'. Therefore, spare memory 1
Only the memory cells on the spare word line 8 are replaced, and the memory cells (111)ze on the spare data line of the spare memory 20 are not used.

Next, a case where word lines and data lines in different memory block chips 40 are defective will be described.

In example (5) in the figure, the input/output signal of main memory 2 is
2-bit word line address of ○ = (123)18 and 5-bit data line address of input/output signal I10 = (1
23) If za is defective, 8-bit data “01010010” is stored at address (123)so of defective storage section 14'.
Write. As a result, when the word line address of the external address reaches (123)io, the input/output switching circuit 100
', the input/output signal terminal 104 of the spare memory 18 is connected to the input/output signal terminal 10 of the second bit of the input/output signal of the main memory 2.
2 and is connected to the external input/output terminal 108.

Also, the data line address of the external address is (123)1e
When the input/output switching circuit 100' switches the input/output signal terminal 114 of the spare memory 20 to the input/output signal terminal 102 of the 5th bit of the input/output signal of the main memory 2, and connects it to the external input/output terminal 10g. A normal bit is read or written by zero or more operations.

Note that the memory used in the defect storage section 14' shown in FIG. 4 has an 8-bit configuration, and the word line defect detection signal 106
a, word line defective position signal 106b;

A data line defect detection signal 106c, a data line defect position signal 106d, etc. are output at the same time according to an external address signal. Therefore, each signal 106a to 106d
D may be latched and used during the active period of the memory device.
Memory devices using RAM generally use an address multi-input format, and the memory chip is RA S (R
The word line address is internally latched using the CA S (ColomAddressSignal) control signal.
The data line address is internally latched using the (Address Signal) control signal and a memory cell is selected.

Therefore, the defective storage section 14' uses a memory with an 8-bit configuration, and divides the memory into two into 4-bit units, each of which corresponds to the signal 106a, 106b or 10.
6c and 106d, and latching and using each of them based on the timing of the RAS control signal or CAS control signal is also considered.

FIG. 5 shows a block diagram of a semiconductor memory device according to another embodiment of the present invention, which differs from the one shown in FIG. Or, unlike FIG. 3, the other things are the same. Input signal line 302 of this buffer circuit 300
is connected to the external output signal (Ilo) 108, and the word line/data line defect detection signals 106a, 106c and defect switching signals 106b, 106d are connected to the output signal line 304 of the buffer circuit 300. By using the buffer circuit 300, the upper rudder signal 1 to the defective storage section 14' is
Writing of 06a to 106d becomes easy.

That is, based on the test results of the main memory 2, the above-mentioned signals 106a to 106d are set to the external input/output signal terminal 108, and written to the address of the defective memory section 14' corresponding to the defective address, thereby allowing online defective bit relief. Writing becomes easier, and memory inspection time and repair processing time can be saved. In addition, as another effect, the output signal line 30
By controlling the main memory 2 and the spare memory 18, 20 from the outside, each of the input/output signal terminals 104 and 114 can be independently selected, so that the characteristics of each memory can be inspected.

Note that the buffer circuit 300 is composed of, for example, a tri-state buffer, and is inactivated by an external input signal except for write operations to the defective storage section 14', and is inactivated during normal read/write operations of the semiconductor memory device. It is controlled so that it does not have any influence. Also, the defective memory section 1
Reading of the data written to the buffer circuit 4' is possible by using a bidirectional buffer in the buffer circuit 300, but even in that case, the control is controlled so as not to affect normal read/write operations. Furthermore, as another method for reading data written in the defective storage section 14', the input/output switching circuit 100'
Switch S W 1 ” S W , connected to terminal 22
as~22an, 22bx~22bn, 22c
A separate connection terminal from the
' input/output signals 106a to 106d are connected. By controlling this other connection terminal externally.

Reading becomes possible.

FIG. 6 shows a block diagram of a semiconductor memory device according to another embodiment of the present invention. In FIG. 6, 70 is a control circuit; 72.74
The present embodiment differs from FIG. 3 only in that a control circuit 70 is added, and is otherwise the same as the one shown in FIG. When the memory device is configured with a DRAM, this control circuit receives the control signals RAS, CAS, and WE of the memory device and holds input/output data during the active period of the memory device.
Control is performed so that there is no erroneous writing or reading error in the spare memory by, for example, holding the write signal WE times the signal. In addition, when the external address changes simultaneously with the RAS or CAS signal, the outputs 106 a to l of the defective memory section 14'
In order to latch O6d with the RAS or CAS signal, the RAS or CAS signal is delayed until the access time of the defective storage section 14' where LO6a to LO106d are output.

FIG. 7 shows a specific embodiment of the defective memory section 14'. 14' in the figure is composed of a nonvolatile memory block, and outputs an input/output signal I10 for an external address in a plurality of bits.

30.34 is a word line defect detection signal 106 indicating the presence or absence of a defective address in the memory block chip 40 of the main memory 2.
a and the data part of the data line defect detection signal 106c, and 32.36 is the word line defect position signal 106 indicating the position C of the input/output signal terminal of the main memory 2 where the defect exists.
b and the data portion of the data line defective position signal 106d.

In the figure, when the main memory 2 has an n-bit configuration, that is, it is composed of n memory block chips 4o, the data portions 30 and 34 of the word line defect detection signal 106a or the data line defect detection signal 106c each have at least 1 bit. Consists of. In addition, the word line defective position signal 106b
Or the data part 32 of the data line defective position signal 106d
．． 36 are each comprised of at least login bits.

For example, main memory 2 has an 8-bit input/output signal configuration (n, 8).
In this case, the number of bits of the data portions 32 and 36 of the defective position signals 106b and 106d each consists of at least 3 bits.

Note that if the number of bits of the data portions 32 and 36 of the word line defective position signal 106b and the data line defective position signal 106cl is 8 bits each, and 8 spare memories are prepared, the number of memory block chips in the main memory 2 is 8. It goes without saying that all can be replaced at the same time.

FIG. 8 shows another embodiment of the defective storage section 14 shown in FIG.
Reference numeral 14 in the figure is an embodiment constructed using an associative memory device.

In the figure, 60 is an associative memory cell section which stores a defective word line address. Further, 62 is a data portion of the word line defect detection signal 106a, and 64 is a data portion of the word line defect position signal 106b. The operation will be briefly explained below.

The defective address is determined by comparing the defective word line address written in the associative memory cell unit 60 with the external word line address and detecting a match. signal 1
06a, the data part of the word line defective position signal 106b is output, and the defective address is replaced by the input/output switching circuit 100 of FIG.

In general, the associative memory cell section requires 8 to 10 transistors per cell, which increases the area occupied by the memory cell, which is more than twice that of a normal memory cell.However, on the other hand, the number of transistors that can be repaired is limited in the word direction of the associative memory. can be arbitrarily set at the time of designing the repair circuit, so when the number of memory devices to be repaired is small, there is an advantage that the defective storage section 14 can be made compact. Therefore, this embodiment using an associative memory device is suitable for a small-scale memory device whose purpose is to rescue a relatively small number of bits.

Note that although the above embodiment is configured for the purpose of relieving defective word lines, it is also possible to relieve defective data lines. This is the data line defect detection signal 106c.

The data part of the data line defective position signal 106d is converted into the word line defective detection signal 106a and the word line defective position signal 106.
This can be achieved by adding each to the data section of b and expanding the associative memory cell section so that it can also perform a match search for data line addresses.

FIG. 9 shows an embodiment in which the present invention is applied to a memory module, which is a relatively small memory device. The figure shows a main memory 2 mounted on the front side of the board, and a spare memory having the same configuration as the main memory 2 on the back side. 1 nonvolatile memory (for example, EPROM) in the defective storage section 14', and an input/output switching section 1o.
This is an example in which one relief chip, which is O' chipped, is mounted. This relief chip is the defective memory section 14' (EFR
It is also conceivable that a spare memory (18, 20) may be built in. In that case, it is expected that the number of wirings on the board will be reduced and the speed will be increased due to integration.

As mentioned above, devices used for relief other than main memory 2 can be mounted in the space behind the main memory mounting surface of the memory module, or in the empty area on the front side, in the same way as normal memory modules without relief. A level shape can be achieved.

The above two objects of the present invention are that when replacing a defective address in main memory with spare memory, instead of converting the external address and accessing the spare memory with the new address, the main memory and spare memory are simultaneously activated with the external address, The purpose is to repair defective bits by switching the input/output signal terminals of the circuit at high speed. This aims to achieve high-speed access time and high yield for the entire memory device. Therefore, the structure of the defect detection signal and defect position signal of the defective memory section, the number of input/output signal bits of the main memory and spare memory, and memories such as SRAM and DRAM are not limited, and the spirit of the present invention is not limited. Various modifications are possible without deviation.

Furthermore, the buffer circuit shown in FIG. 5 is not only used in semiconductor memory devices for the purpose of relieving both word line defects and data line defects, but also for the purpose of relieving only either word line defects or data line defects. Needless to say, the present invention can be used in a semiconductor memory device that uses an associative memory device, and it goes without saying that a relief method using an associative memory device also requires a data writing function like the buffer circuit shown in FIG.

[Invention adoption effect]

According to the present invention, defective bits that occur during use of the memory system can also be corrected, thereby improving the operating rate and reliability of the device. Furthermore, since a partially defective memory is cheaper than a good memory, the device price can be set at a lower price. Furthermore, since the semiconductor memory device of the present invention can use partially defective memory as a spare memory, it can be constructed entirely of low-cost memories.

On the other hand, the semiconductor memory device of the present invention can be configured with a general non-volatile memory that outputs multiple bits in the defective storage section indicating the defective location of the main memory.

The method for repairing defective bits is simple. The hardware to achieve this relief is also main memory.

Activate the spare memory and defective memory at the same time.

Since the semiconductor memory device has a simple configuration in which the input/output terminals are switched depending on the data in the defective memory section, and the defective memory section is a small-capacity memory, it is possible to provide a semiconductor memory device that can realize high-speed access time. Furthermore, the semiconductor memory device of the present invention can be used even while the device is in operation.

Since it is possible to write to the defective storage section from outside using software without stopping the memory device (EFROM writing time is about several μs), it is useful for improving the reliability of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the principle of a semiconductor memory device according to the present invention, FIG. 2 is a block diagram for explaining a conventional semiconductor memory device, and FIG. 3 is a block diagram for explaining the principle of a semiconductor memory device according to the present invention. 2 is a block diagram for explaining the second embodiment, FIG. 4 is a state diagram for explaining the defective storage section shown in FIG. 3, and FIGS. FIG. 7 is a block diagram for explaining the semiconductor memory device of the embodiment, and FIG. 7 is a block diagram for explaining the embodiment in which the defective storage section of FIG. 3 is configured by a nonvolatile memory block; FIG. 9 is a block diagram for explaining an embodiment in which the defective storage section in FIG. 1 is configured by an associative memory device using nonvolatile memory blocks, and FIG. 9 is an embodiment in which the semiconductor memory device of the present invention is applied to a memory module. It is. 2... Main memory, 4... Data line address direction, 6
... Word line address direction, 8.10... Word line defective. 8', 10'...Good word line selected at the same time as word line defect, 12...Data line defect, 12'...
...A good data line is selected at the same time as a defective data line. 14.14'... Defective storage unit, 18.20... Spare memory, 22 ax~22 a-, 22bt~22
bn. 22 as~22 cn-changeover switch SW t”
'S W n terminals, 26a, 26b, 26c, 28
a, 28b. 28c, 28d...Failure bit, 30...Data portion of word line defect detection signal, 32...Data portion of word line defect position signal, 34...Data portion of data line defect detection signal, 36.・Data part of data line defective position signal,
40...Memory block chip of main memory. 50...Priority determination circuit, 60...Associative memory cell section. 62...Data part of word line defect detection signal, 64...
- Data portion of word line defective position signal, 70... Control circuit, 72... Control signal for spare memory 18, 74...
Control signal for the spare memory 20, 100, 100'... input/output switching circuit, 102... input/output signal terminal of the main memory, 104, 114... input/output signal terminal of the spare memory,
106a...Word line defect detection signal, 106b...
Word line defective position signal, 106c... Data line defective detection signal, 106d... Data line defective position signal, 108
...External input/output signal, 110...External address signal, 112...External control signal, 120, 120'...
Decoder circuit, 300... Buffer circuit, 302...
- Input signal line of buffer circuit, 304... Output signal line of buffer circuit, Wl, Wk... Defective word line of memory block chip, Di, Dk... Defective data line of memory block chip, wl, wk ...Spare word line,
di, dk...Spare data line, SWI~SV□s w
t'~s w, 1'... Switch number for switching input/output terminals! Concave position 2 Diagram [Ward child Japanese and Ayu use reserve rejection [Tenita Sakuhama 1'fl possession 1 dispute 1su] Ne concave No. 6 Diagram No. Concave number? national territory

Claims (1)

[Claims] 1. A semiconductor memory device comprising: (1) a main memory that is a set of memories in which a predetermined memory cell is selected from a plurality of memory cells in response to an address signal; (2) the above-mentioned memory cell; a spare memory for relieving a defect in the main memory by being supplied with an address signal; (3) a defective memory section to which the address signal is supplied and storing a defect in the main memory; A semiconductor memory device comprising: an input/output switching circuit that switches the input/output signal terminal of the main memory to the input/output signal terminal of the second spare memory based on information of the defective storage section. 2. The semiconductor memory device according to claim 1, wherein the main memory, the spare memory, and the defective storage section are operated in parallel by the address signal. 3. The semiconductor memory device according to claim 1 or 2, wherein a defect detection signal indicating whether or not the main memory is defective and a defective position signal indicating a defective location of the main memory are written in the defective storage section. A semiconductor memory device characterized by: 4. The semiconductor memory device according to claim 1, wherein the switching operation of the input/output switching circuit is controlled by the defect detection signal and the defect location signal from the defect storage section. A semiconductor memory device characterized by: 5. A semiconductor memory device: (1) A memory having a plurality of memory cells, in which a predetermined memory cell is selected from the plurality of memory cells in response to a word line address signal and a data line address signal. (2) a first spare memory for relieving a word line defect in the main memory by being supplied with the word line address signal and the data line address signal; (3) a second spare memory for relieving data line defects in the main memory by being supplied with the word line address signal and the data line address signal; (4) the word line address; a first defect storage section to which the signal and the data line address signal are supplied and which stores word line defects of the main memory; (5) to which the word line address signal and the data line address signal are supplied; and (6) input/output signal terminals of the main memory based on information from at least one of the first and second defective storage sections. A semiconductor memory device comprising: an input/output switching circuit for switching the input/output signal terminal to either the input/output signal terminal of the first or second spare memory. 6. The semiconductor memory device according to claim 5, wherein the main memory, the first and second spare memories, and the first and second
A semiconductor memory device characterized in that the defective memory section of is operated in parallel by the word line address signal and the data line address signal. 7. The semiconductor memory device according to claim 5 or 6, wherein a spare word line of the first spare memory is connected to a plurality of addresses of the first defective storage section determined by the word line address signal. A word line defect detection signal indicating the presence or absence of a defective word line for selecting an input/output signal terminal of the spare memory for selecting a defective main memory, and a word line defect position signal indicating the position of the input/output signal terminal of the defective main memory are written; A plurality of addresses of the second defective memory section determined by the data line address signal are used to select input/output signal terminals of the spare memory for selecting a spare data line of the second spare memory. A semiconductor memory device characterized in that a data line defect detection signal indicating the presence or absence of a data line defect and a data line defect position signal indicating the position of an input/output signal terminal of the defective main memory are written. 8. The semiconductor memory device according to claim 7, wherein when the word line defect detection signal and the word line defect position signal are generated from the output of the first defect storage section, the first
selects an input/output signal terminal of a spare memory of the first spare memory, and selects at least one spare memory cell from the plurality of spare memory cells of the first spare memory in response to the word line address signal and the data line address signal. As a result, when the defect related to the word line of the main memory is relieved and the data line defect detection signal and the data line defect position signal are generated from the output of the second defect storage section, Select the input/output signal terminal and
At least one spare memory cell is selected from a plurality of spare memory cells of the spare memory in response to the word line address signal and the data line address signal, and as a result, a defect related to the data line of the main memory is relieved. A semiconductor memory device characterized by: 9. In the semiconductor memory device according to claim 5, when the word line address and the data line address of the main memory are the same address and the same bit is to be relieved, the word line address is preferentially rescued. A semiconductor memory device characterized by: 10. The semiconductor memory device according to any one of claims 5 to 9, characterized in that the first and second defective storage sections are constituted by semiconductor memory blocks of multi-bit output format. semiconductor memory device. 11. The semiconductor memory device according to any one of claims 5 to 9, wherein the semiconductor memory device is configured to repair either the word line defect or the data line defect. A semiconductor memory device characterized by: 12. The semiconductor memory device according to any one of claims 5 to 9, wherein the first and second defective memory sections include an associative memory cell section for detecting coincidence of defective addresses, and a word line defect detection signal. A semiconductor memory device comprising an associative memory device comprising at least a word line defective position signal, a data line defective detection signal, and a data line defective position signal. 13. A defect relief method using a semiconductor memory device according to claim 8, wherein a plurality of addresses of the first defective memory section determined by the word line address signal are set in the first spare memory. Write a word line defect detection signal and a word line defect position signal for selecting an input/output signal terminal, and write a word line defect detection signal and a word line defect position signal to a plurality of addresses of the defect storage section of the second data line defect determined by the data line address signal. , a first step of writing a data line defect detection signal and a data line defect position signal for selecting the input/output signal terminal of the second spare memory, and from the output of the first defect storage section of the word line defect. When the word line defect detection signal and the word line defect location signal are generated, at least one spare memory cell from the plurality of spare memory cells of the first spare memory is connected to the word line address signal and the data line address signal. As a result, the defect related to the word line of the main memory is relieved, and the data line defect detection signal and the data line defect location signal are generated from the output of the second defect storage section of the data line defect. In the case where the data in the main memory is selected, at least one spare memory cell is selected from the plurality of spare memory cells of the second spare memory in response to the data line address signal and the word line address signal. and a second step of relieving a defect related to a line. 4. The defect relief method according to claim 13, characterized in that when the word line address and the data line address are the same address and the same bit is to be relieved, the word line address is preferentially relieved. . 15. The defect relief method according to claim 13, wherein the first and second defective memory sections are constituted by semiconductor memory blocks of multi-bit output format. 16. The defect relief method according to claim 13, characterized in that the defect relief method is configured to relieve either the word line defect or the data line defect. . 17. The defect relief method according to claim 13, wherein the first and second defective memory sections include an associative memory cell section for detecting coincidence of defective addresses, a word line defect detection signal, a word line defect position signal, and data. 1. A defect relief method comprising an associative memory device comprising at least a line defect detection signal and a data line defect position signal. 18. The first and second defective memory sections are electrically written,
It consists of either EEPROM type memory cells that can be electrically erased, EPROM type memory cells that can be written to electrically and erased using ultraviolet light, phase ROM type memory cells, or SRAM type memory cells that are backed up by batteries. 6. A semiconductor memory device according to claim 5, characterized in that: 19. The semiconductor memory device according to claim 5, further comprising a buffer circuit capable of writing to input/output signal terminals of the first and second defective storage sections. 20. The semiconductor memory device according to claim 5, further comprising a control circuit for controlling write control signals for the first and second spare memories. 21. The semiconductor memory device according to claim 5, wherein the configuration memory of the main memory and the first and second spare memories have the same configuration. 22. The semiconductor memory device according to claim 5, wherein the main memory, the first and second spare memories, the first and second defective storage sections, and the input/output switching circuit are made of at least the same semiconductor. A semiconductor memory device characterized in that it is provided on a base.