JPH03149862A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03149862A JPH03149862A JP1289114A JP28911489A JPH03149862A JP H03149862 A JPH03149862 A JP H03149862A JP 1289114 A JP1289114 A JP 1289114A JP 28911489 A JP28911489 A JP 28911489A JP H03149862 A JPH03149862 A JP H03149862A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- silicon
- chip
- mold resin
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 239000011347 resin Substances 0.000 claims abstract description 36
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims abstract description 4
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000000465 moulding Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 10
- 238000010438 heat treatment Methods 0.000 abstract description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 10
- 230000001070 adhesive effect Effects 0.000 description 10
- 239000003822 epoxy resin Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 229920000647 polyepoxide Polymers 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 150000003377 silicon compounds Chemical class 0.000 description 2
- 241000287828 Gallus gallus Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Abstract
Description
【発明の詳細な説明】
［１ｍ要］
リードフレームのグイパッドにＩＣチップをマウントし
、樹脂でモールドした半導体装置に関し、耐湿性の優れ
た半導体装置を提供することを目的とし、
グイパッドと、該ダイパッドの表面上にマウントされた
シリコン製ＩＣチップと、該チップ表面に設けられたボ
ンディングパッドとボンディングワイヤを介して接続さ
れるリードと、該ダイパッドの裏面をコートするシリコ
ン系の半導体ないし金属の膜と、該ＩＣチップ、該ダイ
パッド、該シリコン系の半導体ないし金属の膜、該ボン
ディングワイヤおよび該リードの一部をモールドするモ
ールド樹脂とを有するように構成する。[Detailed description of the invention] [Requires 1 m] The purpose of this invention is to provide a semiconductor device with excellent moisture resistance in which an IC chip is mounted on a lead frame and molded with resin. A silicon IC chip mounted on the surface of the chip, a lead connected to a bonding pad provided on the surface of the chip via a bonding wire, and a silicon-based semiconductor or metal film coating the back surface of the die pad. , the IC chip, the die pad, the silicon-based semiconductor or metal film, the bonding wire, and a molding resin for molding a part of the lead.
［産業上の利用分野】
本発明は半導体装置に関し、特にリードフレームのダイ
パッドにＩＣチッ１をマウントし、樹脂でモールドした
半導体装置に関する。[Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which an IC chip 1 is mounted on a die pad of a lead frame and molded with resin.
［従来の技術］ 第２図（Ａ）〜（Ｄ）に従来の技術を示す。[Conventional technology] A conventional technique is shown in FIGS. 2(A) to 2(D).
第２図（Ａ）はエポキシ樹脂にモールドした半導体集積
回路装置を示す、リードフレームのダイパッド５１の上
に半導体チッ１５２がダイス付けされており、半導体チ
ッ１５２上のボンディングパッドとリードフレームのリ
ード５７とがボンディングワイヤ５８によって接続され
ている。半導体チッ１５２、ダイパッド５１−ボンディ
ングワイヤ５８を含む構造体はエポキシ系モールド樹脂
５６にモールドされている。モールド樹脂５６は吸湿性
があるので、表面がろ水分を吸収する。モールド樹脂５
６に吸収された水分は、ダイパッド裏面５９に到達する
。モールド樹脂５６は、半導体チップ５２に対しては強
い接着力を示すが、ダイパッド５１に対しては弱い接着
力しか示さないので、ダイパッド裏面に水分が集まりや
すい。FIG. 2(A) shows a semiconductor integrated circuit device molded in epoxy resin, in which a semiconductor chip 152 is diced on a die pad 51 of a lead frame, and the bonding pad on the semiconductor chip 152 and the lead 57 of the lead frame. are connected by a bonding wire 58. A structure including the semiconductor chip 152, die pad 51 and bonding wires 58 is molded in an epoxy mold resin 56. Since the mold resin 56 is hygroscopic, its surface absorbs moisture. mold resin 5
The moisture absorbed by the die pad 6 reaches the back surface 59 of the die pad. The mold resin 56 exhibits a strong adhesive force to the semiconductor chip 52, but only a weak adhesive force to the die pad 51, so that moisture tends to collect on the back surface of the die pad.
第２図（Ｂ）は、ハンダ実装のプロセスにおいて−ＩＣ
パッケージないしはリードがハンダ液に浸され高温にな
ると、ダイパッド５１裏面に集まった水分が蒸発し、気
泡６０を作る。ｍ度の上昇と共に気泡６０は圧力を上昇
させ、体積を増加させる。このように膨張した水蒸気６
０はダイパッド裏面とモールド樹脂５６とを剥離させる
。Figure 2 (B) shows -IC in the solder mounting process.
When the package or the leads are immersed in the solder liquid and the temperature becomes high, the moisture collected on the back surface of the die pad 51 evaporates, forming bubbles 60. With an increase in m degrees, the bubble 60 increases its pressure and volume. Water vapor expanded in this way 6
0 causes the back surface of the die pad and the mold resin 56 to be peeled off.
膨張する力が強ければ、剥離はさらに進んで、第２図（
Ｃ）に示すように、グイバッド５１真面の全面でモール
ド樹脂５６は剥離する。このような状態になった時に、
モールド樹脂５６において最も応力が強く働くのは、ダ
イパッド５１の端部においてである。If the expansion force is strong, the peeling will progress further, as shown in Figure 2 (
As shown in C), the mold resin 56 is peeled off from the entire surface directly in front of the Guibad 51. When you are in a situation like this,
The strongest stress acts on the mold resin 56 at the end of the die pad 51.
モールド樹脂５６が応力に耐えきれなくなると、第２図
（Ｄ）に示すように、ダイパッド５１端部よりクラック
６２が発生する。クラックがモールド樹脂５６の表面ま
で達すると、クラックを介して圧力のかかった水蒸気６
１は外部に逃げるので、モールド樹脂５６は元の形態に
戻る。但し、クラックは修復しないので、クラック６２
に沿って水分の侵入する経路が残る。When the mold resin 56 cannot withstand the stress, a crack 62 occurs from the end of the die pad 51, as shown in FIG. 2(D). When the crack reaches the surface of the mold resin 56, pressured water vapor 6 flows through the crack.
1 escapes to the outside, so the mold resin 56 returns to its original form. However, cracks cannot be repaired, so crack 62
A path remains along which moisture can enter.
［発明が解決しようとするＩＮ！ｆｉ］以上説明した従
来の技術によれば、モールド樹脂が吸収する水分によっ
て、ハンダ液ディッ１等により水分が気化する温度に半
導体装置を加熱すると、パッケージ割れ等の事故が発生
した。[Invention tries to solve IN! [fi] According to the conventional technology described above, when a semiconductor device is heated to a temperature at which the moisture absorbed by the molding resin is vaporized by the solder liquid dip 1 or the like, accidents such as package cracking occur.
本発明の目的は、耐湿性の優れた半導体装置を提供する
ことである。An object of the present invention is to provide a semiconductor device with excellent moisture resistance.
本発明の他の目的は、ハンダ実装等の加熱工程を経ても
モールド樹脂が吸収する水分によって問題が生じない半
導体装置を提供量ることである。Another object of the present invention is to provide a semiconductor device that does not cause problems due to moisture absorbed by the molding resin even after a heating process such as solder mounting.
［課題を解決するための手段１
第１図は本発明の原理説明図である。シリコンのＩＣチ
ップ６はリードフレーム４のダイパッド２の表面上にマ
ウントされる。ＩＣチップ６のボンディングパツドフは
ボンディングワイヤ８によってリードフレーム４のリー
ド３と接続される。[Means for Solving the Problems 1] FIG. 1 is a diagram illustrating the principle of the present invention. A silicon IC chip 6 is mounted on the surface of the die pad 2 of the lead frame 4. The bonding pads of the IC chip 6 are connected to the leads 3 of the lead frame 4 by bonding wires 8.
ダイパッド２の裏面にはシリコン系半導体ないし金属の
１１５が設けられている。シリコン系の半導体ないしは
金属はシリコンまたはシリコン化合物であり、シリコン
は好ましくは、多結晶シリコンまたはアモルファスシリ
コンであり、シリコン化合物は好ましくは高融点金属シ
リサイド、より好ましくはタングステンシリサイド、モ
リブデンシリサイド、チタンシリサイドである。On the back surface of the die pad 2, a silicon-based semiconductor or metal 115 is provided. The silicon-based semiconductor or metal is silicon or a silicon compound, silicon is preferably polycrystalline silicon or amorphous silicon, and the silicon compound is preferably a high melting point metal silicide, more preferably tungsten silicide, molybdenum silicide, or titanium silicide. be.
［作用］
ＩＣチップ６はモールド樹脂９との馴染みがよく、モー
ルド樹脂９と強く接着する。このため、モールド樹脂９
とＩＣチップ６との界面には水分が入り込みにくい、ダ
イパッド２は銅、４２アロイ（４２％Ｎｊ＋残部Ｆｅ）
等の金属で構成され、モールド樹Ｎ９との馴染みが悪い
、−のダイパッド２とモールド樹脂９との接着力は、Ｉ
Ｃチッ１６とモールド樹脂９との接着力の１７２０〜１
／３０程度しかない、このため、裸のダイパッド２がモ
ールド樹脂９と接触すると、その界面は接着力が弱いの
で、水分が侵入し溜まりやすい、ハンダ実装の際に生じ
たクラック等の事故は、このダイパッドとモールド樹脂
との界面に溜まる水分が主な原因である。ダイパッド２
裏面にシリコン系半導体ないし金属の膜５を設けると、
モールド樹脂９はこのシリコン系半導体ないし金属の膜
５と接着することになる。モールド樹脂９とシリコン系
半導体ないし金属のＭ５の接着力は、モールド樹脂とダ
イパッドの接着力より強くなるので、その界面への水分
の侵入が低減する。また、僅かに水分の侵入しーハンダ
実装等の際に気化しても、接着力が強いので、ダイパッ
ド２裏面からモールド樹脂９が剥離することが低減する
。[Function] The IC chip 6 is compatible with the mold resin 9 and strongly adheres to the mold resin 9. For this reason, mold resin 9
Moisture does not easily enter the interface between the die pad 2 and the IC chip 6. The die pad 2 is made of copper and 42 alloy (42% Nj + balance Fe).
The adhesion force between the mold resin 9 and the - die pad 2, which is made of metal such as metal and has poor compatibility with the mold resin N9, is I
1720 to 1 of the adhesive force between the C chip 16 and the mold resin 9
For this reason, when the bare die pad 2 comes into contact with the mold resin 9, the adhesive force at the interface is weak, so moisture easily enters and accumulates, and accidents such as cracks that occur during solder mounting can be prevented. The main cause is moisture that accumulates at the interface between the die pad and the mold resin. die pad 2
When a silicon-based semiconductor or metal film 5 is provided on the back surface,
The mold resin 9 is bonded to this silicon-based semiconductor or metal film 5. Since the adhesive force between the mold resin 9 and the silicon semiconductor or metal M5 is stronger than the adhesive force between the mold resin and the die pad, the intrusion of moisture into the interface is reduced. Further, even if a slight amount of moisture intrudes and evaporates during solder mounting, etc., the adhesive force is strong, so peeling of the mold resin 9 from the back surface of the die pad 2 is reduced.
シリコン系半導体ないし金属として、多結晶シリコン、
アモルファスシリコン、タングステンシリサイド、モリ
ブデンシリサイド、チタンシリサイドの１種以上を用い
ると、モールド樹脂とダイパッドとの間に十分強い接着
力を得ることができる。As silicon-based semiconductors or metals, polycrystalline silicon,
By using one or more of amorphous silicon, tungsten silicide, molybdenum silicide, and titanium silicide, a sufficiently strong adhesive force can be obtained between the mold resin and the die pad.
特に、アモルファスシリコンまたは多結晶シリコンをダ
イパッド２の裏面にコートした場合は、ダイパッド表面
側のＩＣチッ１６とモールド樹脂９との接着力と、ダイ
バブト裏面のシリコン膜５とモールド樹脂９との接着力
とのバランスがよい。In particular, when amorphous silicon or polycrystalline silicon is coated on the back surface of the die pad 2, the adhesive force between the IC chip 16 on the front surface side of the die pad and the mold resin 9, and the adhesive force between the silicon film 5 and the mold resin 9 on the back surface of the die pad. Good balance with.
［実施例］
第３図に本発明の実施例による半導体装置の断面ｍ造を
示す。[Embodiment] FIG. 3 shows a cross-sectional structure of a semiconductor device according to an embodiment of the present invention.
１Ｍ−ＤＲＡＭ等の集積回路を形成し、ＳｉＮ、Ｓｉ０
２等の力バー膜を設けたシリコンのＩＣチップ１６が銅
（Ｃｕ１４２アロイ（４２％Ｎｉ＋残部ｒｅ）等で形成
されたダイパッド１２の上にマウントされている。ＩＣ
チツプ１６上のボンディングパッドとリード１３との問
はＡｕ Ｓ Ａ費、Ｃｕ等 で形成されたボンディン
グワイヤ１８にって接続される。ダイパッド１２とリー
ド１３とは同一材料で構成され、リードフレーム１４を
構成している。このリードフレーム１４の裏面上にはア
モルファスシリコン膜１５がコートされている。ＩＣチ
ップ１６、それをマウントしたダイパッド１２およびボ
ンディングワイヤ１８をモールドしてエポキシ樹脂１９
がモールド体を構成する。エポキシ樹脂１９はＩＣチッ
プ１６に対しても、アモルファスシリコン膜１５に対し
ても強い接着力を発揮する。従って、エポキシ樹脂１９
が水分を吸収しても、ハンダブイラ１等の加熱工程の際
エポキシ樹脂１９がダイパッド１２やＩＣチップ１６か
ら剥離することが少ない、このため、ハンダ実装等の際
におけるクラック発生が低減できる。また、リードフレ
ーム１４の表面側には何の加工も行わないので、ＩＣチ
ップ１６やボンディングワイヤ１８等に悪い影響を与え
ることはない。Forms integrated circuits such as 1M-DRAM, SiN, Si0
A silicon IC chip 16 provided with a force bar film of grade 2 is mounted on a die pad 12 made of copper (Cu142 alloy (42% Ni + balance re) or the like.
The bonding pads on the chip 16 and the leads 13 are connected by bonding wires 18 made of Au SA, Cu, or the like. The die pad 12 and the leads 13 are made of the same material and constitute a lead frame 14. The back surface of this lead frame 14 is coated with an amorphous silicon film 15. The IC chip 16, the die pad 12 on which it is mounted, and the bonding wires 18 are molded and coated with epoxy resin 19.
constitutes the mold body. The epoxy resin 19 exhibits strong adhesion to both the IC chip 16 and the amorphous silicon film 15. Therefore, epoxy resin 19
Even if it absorbs moisture, the epoxy resin 19 is less likely to peel off from the die pad 12 or the IC chip 16 during the heating process using the solder broiler 1 or the like, and therefore, the occurrence of cracks during solder mounting or the like can be reduced. Further, since no processing is performed on the front surface side of the lead frame 14, there is no adverse effect on the IC chip 16, bonding wire 18, etc.
第４図（Ａ）〜（Ｄ）は、第３図に示したような半導体
装置を製造する製造方法を説明する。FIGS. 4A to 4D illustrate a manufacturing method for manufacturing a semiconductor device as shown in FIG.
第４図（Ａ）はリードフレームの裏面にアモルファスシ
リコン膜をコートするための１ラズマＣＶＤ工程を示す
、上部電極２１と下部電極２２が対向するプラズマＣＶ
Ｄ装置内の下部電極２２上にリードフレーム１４を伏せ
て設置する。１ラズマＣＶＤ装置内を予備排気した後、
反応ガスとしてＳｉＨ＋を２００８ＣＣＭ導入し、圧力
を約Ｉ Ｔｏｒｒに保つ、反応温度を約３００℃に設定
し、１３゜５６ ＭＨｚの高周波電源２３から上下ｔｌ
ｊ２１．２２間に約３００Ｗの高周波電力を供給し、プ
ラズマを発生させる。発生したプラズマからリードフレ
ーム１４の露出した裏面上にアモルファスシリコン（ａ
−Ｓｉ）膜が堆積する。このようにして、リードフレー
ム１４裏面および側面上に約５０００λ〜１μｍのアモ
ルファスＳｉ膜１５を堆積する。なお、リードフレーム
１４が鏡面であれば、アモルファスＳｉ膜は約１０００
Å以上の厚さを有すればよい、なお、プロセスのパラメ
ータは適宜変更する。FIG. 4(A) shows a plasma CVD process in which an upper electrode 21 and a lower electrode 22 face each other, showing one plasma CVD process for coating an amorphous silicon film on the back surface of a lead frame.
The lead frame 14 is placed face down on the lower electrode 22 in the device D. 1 After preliminary evacuation of the inside of the plasma CVD equipment,
2008 CCM of SiH+ was introduced as a reaction gas, the pressure was kept at about I Torr, the reaction temperature was set at about 300°C, and the upper and lower tl were supplied from a 13°56 MHz high frequency power source 23
Approximately 300 W of high frequency power is supplied between J21 and J22 to generate plasma. Amorphous silicon (a
-Si) film is deposited. In this way, an amorphous Si film 15 of about 5000λ to 1 μm is deposited on the back and side surfaces of the lead frame 14. Note that if the lead frame 14 has a mirror surface, the amorphous Si film has a thickness of about 1000
It suffices to have a thickness of .ANG. or more, and process parameters may be changed as appropriate.
第４図（Ｂ）はこのようにして得たアモルファスＳｔを
コートしたリードフレームを示す、すなわち、リードフ
レーム１４はダイパッド１２とリード１３を有し、その
裏面上にアモルファスＳｌ膜１５が形成されている。FIG. 4(B) shows the lead frame coated with amorphous St obtained in this way. That is, the lead frame 14 has a die pad 12 and leads 13, and an amorphous Sl film 15 is formed on the back surface of the lead frame 14. There is.
第４図（Ｃ）はダイボンディングおよびワイヤボンディ
ングの工程を示す、ＩＣチップ１６の裏面をダイパッド
１２の表面上に銀エポキシ等の有機系ダイス付は材料に
よってダイス付けして、グイボンディングを行う、次に
、ＩＣチッ１１６の表面上のボンディングパッドをボン
ディングワイヤ１８によってリード１３と接続してワイ
ヤボンディングを行う。FIG. 4(C) shows the process of die bonding and wire bonding, in which the back side of the IC chip 16 is attached to the front surface of the die pad 12 using an organic material such as silver epoxy, and bonding is performed. Next, wire bonding is performed by connecting the bonding pads on the surface of the IC chip 116 to the leads 13 using the bonding wires 18.
次に、第４図（Ｄ）に示すように、ＩＣチップ１６、ダ
イパッド１２、ボンディングワイヤ１８を取り囲むよう
にエポキシ樹脂１９のトランスファモールドを行う、エ
ポキシ樹脂１９はＩＣチップ１６、アモルファスＳｉｌ
［１５に強く接着する。Next, as shown in FIG. 4(D), transfer molding of epoxy resin 19 is performed so as to surround the IC chip 16, die pad 12, and bonding wire 18.
[Adhere strongly to 15.
次に、両側に突き出すリード１３を整形する。図示の場
合、リード１３は内側に曲げられて表面実装を行う形状
にされる。Next, the leads 13 protruding from both sides are shaped. In the illustrated case, the leads 13 are bent inward to form a shape for surface mounting.
なお、リード１３上のアモルファスシリコン膜１５は必
ずしも必要ない、図示の構成の場合、リード１３上のア
モルファスシリコン膜によって特に差し障りは生じない
が、所望に応じてエッチングで除去してもよい、たとえ
ば、リード１３を外側に曲げた表面実装型とする場合に
は、ハンダ付けすべき表面をアモルファスシリコン膜１
５が覆うことになるので、少なくとも先端部分のアモル
ファスシリコン膜を除去してリード１３の金属表面を露
出させる。Note that the amorphous silicon film 15 on the lead 13 is not necessarily necessary, and in the case of the illustrated configuration, the amorphous silicon film on the lead 13 does not cause any particular trouble, but it may be removed by etching if desired. For example, When using a surface mount type with the leads 13 bent outward, the surface to be soldered is covered with an amorphous silicon film 1.
5, the amorphous silicon film at least at the tip portion is removed to expose the metal surface of the lead 13.
このように形成した半導体装置を、温度８５℃、湿度８
５％の加速条件下で２４時間吸湿させ、その後、ハンダ
ディッグエ稈を行ってクラック発生等の調査を行った。The semiconductor device thus formed was heated at a temperature of 85°C and a humidity of 8°C.
Moisture was absorbed for 24 hours under 5% acceleration conditions, and then soldering was conducted to investigate the occurrence of cracks, etc.
従来のものと比べ、クラック防止に効果があることが判
った。従って、耐湿性を向上した半導体装置が得られる
ことが判った。It was found to be more effective in preventing cracks than conventional products. Therefore, it has been found that a semiconductor device with improved moisture resistance can be obtained.
以上、実施例に沿って説明したが、本発明はこれらにａ
限されるものではない、たとえば、種々の変更、改良、
組み合わせ等が可能なことは当業者に自明であろう。Although the above has been explained along with the embodiments, the present invention is based on a
For example, without limitation, various modifications, improvements,
It will be obvious to those skilled in the art that combinations and the like are possible.
［発明の効果］
以上説明したように、本発明によれば、モールド樹脂が
吸収する水分によって発生する事故を低減することので
きる半導体装置が得られる。[Effects of the Invention] As described above, according to the present invention, a semiconductor device can be obtained that can reduce accidents caused by moisture absorbed by a molding resin.
ハンダディップ等の加熱工程を行っても、モールド樹脂
が吸収した水分によってクラック等の事故を発生するこ
とが防止できる。Even if a heating process such as solder dipping is performed, it is possible to prevent accidents such as cracks from occurring due to moisture absorbed by the mold resin.
第１図は本発明の原理説明図、
第２図（Ａ）〜（Ｄ）は従来の技術を示す断面図、
第３図は本発明の実施例による半ｌｉ＃装置を概略的に
示す断面図、
第４図（Ａ）〜（Ｄ）は第３図に示すような半導体装ｌ
を製造する製造方法を説明する図であり、第４図（Ａ）
はプラズマＣＶＤ装置の概略斜視図、第４図（Ｂ）〜（
Ｄ）は製造工程を説明するための断面図である。
図において、
２ ダイパッド
３ リード
４ リードフレーム
５ Ｓｉ系半導体ないし金属の展６
ＩＣチップ
７ ボンディングパッド
８ ボンディングワイヤ
９ モールド樹脂
１２ ダイパッド
１３ リード
１４ リードフレーム
１５ アモルファスＳｔ膜
１６ ＩＣチップ
１８ ボンディングワイヤ
１９ エポキシ樹脂
２１ 上部をＳ
２２ 下部電極
２３ 高周波電源
１ ｌ ！本発明の原理説
明図
第１図
（Ｄ）クラツク発生
ｔフ損
実施例による半導体装置
第３図
（Ａ）プラズマＣＶＤ
製造方法
第４図（その１》
７１２１ρ
（８）ａ−Ｓｉ膜をコートしたリードフレーム（Ｃ）グ
イボンディングおよびワイヤボンディング（Ｄ）トラン
スファモールドおよびリード整形製造方法
第４図（その２）Fig. 1 is a diagram explaining the principle of the present invention, Figs. 2 (A) to (D) are cross-sectional views showing the conventional technology, and Fig. 3 is a cross-sectional view schematically showing a half-li# device according to an embodiment of the present invention. Figures 4(A) to 4(D) show the semiconductor device shown in Figure 3.
FIG. 4A is a diagram illustrating a manufacturing method for manufacturing
is a schematic perspective view of a plasma CVD apparatus, and FIGS. 4(B) to (
D) is a sectional view for explaining the manufacturing process. In the figure, 2 Die pad 3 Lead 4 Lead frame 5 Si-based semiconductor or metal layer 6
IC chip 7 Bonding pad 8 Bonding wire 9 Mold resin 12 Die pad 13 Lead 14 Lead frame 15 Amorphous St film 16 IC chip 18 Bonding wire 19 Epoxy resin 21 Upper part S 22 Lower electrode 23 High frequency power supply 1 l! Figure 1 (D) Semiconductor device according to an example of crack occurrence and loss Figure 3 (A) Plasma CVD manufacturing method Figure 4 (Part 1) 7121ρ (8) Coated with a-Si film Lead frame (C) Gui bonding and wire bonding (D) Transfer mold and lead shaping manufacturing method Figure 4 (Part 2)
Claims (2)
製ＩＣチップ（６）と、 該チップ表面に設けられたボンディングパッド（７）と
ボンディングワイヤ（８）を介して接続されるリード（
３）と、 該ダイパッド（２）の裏面をコートするシリコン系の半
導体ないし金属の膜（５）と、 該ＩＣチップ（６）、該ダイパッド（２）、該シリコン
系の半導体ないし金属の膜（５）、該ボンディングワイ
ヤ（８）および該リードの一部をモールドするモールド
樹脂（９）と を有する半導体装置。(1), a die pad (2), a silicon IC chip (6) mounted on the surface of the die pad (2), a bonding pad (7) and a bonding wire (8) provided on the surface of the chip. Leads connected through (
3), a silicon-based semiconductor or metal film (5) that coats the back surface of the die pad (2), the IC chip (6), the die pad (2), and the silicon-based semiconductor or metal film ( 5) A semiconductor device having the bonding wire (8) and a molding resin (9) for molding a part of the lead.
は、多結晶シリコン、アモルファスシリコン、タングス
テンシリサイド、モリブデンシリサイド、チタンシリサ
イドから選ばれた１種以上の材料で構成される請求項１
記載の半導体装置。(2), the silicon-based semiconductor or metal film (5)
Claim 1: is composed of one or more materials selected from polycrystalline silicon, amorphous silicon, tungsten silicide, molybdenum silicide, and titanium silicide.
The semiconductor device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1289114A JPH03149862A (en) | 1989-11-07 | 1989-11-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1289114A JPH03149862A (en) | 1989-11-07 | 1989-11-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03149862A true JPH03149862A (en) | 1991-06-26 |
Family
ID=17738966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1289114A Pending JPH03149862A (en) | 1989-11-07 | 1989-11-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03149862A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018098251A (en) * | 2016-12-08 | 2018-06-21 | 株式会社豊田中央研究所 | Semiconductor module and method for manufacturing the same |
-
1989
- 1989-11-07 JP JP1289114A patent/JPH03149862A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018098251A (en) * | 2016-12-08 | 2018-06-21 | 株式会社豊田中央研究所 | Semiconductor module and method for manufacturing the same |
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