JPH0314922Y2 - - Google Patents

Description

[Detailed description of the invention] This invention focuses on the fact that the excitation rush current contains a large amount of second harmonics, and the invention suppresses operation when the second harmonic content of the input current is high to prevent malfunctions in the excitation current. This invention relates to a ratio differential relay with two-harmonic suppression.

A general example of transformer protection is shown in FIG. In FIG. 6, 30 is a protected transformer;
1 and 32 are current transformers (referred to as CT) installed at both ends of the protected transformer, and 33 to 35 are transformer protection relays to which the present invention is applied. In transformer protection, changes in current due to the transformation ratio of the transformer (Iu and
change in the magnitude of Iu′) and change in current due to the winding configuration of the transformer (change in Iu and
Therefore, as shown in Figure 6, the wiring method is changed using CT and the CT ratio is selected so that the differential current becomes zero. However, it is known that when a transformer is turned on with no load, a magnetizing inrush current flows through the transformer, and this current is, for example, the 6th inrush current.
If Iu′, Iv′, and Iw′ do not flow, it becomes a differential current, that is, the operating current of the relay, and some countermeasure is required to prevent the transformer protection relay from operating. Become. The most common one is a ratio differential relay with second harmonic suppression.
The present invention relates to this improvement.

Conventionally, a circuit system as shown in FIG. 1 has been commonly used as a structure of a relay aimed at protecting this type of transformer. That is, in FIG. 1, 1 is a suppression input terminal, 2 is a rectifier circuit for the input signal, and 3 is a smoothing circuit for smoothing the rectified output, and these constitute a suppression circuit 21 that outputs a suppression output. Further, 4 is a differential input terminal, 5 is a derivation circuit that derives the fundamental wave component from the input terminal, 6 is a rectifier circuit that rectifies the fundamental wave component, and 7 is a smoothing circuit that smoothes the rectified output. , 6, and 7 form a differential circuit 22 that outputs a fundamental wave output. Furthermore, 8 is the differential input terminal 4
9 is a rectifier circuit that rectifies the second harmonic component, and 10 is a smoothing circuit that smoothes the rectified output. , 10 constitute a second harmonic suppression circuit 23. These suppression circuit 21, differential circuit 22, and second harmonic suppression circuit 2
Each output of 3 is connected to the first and second comparator circuits 11 and 1, respectively.
2, operation time limit circuits 13 and 14 and return time limit circuits 15 and 16, and an AND circuit 17 outputting a final operation signal. Also, V _A , V _B , V _C , V _D ,
V _E , V _F , V _G , and V _H are the output waveforms of the main parts, respectively.

Note that FIG. 2 shows the second circuit in the conventional circuit example of FIG.
FIG. 3 shows the waveforms of various parts when there are many second harmonics. The waveforms of each part have many characteristics described for explanation purposes. In the figure, V _A ,
The dashed lines for V _B and V _C indicate the instantaneous values before smoothing, and the dashed-dotted lines for V _D and V _E indicate the case of limit non-operation.

Below, based on the conventional example shown in Fig. 1, Figs. 2 and 3 will be explained.
The operation will be explained with reference to the waveforms in the figure. First, when there is an input to the suppression input terminal 1 and the differential input terminal 4, the suppression circuit 21, the differential circuit 22, and the second harmonic suppression circuit 23 are input as shown in V _A , V _B , and V _C in FIG. An output waveform similar to that appears. Each of the above circuits has smoothing circuits 3, 7 and 10, but the detailed waveforms usually include ripples.
The first and second comparison circuits 11 and 12 are configured to compare the outputs of the differential circuit 22 and the suppression circuit 21, or the differential circuit 22 and the second harmonic suppression circuit 23, respectively. Then, the output V _B of the differential circuit 22 is
When the output V _A of the suppression circuit 21 is greater than the output V A of the first comparison circuit _{11 , the output signal V D of} the differential circuit 22 is outputted from the second harmonic suppression circuit 23 .
The second comparator circuit 12 generates an output signal V _E when the output signal V _C is greater than the output V C of the second comparator circuit 12 . However, these comparative waveforms V _A , V _B , and V _C contain ripples as shown in Figure 2, so the magnitudes of the compared V _A and V _B or V _B and V _C are almost the same. Near the same level, the output conditions (V _A < V _B , V _C < V _B ) of the first and second comparator circuits 11 and 12 are not continuously satisfied and become intermittent. , and the outputs of the second comparison circuits 11 and 12 are rectangular waves. That is,
The ripple frequency is the same for V _A and V _B , but the amount of ripple is usually larger for V _A than for V _B , while for V _B
Since the ripple frequency of V _C is higher in V _C than in V _B , the outputs of the first and second comparison circuits become intermittent and become rectangular waves. Then, an operation time limit circuit 1 in which the pulse width of the rectangular wave is set in advance.
When the set time of 3 and 14 is exceeded, the operation time limit circuit 1
3 and 14 are output, and outputs are generated from return time limit circuits 15 and 16. The return time limit circuits 15 and 16 are
Once activated, even if the output of the operation time limit circuits 13, 14 is cut off, the operation continues for a certain period of time, and as a result, the pulse width of the pulse output from the operation time limit circuits 13, 14 is expanded. This return time limit circuit 1
The output signals 5 and 16 are ANDed by an AND circuit 17 to generate a final output signal.

It should be noted that the rectangular wave indicated by the dashed-dotted line in the output waveforms V _D and V _E shown in FIG.
This shows a case where the set time of 14 is not reached, that is, a case where the relay cannot operate. Further, the set times T ₁ and T ₂ of the operation time limit circuits 13 and 14 in the above explanation are given by the following. In other words, in a normal input waveform, the outputs of the suppression circuit 21 and the differential circuit 22 are in the same phase even for the same input.
The ripple response and the transient response are not necessarily the same, and therefore, in terms of dynamic characteristics, the output of the comparator circuit 11 may generate an output signal transiently. For example, smoothing circuits 3 and 7
When the latter smoothing constant becomes large due to the size relationship of the delay elements of
1, and conversely, if the smoothing constant of the latter differential circuit 22 is small, there is a possibility that an output will be generated even when the input is de-energized.
Therefore, the operation time limit circuit 13 is required to eliminate these malfunctions. However, since this time limit width differs depending on the nature of the input signal, a method of setting it experimentally has been used. Next, the second harmonic suppression circuit 23
The output relationship between and the differential circuit 22 is as follows:
In addition to consideration similar to the relationship between 1 and the differential circuit 22, the second harmonic derivation circuit 8 generally uses a bandpass filter circuit with high selectivity, so the output waveform changes due to this transient response. As shown in Figure 3, it is not uncommon for a larger output V _C to be produced than during steady input. Therefore, since the second comparator circuit 12 may transiently generate the output V _E , a set time T ₂ of the operation time limit circuit 14 is required to prevent this malfunction. In addition, in such a case, if the pulse width of the comparator circuit 12 exceeds the set time _T2 in the worst case, the first
It has become extremely important to determine the set time T ₁ of the operation time limit circuit 13 so that an AND circuit with the output side of the comparison circuit 11 is not established.
Note that generally, T ₂ is usually longer than the set time T ₁ .

Also, from the above, the relay operating time T is the transient response time + T ₂ .

As mentioned above, in the conventional second harmonic ratio differential relay circuit, since the operation time limit circuits 13 and 14 are present, the response is naturally slow, and the set times T ₁ and T of the operation time limit circuits 13 and 14 are ₂
The setting method also had the disadvantage that it was a qualitative work based on experience and experimentation, which required time and effort, and was not efficient or uniform.

Therefore, the present invention has been made to eliminate the above-mentioned drawbacks, and includes a suppression circuit and a first comparison circuit that compares the outputs of each instantaneous value level of the differential circuit, and a harmonic component including a ripple component. An AND circuit (AND circuit) is connected to the rear stage of the second comparison circuit that compares the instantaneous level outputs of the second harmonic suppression circuit and the differential circuit, and its output is To provide a ratio differential relay with a second harmonic suppression circuit operable with an operation time limit circuit having an operation time limit of at least 1/4 cycle of a fundamental component with a time limit width constrained by a first comparison circuit. The purpose is to

An embodiment of the present invention will be described below with reference to FIGS. 4 and 5. In the figure, the same reference numerals as in FIG. 1 indicate the same parts. In FIG. 4, 18 is an AND circuit, 19 is an operation time limit circuit, and 20 is a return time limit circuit. In addition, the smoothing circuit 1 in FIG.
0 is a smoothing circuit with a small time constant, unlike the conventional one, and therefore, the second harmonic component containing many ripple components is input to the second comparison circuit. In addition, Fig. 5 shows the waveforms V _A to V _E , V _K of the main parts shown in Fig. 4.
This is what is shown. In the figure, since the parts before the outputs of the first and second comparators 11 and 12 have already been mentioned in the description of the conventional circuit, their description will be omitted here. However, the second
The V _C input to the comparator circuit contains many ripple components. Therefore, the output waveform of the second comparator 12 has a frequency twice that of the output waveform of the first comparator 11 near the operating point.

First, when the second harmonic component is sufficiently small, the operation time is determined only by the output V _D of the first comparator 11, as shown by the solid lines V _D , V _E , and V _J in FIG. In other words, the constraint conditions for the setting time of the operation time limit circuit 19 are the same as those of the operation time limit circuit 1 of the conventional circuit.
This is the same as in case 3. In other words, the operating limit of the second comparator circuit 12 is that the period of the rectangular wave V _E is half of V _D as described above, so the operating limit of the operation time limit circuit 1
By setting the signal delay setting time T ₃ of 9 to be larger than the rectangular wave period of V _E (1/4 period of the basic waveform),
This will satisfy the time limit.

That is, according to the present invention, the set time T 3 of the operation time limit circuit 19 is set for output coordination between the first comparison circuit 11 on the suppression circuit side and the second comparison circuit 12 on the second harmonic suppression circuit side _. can be quantitatively given by 1/4 or more of the fundamental wave period. Therefore, the operating time T' of the relay is the sum of the time _T0 until V _D rises and the set time _T3 , and it is clear that T'<T compared to the conventional operating time T. be.
Note that the above explanation includes the smoothing circuits 3, 7, and 10 like the conventional circuit, but since the present invention basically measures the rectangular wave pulse width, the set time T ₃ is the same as the fundamental wave. The smoothing circuits 3, 7, and 10 are not particularly necessary unless the period is 1/2 or more. Therefore, by eliminating the smoothing circuit that functions as a delay element, the operating time can be further increased.

Therefore, according to the present invention, the output simultaneous conditions of the first and second comparison circuits that compare the instantaneous value level output signals of the suppression circuit without delay elements, the differential circuit, and the second harmonic suppression circuit, respectively. It consists of an AND circuit that outputs an AND circuit, an operation timer circuit that measures the output time, and a recovery timer circuit that holds the signal when the malfunction timer circuit outputs the signal, which simplifies the circuit configuration. Timing constraints are also reduced, and the operation time limit can be set quantitatively and uniformly, so there is a significant effect that a relay capable of high-speed operation can be provided at low cost. Furthermore, in the present invention, since the first and second comparator circuits each compare input signals at instantaneous value levels, there is an effect that higher speed operation can be obtained compared to the case where signals at effective value levels are handled.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a conventional relay circuit, Fig. 2 is a waveform diagram to explain the operation of Fig. 1, Fig. 3 is a waveform diagram of the main part showing other operating conditions, and Fig. 4 is a waveform diagram for explaining the operation of Fig. 1. 5 is a waveform diagram for explaining the operation of FIG. 4, and FIG. 6 is a circuit diagram showing a general example of transformer protection. Note that the same reference numerals in the figures indicate the same or corresponding parts. 1... Suppression input terminal, 21... Suppression circuit, 4...
... Differential input terminal, 22 ... Differential circuit, 11, 12
...First and second comparison circuits, 18...AND circuit, 19...Operation time limit circuit, 20...Return time limit circuit.

Claims (1)

[Scope of utility model registration request] a first comparison circuit that compares the instantaneous value level output of the full-wave rectified suppression circuit and the instantaneous value level output of the differential circuit and outputs an output when the output of the differential circuit becomes large; a second comparison circuit that compares an instantaneous value level output of a second harmonic suppression circuit including a ripple component with an instantaneous value level output of the differential circuit and outputs an output when the output of the differential circuit becomes large; , an AND circuit that outputs the output conditions of both the first and second comparison circuits, and an output time of the AND circuit that is at least 1/1/1 of the basic component with a time limit limited by the first comparison circuit. A second circuit comprising an operation time limit circuit that measures four cycles or more, and a return time limit circuit that holds the signal when the output of the operation time limit circuit is generated.
Ratio differential relay with harmonic suppression.