JPH03147101A - Control system with erroneous control prevention - Google Patents
Control system with erroneous control preventionInfo
- Publication number
- JPH03147101A JPH03147101A JP1286243A JP28624389A JPH03147101A JP H03147101 A JPH03147101 A JP H03147101A JP 1286243 A JP1286243 A JP 1286243A JP 28624389 A JP28624389 A JP 28624389A JP H03147101 A JPH03147101 A JP H03147101A
- Authority
- JP
- Japan
- Prior art keywords
- control
- package
- signal
- abnormality
- controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002265 prevention Effects 0.000 title description 3
- 230000005856 abnormality Effects 0.000 claims abstract description 22
- 230000002159 abnormal effect Effects 0.000 claims description 4
- 238000004092 self-diagnosis Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Safety Devices In Control Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は誤制御防止付き制御方式に関し、特に被制御パ
ッケージ群とこれを制御するパッケージとを搭載した制
御装置における誤制御防止付き制御方式に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a control method with prevention of erroneous control, and particularly relates to a control method with prevention of erroneous control in a control device equipped with a group of controlled packages and a package that controls the same. .
従来、この種の装置の制御方式は、制御パッケージの自
己診断手段を有し、警報を外部に発出する機能を有して
いるが、プロセッサの暴走等の制御パッケージの異常時
に制御パッケージの被制御パッケージ群への誤制御を防
止し、装置の主機能に影響を与えないようにする機能は
有していない。Conventionally, the control system for this type of device has a self-diagnosis means for the control package and a function to issue an alarm to the outside. It does not have a function to prevent erroneous control of the package group and prevent it from affecting the main functions of the device.
上述した従来の制御方式は、制御パッケージの自己診断
手段を有しているが、プロセッサの暴走等の制御パッケ
ージの異常時に制御パッケージが被制御パッケージ群を
誤制御し、装置の主機能が麻痺するのを防止できないと
いう問題点がある。The conventional control method described above has a self-diagnosis means for the control package, but when there is an abnormality in the control package such as a runaway of the processor, the control package incorrectly controls the group of controlled packages, paralyzing the main functions of the device. The problem is that it cannot be prevented.
本発明の制御方式は、制御用のプロセッサを搭載した制
御パッケージと、該制御パッケージが送出する制御信号
を伝達する制御バスと、前記制御パッケージの自己診断
手段で検出された該制御パッケージの異常を示す異常信
号を伝達する信号線と、前記制御パッケージに前記制御
バスおよび前記信号線を介して接続しており前記異常信
号の受信時に前記制御信号を無効にするゲート手段をそ
れぞれ有する少なくとも1個の被制御パッケージとを備
えている。The control method of the present invention includes a control package equipped with a control processor, a control bus for transmitting control signals sent by the control package, and an abnormality of the control package detected by a self-diagnosis means of the control package. at least one gate means connected to the control package via the control bus and the signal line for disabling the control signal when the abnormal signal is received; A controlled package is provided.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例のブロック図である。同図に
おいて、参照番号10は制御パッケージ、20は被制御
パッケージ、40は制御バス、50は制御パッケージ異
常伝達用の信号線、aは制御信号、bは制御パッケージ
異常信号をそれぞれ示す。制御パッケージ10は、制御
信号aと制御パッケージ異常信号すとを発蛙する。制御
バス40は、制御信号aを被制御パッケージ20に伝達
する。被制御パッケージ20は、制御信号aに応じて固
有の機能を果たす。信号線50は、制御パッケージ異常
信号すを被制御パッケージ20に伝達する。FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, reference number 10 is a control package, 20 is a controlled package, 40 is a control bus, 50 is a signal line for transmitting a control package error, a is a control signal, and b is a control package error signal, respectively. The control package 10 emits a control signal a and a control package abnormality signal. Control bus 40 transmits control signal a to controlled package 20 . The controlled package 20 performs a specific function depending on the control signal a. The signal line 50 transmits a control package abnormality signal to the controlled package 20.
第2図は制御パッケージ10の構成例を示すブロック図
である。参照番号11はプロセッサ、12はWDT (
ウォッチドッグタイマ)回路、CはWDTリセット信号
を示す。プロセッサ11は制御信号aを生成し、またW
DT回路12WDTリセット信号Cを発出する。WDT
回路12は〜VDTによりプロセッサ11の動作を監視
し、タイムアウト時には制御パッケージ異常信号すを発
出する。FIG. 2 is a block diagram showing an example of the configuration of the control package 10. As shown in FIG. Reference number 11 is a processor, 12 is a WDT (
watchdog timer) circuit, C indicates the WDT reset signal. Processor 11 generates control signal a and also W
DT circuit 12 issues WDT reset signal C. WDT
The circuit 12 monitors the operation of the processor 11 by VDT, and issues a control package abnormality signal upon timeout.
第3図は被制御パッケージ20の構成例を示すブロック
図である。参照番号21は制御信号aのゲート回路、2
2は制御パッケージ異常信号すの検出回路、23は被制
御回路20の固有の機能を果たす主回路、dはゲート制
御信号を示す。検出回路22は制御パッケージ異常信号
bt!−検出し、制御パッケージ異常信号すが有意のと
き、ゲート制御信号dをゲート回821に発出する。ゲ
ート回路21はゲート信号dが有意でないときには主回
路23に制御信号aを伝達し、ゲート信号dが有意のと
きにはゲートを閉じて主回路23に制御信号aが伝達さ
れないようにする。FIG. 3 is a block diagram showing an example of the configuration of the controlled package 20. As shown in FIG. Reference number 21 is a gate circuit for control signal a, 2
2 is a control package abnormality signal detection circuit, 23 is a main circuit that performs a specific function of the controlled circuit 20, and d is a gate control signal. The detection circuit 22 outputs a control package abnormality signal bt! - Detects and issues a gate control signal d to the gate circuit 821 when the control package abnormality signal is significant. The gate circuit 21 transmits the control signal a to the main circuit 23 when the gate signal d is not significant, and closes the gate to prevent the control signal a from being transmitted to the main circuit 23 when the gate signal d is significant.
したがって、制御パッケージ10が異常のとき、被制御
パッケージ20の群は制御を受けない このため、装置
の主機能を制御パッケージ10の異常発生以前の状態に
保ち、制御パッケージ10の異常が装置の主機能に影響
を与えないようにすることができる。Therefore, when the control package 10 is abnormal, the group of controlled packages 20 is not controlled. Therefore, the main function of the device is maintained in the state before the abnormality of the control package 10 occurred, and the main function of the device is This can be done without affecting functionality.
以上説明したように本発明は、制御パッケージの異常を
パッケージ群に伝達して各被制御パッケージでは制御パ
ッケージの異常時に制御信号を無効にすることにより、
プロセッサの暴走等の制御パッケージの異常時に制御パ
ッケージが被制御パッケージ群を誤制御することを防止
し、装置の主機能を制御パッケージ異常発生以前の状態
に保ち、制御パッケージ異常が装置の主機能に影響を与
えないようにできる効果がある。As explained above, the present invention transmits the abnormality of the control package to the package group, and disables the control signal in each controlled package when the control package is abnormal.
This prevents the control package from erroneously controlling a group of controlled packages in the event of a control package abnormality such as a runaway processor, keeps the main function of the device in the state before the control package abnormality, and prevents the control package from returning to the main function of the device when the control package abnormality occurs. There is an effect that can prevent it from affecting you.
第1図ないし第3図は本発明の実施例のブロック図であ
る。
10・・・制御パッケージ、20・・・被制御パッケー
ジ、40・・・制御バス、50・・・信号線、11・・
・プロセッサ、12・・・WDT(ウォッチドッグタイ
マ)回路、21・・・ゲート回路、22・・・検出回路
、23・主回路。1 through 3 are block diagrams of embodiments of the present invention. DESCRIPTION OF SYMBOLS 10... Control package, 20... Controlled package, 40... Control bus, 50... Signal line, 11...
- Processor, 12...WDT (watchdog timer) circuit, 21... Gate circuit, 22... Detection circuit, 23. Main circuit.
Claims (1)
御パッケージが送出する制御信号を伝達する制御バスと
、前記制御パッケージの自己診断手段で検出された該制
御パッケージの異常を示す異常信号を伝達する信号線と
、前記制御パッケージに前記制御バスおよび前記信号線
を介して接続しており前記異常信号の受信時に前記制御
信号を無効にするゲート手段をそれぞれ有する少なくと
も1個の被制御パッケージとを備えていることを特徴と
する誤制御防止付き制御方式。A control package equipped with a control processor, a control bus for transmitting control signals sent by the control package, and a signal for transmitting an abnormality signal indicating an abnormality in the control package detected by a self-diagnosis means of the control package. at least one controlled package connected to the control package via the control bus and the signal line and each having gate means for disabling the control signal upon receipt of the abnormal signal. A control system that prevents erroneous control.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1286243A JPH03147101A (en) | 1989-11-02 | 1989-11-02 | Control system with erroneous control prevention |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1286243A JPH03147101A (en) | 1989-11-02 | 1989-11-02 | Control system with erroneous control prevention |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03147101A true JPH03147101A (en) | 1991-06-24 |
Family
ID=17701839
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1286243A Pending JPH03147101A (en) | 1989-11-02 | 1989-11-02 | Control system with erroneous control prevention |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03147101A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05334110A (en) * | 1992-06-04 | 1993-12-17 | Nec Corp | Delay error correcting device |
-
1989
- 1989-11-02 JP JP1286243A patent/JPH03147101A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05334110A (en) * | 1992-06-04 | 1993-12-17 | Nec Corp | Delay error correcting device |
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