JPH03146466A - Dielectric porcelain composition for combined circuit board - Google Patents

Dielectric porcelain composition for combined circuit board

Info

Publication number
JPH03146466A
JPH03146466A JP1284134A JP28413489A JPH03146466A JP H03146466 A JPH03146466 A JP H03146466A JP 1284134 A JP1284134 A JP 1284134A JP 28413489 A JP28413489 A JP 28413489A JP H03146466 A JPH03146466 A JP H03146466A
Authority
JP
Japan
Prior art keywords
circuit board
dielectric
dielectric layer
capacitor
combined circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1284134A
Other languages
Japanese (ja)
Other versions
JP2784545B2 (en
Inventor
Yoshihiro Fujioka
芳博 藤岡
Katsuhiko Onizuka
克彦 鬼塚
Akiya Fujisaki
昭哉 藤崎
Nobuyoshi Fujikawa
信儀 藤川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP1284134A priority Critical patent/JP2784545B2/en
Publication of JPH03146466A publication Critical patent/JPH03146466A/en
Application granted granted Critical
Publication of JP2784545B2 publication Critical patent/JP2784545B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To obtain an insulator layer, a dielectric layer, etc., having superior high frequency insulating property by blending BaTiO3 with CaZrO3, Nb2O5 and ZnO in a prescribed ratio. CONSTITUTION:BaTiO3 is blended with CaZrO3, Nb2O5 and ZnO or Co2O3 so as to obtain a compsn. represented by formula I (where 5.0<=x<=14.0mol%, 1.0<=y<=3.0mol% and 0.5<=z<=3.0mol%) or formula V (where 5.0<=x<=14.0mol%, 1.0<=y<=3.0mol% and 0.25<=z<=1.5mol%) and an org. binder, a dispersant, a plasticizer, etc., are added as required. They are mixed and molded to produce a dielectric porcelain compsn. for a combined circuit board forming a dielectric layer. Electrode layers are formed on both sides of the dielectric layer to obtain a capacitor part and this capacitor part is held between insulator layers to produce a combined circuit board with a built-in capacitor.

Description

【発明の詳細な説明】 【産業上の利用分野1 本発明はコンデンサーを内蔵した複合回路基板を形成す
る誘電体層に適用される複合回路基板用・誘電体磁器組
成物に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a dielectric ceramic composition for a composite circuit board, which is applied to a dielectric layer forming a composite circuit board incorporating a capacitor.

[従来の技術j 近年、各種の電子部品はIC及びLSI等の半導体集積
回路素子の利用で小型化・高密度実装化が急速に進めら
れ、それに伴い前記半導体集積回路素子等を搭載する絶
縁基板も小型化とともに、より高密度化が要求されてき
た。そこで、電気配線の微細化や多層化による高密度化
、および電子回路におけるコンデンサーや抵抗等の受動
部品のチップ化が進められ、更にそれら小型化された受
動部品を絶縁基板の両面に設けられた電気配線用導体層
に接続した両面実装化が実用化されたきた。
[Prior art j] In recent years, various electronic components have rapidly become smaller and more densely packaged through the use of semiconductor integrated circuit elements such as ICs and LSIs. In addition to miniaturization, there has also been a demand for higher density. Therefore, progress has been made in increasing the density of electrical wiring through miniaturization and multilayering, and in chipping passive components such as capacitors and resistors in electronic circuits. Double-sided mounting connected to conductor layers for electrical wiring has been put into practical use.

しかし乍ら、半導体材料の著しい発達に伴って電子部品
は、より一層の小型化・高密度実装化が要求されるよう
になり、前記受動部品の小型化等ではその要求を満足す
ることができなくなっていた。
However, with the remarkable development of semiconductor materials, electronic components are required to be smaller and more densely packaged, and these demands cannot be met by miniaturizing the passive components mentioned above. It was gone.

そこでかかる要求に応えるべく、絶縁基体上に誘電体ペ
ーストをスクリーン印刷法により厚膜印刷して受動素子
であるコンデンサ一部を、また同様の厚膜印刷により電
極層及び内部配線用導体層を形成し、前記絶縁基体を積
層圧着して焼威した後、積層一体化された焼結体面上に
前記と同様の厚膜印刷により形成した電気配線用導体層
及び抵抗体層を焼付けてハイブリッド化し、広範囲の優
れた温度特性と大容量のコンデンサー回路を有する小型
化・高密度化された複合セラミック回路基板を得んとす
る誘電体材料が提案されている。(特開昭63−224
107号公報参照)[発明が解決しようとする課題] しかし乍ら、この従来の複合セラミック回路基板はその
誘電体層の誘電率が100以上になるものの、1200
°C乃至1350℃の温度で同時に焼成一体化可能なM
gO−5iOz−CaO−AI !om系を主成分とす
る絶縁基体とは40℃乃至2O0℃の熱膨張率の差がl
0XIO−’/ ’Cを越え、焼成後のコンデンサ一部
にクラックを生じるという問題がある他、誘電率が15
00以上を示す組成物の誘電体では該誘電体の温度特性
が、20°Cにおける静電容量を基準として一55°C
乃至+125℃における容量変化率が±15%を越える
ことから、極めて限定された条件下でしか使用できない
という課題があった。
In order to meet these demands, a part of the capacitor, which is a passive element, is formed by thick-film printing a dielectric paste on an insulating substrate using a screen printing method, and an electrode layer and a conductor layer for internal wiring are formed by the same thick-film printing. Then, after laminating and pressing the insulating substrate and burning it, a conductor layer for electric wiring and a resistor layer formed by thick film printing similar to the above are baked on the surface of the laminated and integrated sintered body to hybridize it, Dielectric materials have been proposed with the aim of producing compact, high-density composite ceramic circuit boards that have excellent temperature characteristics over a wide range and large-capacity capacitor circuits. (Unexamined Japanese Patent Publication No. 63-224
(See Publication No. 107) [Problems to be Solved by the Invention] However, although this conventional composite ceramic circuit board has a dielectric constant of 100 or more, it has a dielectric constant of 1200 or more.
M that can be simultaneously fired and integrated at temperatures from °C to 1350 °C
gO-5iOz-CaO-AI! The difference in thermal expansion coefficient between 40°C and 200°C with the insulating substrate whose main component is om
0XIO-'/'C, which causes cracks in some capacitors after firing, and the dielectric constant is 15.
In the case of a dielectric material having a composition exhibiting a temperature of 0.00 or higher, the temperature characteristics of the dielectric material are -55°C based on the capacitance at 20°C.
Since the rate of change in capacity from +125° C. exceeds ±15%, there was a problem that it could only be used under extremely limited conditions.

[発明の目的] 本発明は上記欠点に鑑み案出されたもので、その目的は
高周波絶縁性に優れた絶縁体層と誘電体層を同時に焼威
し、広範囲にわたる優れた温度特性と大容量を有するコ
ンデンサ一部を内蔵した信頼性の高いコンデンサー内蔵
複合回路基板が得られる複合回路基板用誘電体磁器組成
物を提供することにある。
[Object of the Invention] The present invention was devised in view of the above-mentioned drawbacks, and its purpose is to simultaneously burn out an insulator layer and a dielectric layer with excellent high frequency insulation properties, and to achieve excellent temperature characteristics over a wide range and large capacity. An object of the present invention is to provide a dielectric ceramic composition for a composite circuit board from which a highly reliable capacitor-embedded composite circuit board incorporating a part of a capacitor having the following characteristics is obtained.

[課題を解決するための手段1 本発明に係る複合回路基板用誘電体磁器組成物は、誘電
体層の上下面に電極層を設けて形成したコンデンサ一部
を、絶縁体層で挾持したコンデンサー内蔵複合回路基板
において、誘電体層の組成式が (100−x −y −z ) BaTi0m 6 x
caZros・yNbt05・zZnO 但し、X5VsZはモル%を表わし 5.0≦x≦14.0 1.0≦y≦ 3.0 0.5≦z≦ 3.0 もしくは (100−x −y −z ) BaTiOs −xc
aZrOs・y NbzOs  ・Z CotOa但し
、x、y、zはモル%を表わし 5.0≦x≦14.0 1.0≦y≦ 3.0 0.25≦z≦ 1.5 から成ることを特徴とするものである。
[Means for Solving the Problems 1] The dielectric ceramic composition for a composite circuit board according to the present invention is a capacitor in which a part of a capacitor formed by providing electrode layers on the upper and lower surfaces of a dielectric layer is sandwiched between insulating layers. In the built-in composite circuit board, the compositional formula of the dielectric layer is (100-x - y -z) BaTi0m 6 x
caZros・yNbt05・zZnO However, X5VsZ represents mol% and is 5.0≦x≦14.0 1.0≦y≦3.0 0.5≦z≦3.0 or (100-x −y −z) BaTiOs-xc
aZrOs・y NbzOs・Z CotOaHowever, x, y, and z represent mol%, and are 5.0≦x≦14.0 1.0≦y≦3.0 0.25≦z≦1.5 This is a characteristic feature.

即ち、前記誘電体層の組成式中、Xの値が5.0モル%
未満の場合には、いずれも誘電体層の前記熱膨張率が1
22 XIO”’/ ”C以上となり、前記絶縁基体と
同時に焼成一体化すると誘電体層にクラックを生じ、所
期の絶縁抵抗や絶縁破壊電圧等の誘電体特性が得られな
い、他方、14.0モル%を越えるといずれも誘電率が
1500以下に低下し、かつ温度特性が劣化する。
That is, in the composition formula of the dielectric layer, the value of X is 5.0 mol%.
In both cases, the coefficient of thermal expansion of the dielectric layer is less than 1.
22 If it exceeds 0 mol %, the dielectric constant decreases to 1500 or less and the temperature characteristics deteriorate.

また、yの値が1.0モル%未満の場合には、いずれも
−55℃乃至+125°Cの温度範囲の高温側で容・量
変化率が±15%の範囲からはずれる。他方、yの値が
3.0モル%を越えるといずれも一55°C乃至+12
5°Cの温度範囲全域で容量変化率が±15%の範囲か
らはずれる。
Further, when the value of y is less than 1.0 mol%, the volume/volume change rate is out of the range of ±15% on the high temperature side of the temperature range of -55°C to +125°C. On the other hand, when the value of y exceeds 3.0 mol%, the temperature ranges from -55°C to +12°C.
The capacitance change rate deviates from the range of ±15% over the entire temperature range of 5°C.

一方、2の値は、組成式が(100−x −y −z 
)BaTiOs −x CaZr0= −y NbzO
s  −z ZnOで示され0゜5モル%未満の場合、
もしくは組成式が(100−x−y −z) BaTi
0. ・xcaZrO,・7NbzO5+ zco、0
3で示され0.25モル%未満の場合には、いずれも−
55℃乃至+125℃の温度範囲の高温側で容量変化率
が±15%の範囲からはずれる。他方、組成式が(10
0−x−y−z) BaTi0.・xCaZrO,・)
’NbzOs・z ZnOで示され2の値が3.0モル
%を越える場合、もしくは組成式が(100−x −y
 −z ) BaTi0゜・xcaZrO,・yNb*
os  ・zcozOzで示され2の値が1.5モル%
を越える場合には、いずれも−55°C乃至+125°
Cの温度範囲全域で容量変化率が±15%の範囲からは
ずれる。
On the other hand, for a value of 2, the composition formula is (100-x -y -z
) BaTiOs −x CaZr0= −y NbzO
If it is represented by s −z ZnO and is less than 0°5 mol%,
Or the composition formula is (100-x-y-z) BaTi
0.・xcaZrO, ・7NbzO5+ zco, 0
3 and less than 0.25 mol%, all -
On the high temperature side of the temperature range of 55°C to +125°C, the rate of change in capacity deviates from the range of ±15%. On the other hand, the composition formula is (10
0-x-y-z) BaTi0.・xCaZrO,・)
'NbzOs・z ZnO and the value of 2 exceeds 3.0 mol%, or the composition formula is (100-x -y
-z ) BaTi0゜・xcaZrO,・yNb*
It is expressed as os ・zcozOz, and the value of 2 is 1.5 mol%
-55°C to +125° if exceeding
The capacitance change rate deviates from the range of ±15% over the entire temperature range of C.

故に、前記誘電体層の組成式中のxs 3’及び2の値
は夫々前記範囲に特定される。
Therefore, the values of xs 3' and 2 in the compositional formula of the dielectric layer are respectively specified within the above ranges.

■作用] コンデンサー内蔵複合回路基板用の誘電体層としてBa
Ti0.を主成分とする誘電体材料にNb、0.とZn
OまたはCot(hのいずれかを固溶させることにより
、広範囲の温度領域での容量変化率は±15%以内と極
めて小さくなる。
■Function] Use Ba as a dielectric layer for composite circuit boards with built-in capacitors.
Ti0. A dielectric material mainly composed of Nb, 0. and Zn
By dissolving either O or Cot(h), the rate of change in capacity over a wide temperature range becomes extremely small, within ±15%.

更に、前記NbzOsとZnOまたはCo、O,のいず
れかと熱膨張恨事が極めて小なるCaZr01の双方を
固溶させることにより、誘電体層の容量変化率へ影響を
与えずに、誘電体層の熱膨張恨事を121 Xl0−7
/℃以下に低く制御することが可能となる。
Furthermore, by dissolving both NbzOs, ZnO, Co, O, and CaZr01, which has extremely low thermal expansion, the heat of the dielectric layer can be reduced without affecting the capacitance change rate of the dielectric layer. Expanded Grudge 121 Xl0-7
It becomes possible to control the temperature to a low temperature of /℃ or less.

[実施例1 次に本発明の複合回路基板用誘電体磁器MLt7.物を
実施例に基づき詳細に説明する。
[Example 1] Next, dielectric ceramic MLt7. for composite circuit boards of the present invention was prepared. The object will be explained in detail based on examples.

コンデンサ一部は該コンデンサ一部を構成する誘電体層
が第1表に示す組成となる様にBaTiOsを主成分と
し、CaZrOs、Nb、05 とZnOまたはCo、
03から成る誘電体材料の原料粉末に適当な有機バイン
ダー、分散剤、可塑剤及び溶剤を添加してボールミルに
て混合し、泥漿を調製する。得られた泥漿物を例えば従
来周知の引上げ法によりコンデンサー容量設定のため厚
さ25μm乃至55μmのグリーンシートに打ち抜き加
工を施し、170mm角の誘電体シートを得た。
The dielectric layer constituting the capacitor part has the composition shown in Table 1, with BaTiOs as the main component, CaZrOs, Nb, 05, ZnO or Co,
A suitable organic binder, dispersant, plasticizer and solvent are added to the raw material powder of the dielectric material consisting of 03 and mixed in a ball mill to prepare a slurry. The obtained slurry was punched out into a green sheet having a thickness of 25 μm to 55 μm to set the capacitor capacity by, for example, a conventionally well-known drawing method to obtain a dielectric sheet of 170 mm square.

次いで前記誘電体シート上面に銀・パラジウム(Ag−
Pb)合金等の金属粉末に適当な溶剤、溶媒を添加混合
して成る導電ペーストを従来周知のスクリーン印刷法等
の厚膜印刷法により、約2mm乃至9In11角の電極
パターンを必要とする静電容量に応じて印刷形成した。
Next, silver/palladium (Ag-
A conductive paste made by adding and mixing a metal powder such as a Pb) alloy with an appropriate solvent is used to produce an electrostatic paste that requires an electrode pattern of about 2 mm to 9In11 squares using a conventional thick film printing method such as screen printing. Printing was performed according to the capacity.

一方、絶縁体層はMgO、Sin、、CaO及びA1.
03から成る混合物の仮焼物粉末に有機バインダー分散
剤、可塑剤及び溶媒を添加混合して泥漿を調製し、従来
周知のドクターブレード法等により厚さ200 μmの
グリーンシートを底形し、しかる後、該グリーンシート
に打ち抜き加工を施し、170mm角の絶縁体シートを
得るとともに、コンデンサー部及び絶縁体層の上下面の
導通をはかるためスルホール部を形成し、更に該スルホ
ール部にも前記導電ペーストを充填した。
On the other hand, the insulator layer is made of MgO, Sin, CaO and A1.
A slurry was prepared by adding and mixing an organic binder dispersant, a plasticizer, and a solvent to the calcined powder of the mixture consisting of 0.03, and a green sheet with a thickness of 200 μm was shaped using the conventionally well-known doctor blade method. The green sheet was punched to obtain a 170 mm square insulator sheet, and through-holes were formed to ensure electrical continuity between the capacitor part and the upper and lower surfaces of the insulator layer, and the conductive paste was also applied to the through-holes. Filled.

次いで前記複数枚の絶縁体シートの間に、前記チタン酸
バリウムから成る誘電体シートを複数枚積層したものを
挾み込み、熱圧着し、得られた積層体を大気中、200
″C乃至400℃の温度で脱バインダーし、続いて12
40’c〜1340℃の温度にて大気中で焼威して一体
化し、コンデンサ一部を内蔵した絶縁基板を得る。
Next, a plurality of laminated dielectric sheets made of barium titanate were sandwiched between the plurality of insulator sheets and thermocompression bonded, and the resulting laminate was exposed to air for 200 minutes.
Debinding at a temperature of 12°C to 400°C, followed by
The product is baked in the air at a temperature of 40'C to 1340C to be integrated to obtain an insulating substrate with a part of the capacitor built therein.

かくして前記焼成一体化後の絶縁基板にスクリーン印刷
法によりAg−Pb系合金ペーストを使用して電気配線
用導体パターンを形威し、電極を焼付けた。
Thus, a conductor pattern for electrical wiring was formed on the insulating substrate after the firing and integration using a screen printing method using an Ag-Pb alloy paste, and electrodes were baked.

上記評価試料によりLCRメーターを使用してコンデン
サ一部の電極層間の短絡の有無を確認した後、JIS 
C5102の規定に準じて周波数IKk、入力信号レベ
ルl、QVrmsの測定条件にてコンデンサー部の静電
容量を測定し、該静電容量から比誘電率(gr)を算出
し、一方、前記コンデンサ一部の一55℃乃至+125
℃における静電容量を測定し、+25℃での静電容量を
基準として、容量変化率を温度特性(TCC)として算
出した。
After confirming the presence or absence of a short circuit between the electrode layers of a part of the capacitor using the above evaluation sample using an LCR meter, the JIS
The capacitance of the capacitor part was measured under the measurement conditions of frequency IKk, input signal level l, and QVrms according to the regulations of C5102, and the relative dielectric constant (gr) was calculated from the capacitance. 55℃ to +125℃
The capacitance at °C was measured, and the capacitance change rate was calculated as a temperature characteristic (TCC) based on the capacitance at +25 °C.

また、誘電体層及び絶縁体層の熱膨張率は、それぞれ前
記評価試料と同−組成であるll3mm、横3開、長さ
49ma+の角柱状試験片を前記評価試料の坑底と同時
に焼威し、40”C乃至2O0 ”Cの温度範囲におけ
る平均熱膨張率を測定した。
In addition, the thermal expansion coefficients of the dielectric layer and the insulating layer were determined by incinerating a prismatic test piece of 3 mm in width, 3 openings in width, and 49 ma+ in length, which had the same composition as the evaluation sample, at the same time as the bottom of the pit of the evaluation sample. Then, the average coefficient of thermal expansion was measured in a temperature range of 40"C to 2O0"C.

以上の結果を第1表に示す。The above results are shown in Table 1.

(以下余白) [発明の効果1 本発明の複合回路基板用誘電体磁器m放物によれば、高
周波絶縁性に優れた絶縁体層と高い誘電率を有する誘電
体層とが互いに反応することなく、低温度で同時に焼成
一体化することが可能でありかつ前記絶縁体層と誘電体
層の熱膨張率を互いに極めて近似したものとすることが
できることから、誘電体層にクランク等の欠陥を生ぜず
、広範囲にわたる優れた温度特性と大容量を有するコン
デンサ一部を同時に内蔵することができ、その結果、ハ
イブリッド基板等に最適な小型化・高密度化されたコン
デンサー内蔵複合回路基板を得ることができる。
(Left below) [Advantageous Effects of the Invention 1] According to the dielectric ceramic m-paraboloid for a composite circuit board of the present invention, an insulating layer having excellent high frequency insulation properties and a dielectric layer having a high dielectric constant react with each other. It is possible to simultaneously bake and integrate the insulator layer and the dielectric layer at a low temperature, and the thermal expansion coefficients of the insulator layer and the dielectric layer can be made very similar to each other. It is possible to simultaneously incorporate a part of a capacitor with excellent temperature characteristics over a wide range and a large capacity without causing heat generation, and as a result, a compact, high-density capacitor-embedded composite circuit board that is ideal for hybrid boards, etc. can be obtained. Can be done.

Claims (1)

【特許請求の範囲】 (1)組成式が (100−x−y−z)BaTiO_3・xCaZrO
_3・yNb_2O_5・zZnO 但し、x、y、zはモル%を表わし 5.0≦x≦14.0 1.0≦y≦3.0 0.5≦z≦3.0 から成る複合回路基板用誘電体磁器組成物。 (2)組成式が (100−x−y−z)BaTiO_3・xCaZrO
_3・yNb_2O_3・zCO_2O_3 但し、x、y、zはモル%を表わし 5.0≦x≦14.0 1.0≦y≦3.0 0.25≦z≦1.5 から成る複合回路基板用誘電体磁器組成物。
[Claims] (1) The compositional formula is (100-x-y-z)BaTiO_3.xCaZrO
_3・yNb_2O_5・zZnO However, x, y, and z represent mol%, and are for composite circuit boards consisting of 5.0≦x≦14.0 1.0≦y≦3.0 0.5≦z≦3.0 Dielectric porcelain composition. (2) The composition formula is (100-x-y-z)BaTiO_3・xCaZrO
_3・yNb_2O_3・zCO_2O_3 However, x, y, and z represent mol%, and are for composite circuit boards consisting of 5.0≦x≦14.0 1.0≦y≦3.0 0.25≦z≦1.5 Dielectric porcelain composition.
JP1284134A 1989-10-31 1989-10-31 Dielectric ceramic composition for composite circuit board Expired - Fee Related JP2784545B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400210A (en) * 1992-07-06 1995-03-21 Ngk Spark Plug Co., Ltd. Substrate having a built-in capacitor and process for producing the same
US5990029A (en) * 1997-02-25 1999-11-23 Tdk Corporation High dielectric-constant dielectric ceramic composition, and its fabrication process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400210A (en) * 1992-07-06 1995-03-21 Ngk Spark Plug Co., Ltd. Substrate having a built-in capacitor and process for producing the same
US5990029A (en) * 1997-02-25 1999-11-23 Tdk Corporation High dielectric-constant dielectric ceramic composition, and its fabrication process

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