JPH03145165A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable the rapid formation of a depletion layer inside a high resistivity layer and to improve a semiconductor device more in switching speed by a method wherein at a least a hole is provided to the high resistivity layer extending from a surface side to an insulating base, and a control electrode layer is formed on the high resistivity layer and inside the hole concerned. CONSTITUTION:When a zero or a positive voltage is applied to a gate layer 7 as keeping a first N-type single crystal silicon layer 3 at a zero potential and applying a positive potential to a second N-type single crystal silicon layer 4, electrons from the first N-type single crystal silicon layer 3 pass through an intrinsic layer 5, and a current flows. On the other hand, the first N-type single crystal silicon layers 3 and 4 are kept at a zero and a positive potential respectively, and a negative potential is applied to the gate layer 7 keeping the layers 3 and 4 in this state. In this state, electrons in the intrinsic layer 5 around the gate layer 7 are expelled to make the layer 5 depleted. At this point, a part of the intrinsic layer 5 is replaced with the gate layer 7, so that a negative voltage is applied to the intrinsic layer 5 in a lateral direction. By this setup, a depletion layer is rapidly formed in the intrinsic layer 5, so that a semiconductor device of this design can be improved in switching speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and in particular to an SOI type static induction transistor in which an element is formed on an isolated substrate.

[Prior Art] Conventionally, among electrostatic induction transistors that utilize electrostatic induction effects, Sol type electrostatic induction transistors are known in which the electrostatic induction transistor is formed on an insulating substrate in order to improve switching characteristics. .

Figure 3 is a cross-sectional view of a conventional Sol type static induction transistor. FIG. 4 is a plan view of the Sol type static induction transistor shown in FIG. 3.

Referring to FIG. ff13 and FIG. Between the first N-type single-crystal silicon layer 3 and the second N-type single-crystal silicon layer 4 formed above at a predetermined interval, and the first N-type single-crystal silicon layer 3 and the second N-type single-crystal silicon layer 4. The single crystal silicon layer (hereinafter referred to as the "intrinsic layer") 10 containing no electrically conductive impurities and the P! 42 gate layer 11 made of silicon
including.

An oxide film 8 for insulation is formed to cover the side surfaces of the first N-type single crystal silicon layer 3 and the second N-type single crystal silicon layer 4 and the gate layer 11. Aluminum interconnections 9 are provided on the upper surfaces of the first N-type single crystal silicon layer 3 and the second N-type single crystal silicon layer 4 and on the gate layer 11.

Next, the operation will be explained. First, the first N-type single-crystal silicon layer 3 is brought to zero potential, and a positive voltage is applied to the second N-type single-crystal silicon layer 4. Here, when zero or positive voltage is applied to the gate layer 11, electrons from the mlN type single crystal silicon layer 3 pass through the intrinsic layer 10. This causes current to flow.

On the other hand, similarly to the above, a negative voltage is applied to the gate layer 11 while a zero potential is applied to the first N-type single-crystal silicon layer 3 and a positive voltage is applied to the second N-type single-crystal silicon layer 4 . In this state, first, electrons in the intrinsic layer 10 around the gate layer 11 are expelled and become depleted. After depletion, electrons cannot approach due to the electrostatic induction effect and cannot pass through the intrinsic layer 10. As a result, current no longer flows.

In this way, a static induction transistor sandwiches a thin layer without electrons or holes between conductor layers through which electrons flow, and applies a negative voltage to this thin layer. The electrostatic induction effect caused by this negative voltage prevents electrons from entering the thin layer, thereby preventing current from flowing. This static induction transistor may be a bulk silicon type that is directly formed on a normal semiconductor substrate, but if it is a bulk cyanocon type, the area in which the depletion layer must be expanded will be larger than in the Sol type. However, there are disadvantages that the switching speed becomes slow and the reliability of the switching operation decreases. On the other hand, the SO1 type static induction transistor is formed by a thin semiconductor layer formed on an insulating substrate, as shown in FIG. As a result, when forming a depletion layer to block the flow of electrons, the area where the depletion layer is formed is smaller than that of the bulk silicon type, and the area where the depletion layer is formed in the vertical direction is limited. becomes. As a result, there are advantages in that the switching speed can be improved and the reliability of the switching operation can be improved.

[Issues to be Solved by the Invention i] As mentioned above, the conventional Sol type static induction transistor is formed by a thin semiconductor layer on an insulating substrate. This requires less area to form a depletion layer than the bulk silicon type, and limits the area in which a depletion layer must be formed in the vertical direction, improving switching speed and improving the reliability of switching operation. can be improved. However, in the conventional Sol-type static induction transistor, since the gate layer 11 is formed on the surface of the intrinsic layer 10, the depletion layer extends to the bottom of the intrinsic layer 10 on the side of the first N-type single crystal silicon layer 3. It takes time to expand. As a result, it has been difficult to further improve the control speed when controlling the current between the first N-type single crystal silicon layer 3 and the second N-type single crystal silicon layer 4 using the voltage of the gate layer 11.

In other words, in the conventional Sol-type static induction transistor, the intrinsic layer 10 on the first N-type single crystal silicon layer 3 side
Since it takes time to expand the depletion layer to the bottom of the device, it has been difficult to further improve the switching speed.

The present invention was made to solve the above problems, and an object of the present invention is to provide a semiconductor device that can further improve switching speed.

[Means for Solving the Problems] A semiconductor device according to the present invention includes an insulating base, a first conductive layer formed on the main surface of the insulating base, and a first conductive layer formed on the insulating base at a predetermined interval. A second conductive layer is formed between the first conductive layer and the second conductive layer, and at least one hole is provided from the surface side to the insulating base side, and a positive or negative hole is formed between the first conductive layer and the second conductive layer. a high resistivity layer in which air/grass debris is formed when a voltage of Features.

[Function] In the semiconductor device of the present invention, the high resistivity layer is provided with at least one hole extending from the surface side toward the insulating substrate side, and the control electrode layer is formed on the high resistivity layer and within the hole. Therefore, when forming a depletion layer in a high resistivity layer to block the flow of electrons, the negative voltage that forms the depletion layer is applied not only from above the high resistivity layer but also from the side, and the depletion layer is rapidly formed.

[Embodiment of the Invention] FIG. 1 is a sectional view showing the structure of an SOI type static induction transistor showing an embodiment of the invention. FIG. 2 is a plan view of the electrostatic induction transistor shown in FIG. 1.

Referring to FIGS. 1 and 2, the static induction transistor includes a semiconductor substrate 1 made of silicon, an oxide film 2 formed on the semiconductor substrate 1, and a structure in which the oxide film 2 is spaced apart from each other by a predetermined distance. The formed first N-type single crystal silicon layer 3 and the second
formed between the N-type single-crystal silicon layer 4, the first N-type single-crystal silicon layer 3 and the second N-type single-crystal silicon layer 4,
Intrinsic layer 5 provided with through hole 6 reaching oxide film 2, and intrinsic layer 5 and its through hole 6
A gate layer 7 made of P-type silicon is formed inside the gate.

An oxide film 8 for insulation is formed to cover the side surfaces of the first N-type single crystal silicon layer 3 and the second N-type single crystal silicon layer 4 and the gate layer 7.

Aluminum wiring 9 is provided on the upper surfaces of the first N-type single crystal silicon layer 3 and the second N-type single crystal silicon layer 4 and on the gate layer 7.
is applied.

Next, the operation will be explained. First, the first N-type single-crystal silicon layer 3 is brought to zero potential, and the second N-type single-crystal silicon layer 4 is
Apply a positive voltage to . Here, when a zero or positive voltage is applied to the gate layer 7, electrons from the first N-type single crystal silicon layer 3 pass through the intrinsic layer 5 as in the conventional case. As a result, current flows.

On the other hand, similarly to the above, a negative voltage is applied to the gate layer 7 while a zero potential is applied to the first N-type single-crystal silicon layer 3 and a positive voltage is applied to the second N-type single-crystal silicon layer 4 . In this state, first, electrons in the intrinsic layer 5 around the gate layer 7 are expelled and depleted. After being depleted, electrons cannot approach due to the electrostatic induction effect and cannot pass through the intrinsic layer 5.

As a result, current no longer flows. In this way, the operation is the same as the conventional one. However, in this embodiment, a part of the intrinsic layer 5 is replaced by a gate layer 71. Therefore, when a negative voltage is applied to the gate layer 7, the negative voltage is applied to the intrinsic layer 5.
It can be added not only from above but also from the side. This results in
A depletion layer is rapidly formed in the intrinsic layer 5. As a result, the switching speed of the static induction transistor is improved.

In the manufacturing method of this embodiment, as in the conventional method, a semiconductor layer is formed on the oxide film 2, and then the through holes 6 are formed by etching. The subsequent steps are the same as conventional ones.

In the above embodiment, N-type single crystal silicon was used as the conductive layer, but the present invention is not limited to this, and P-type monocrystalline silicon may also be used. Further, although an intrinsic layer containing no electrically conductive impurities was used as the high resistivity layer, the present invention is not limited to this, and the present invention is not limited to this. The material may contain electrically conductive impurities as long as the depletion layer expands when a voltage of Although P-type silicon is used as the material for the gate layer 7, the present invention is not limited to this, and a high melting point metal or the like may be used.

[Effects of the Invention] As described above, according to the present invention, at least one hole reaching the insulating substrate is provided in the high resistivity layer, and a control electrode layer is formed on the high resistivity layer and within the hole. When a depletion layer is formed in the high resistivity layer to block the flow of electrons, the negative voltage that forms the depletion layer is applied not only from above the high resistivity layer but also from the side, causing the depletion Since the layer is rapidly formed, the flow of electrons can be blocked quickly, and the switching speed can be further improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of an SOI type static induction transistor showing an embodiment of the present invention, FIG. 2 is a plan view of the static induction transistor shown in FIG. 1, and FIG. FIG. 4 is a cross-sectional view showing the structure of a conventional Sol type static induction transistor, and FIG. 4 is a plan view of the static induction transistor shown in FIG. 3. In the figure, 1 is a semiconductor substrate, 2 is an oxide film, and 3 is a first N
type single crystal silicon layer, 4 is a second N type single crystal silicon layer,
5 is an intrinsic layer, 6 is a through hole, 7 is a gate, 8
9 is an oxide film, and 9 is an aluminum wiring. In the drawings, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa 10 Certain 2 figures 30 Figure 4

Claims (1)

[Scope of Claims] An insulating base; a first conductive layer formed on the main surface of the insulating base; and a first conductive layer formed on the insulating base at a predetermined distance from the first conductive layer. a conductive layer formed between the first conductive layer and the second conductive layer, at least one hole extending from the surface side toward the insulating substrate side, to which a positive or negative voltage is applied; and a control electrode layer formed on the high resistivity layer and in a hole provided in the high resistivity layer.
Semiconductor equipment.