JPH03142534A - Memory double writing system - Google Patents

Abstract

PURPOSE:To attain the double writing to both working and spare system memories even these two memories perform the refreshing operations independent of each other by providing a circuit to the spare system to write the data into the memory in a cycle except a refresh cycle of the memory. CONSTITUTION:The systems 0 and 1 are used as a working system and a spare system respectively. Thus a memory write signal 7 received from a processor 1 is written to its own system memory 17 after the conflict caused with a refresh signal 13 through a conflict circuit 15. In the same time band, an address and the data are written into a FIFO memory 6. In a spare system, the contents 10 of the memory 6 are read out and written into a spare system memory 18 after the conflict caused with a refresh signal 14. Therefore the spare system includes a circuit which writes the contents 10 into a memory in a cycle except a refresh cycle of the memory 18. As a result, the double write is possible to both systems even when the both system memories are carrying out the refreshing operations independent of each other.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory dual write method used in a data processing system with a dual configuration.

Conventional technical data processing systems, especially real-time data processing systems, employ a redundant configuration of an active system and a backup system to ensure continuity and reliability of processing, and when a failure occurs in the active system, the backup system is The processing is now taken over. In this case, it is necessary to have the processing data before the failure occur from the active system to the standby system.

Methods for taking over this processing data include using a common memory between the active and backup systems, and memory copying, which reads the processing data from the memory of the active system and writes it to the memory of the backup system when switching between the active and backup systems. One-sided methods are used.

However, the method of using a common memory has a reliability problem in that if a failure occurs in the common memory, both the active system and the standby system will be unable to process.

Furthermore, the memory copy method has a problem in continuity of operation because normal processing is interrupted during memory copy after system switching.

Therefore, a memory double write method is adopted in which a bus composed of a memory address line and a memory data line is installed as a confounding signal line, and processing data is simultaneously written into the memories of both systems.

Problems to be Solved by the Invention However, the memory dual write method has problems in systems that use dynamic RAM (DRAM) as memory.
There is a problem in that it is difficult to synchronize the refresh cycles of the active system and the backup system.

Furthermore, in the method of writing data into the active memory and then writing the same content into the backup memory, a problem arises in that the memory access time from the processor is doubled.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel memory dual write method that makes it possible to solve the above-mentioned problems inherent in the conventional technology. It's about doing.

Means for Solving the Problems In order to achieve the above object, the memory double write method according to the present invention provides a method for writing the address and data at the same time when the active processor writes data to the active memory. It has FIFO memory, and in the standby system, the FIFO memory
It is configured to include a circuit that writes the address and data loaded in the FO memory to the spare memory in a cycle other than the refresh cycle.

Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is a block diagram showing an example of a loading circuit into the FIFO memory in the current system, and FIG. 4 is a diagram showing an example of a time chart at that time. Also, Figure 3 shows F in the standby system.
It is a block diagram showing an example of a write signal generation circuit from an IFO memory to a spare memory, and FIG. 5 is a diagram showing an example of a time chart thereof.

Referring to FIG. 1, if the O system is the active system and the 1 system is the backup system, the memory write signal 7 from the processor 1 is sent to the own system memory 17 by the refresh signal 13 and the contention circuit 15.
written after a conflict.

At the same time, the address and data are loaded into the FIFO memory 6. Address 23 and data 24 in FIG. 2 are latched by latch circuits 21 and 22, respectively, and multiplexed by selector 20 and loaded into FIFO memory 6.

Further, in the standby system, the contents 10 of this FTFO memory 6 are read out, passed through the selector 12, and further written into the standby system memory 18 after competing with the refresh signal 14.

At this time, the circuit that separates the address and data from the FIFO memory 6 by the latch circuits 27 and 28 is the circuit shown in FIG. 3, and an example of a time chart at this time is shown in FIG.

The above explanation is for the case where the O system is the active system and the 1 system is the backup system, but it is clear that the same operation will occur if the 1 system is the active system and the 0 system is the backup system. Yes, but in that case, FIFO memory 5 is used instead of FIFO memory 6.
works.

As described in detail, according to the present invention, a FIFO memory is provided between the active system and the standby system for writing addresses and data when the active system processor writes the memory, and The system has a circuit for writing the contents of the FIFO memory to the memory in a cycle other than the refresh cycle of the spare memory, so that even if the memories in both systems are refreshed independently, This provides the advantage of being able to perform double writing.

[Brief explanation of the drawing]

FIG. 1 is a block P4 diagram showing an embodiment of the memory dual write method according to the present invention, and FIGS. 2 and 3 are block diagrams showing an example of a circuit for loading into the FIFO memory and an example of a circuit for reading from the FIFO memory. The configuration diagram, Figures 4 and 5 are
FIG. 4 is an operation time chart of FIG. 4 and FIG. 3;

Claims (3)

[Claims] (1) A data processing system consisting of an active system and a backup system, each system including a memory that requires refreshing, and a processor that writes and reads from the memory;
These memories are composed of buses that connect the processors, and when the memory of each system is refreshed asynchronously, when the active processor writes data to the active memory, the address and It has a FIFO memory for writing data, and in the standby system, it has a circuit that writes the address and data loaded in the FIFO memory to the standby system memory in a cycle other than the refresh cycle. A memory dual write method characterized by writing data to both memory systems. (2) A loading circuit that loads the same write address and data as the active memory into the FIFO memory, a first latch circuit that latches the address, a second latch circuit that latches the data, and a loading circuit that loads the same write address and data as the active memory into the FIFO memory; 1. a selector that multiplexes the outputs of the second latch circuit;
2. The memory dual write system according to claim 1, further comprising a fourth latch circuit for latching data. (3) The circuit for writing the address and data loaded in the FIFO memory to the spare memory in a cycle other than the refresh cycle is configured to output the output of the write signal generation circuit to the spare memory and a refresh request signal. The memory dual write system according to claim 1 or 2, further comprising a competition circuit for competing with.