JPH03142534A - Memory double writing system - Google Patents

Memory double writing system

Info

Publication number
JPH03142534A
JPH03142534A JP1280761A JP28076189A JPH03142534A JP H03142534 A JPH03142534 A JP H03142534A JP 1280761 A JP1280761 A JP 1280761A JP 28076189 A JP28076189 A JP 28076189A JP H03142534 A JPH03142534 A JP H03142534A
Authority
JP
Japan
Prior art keywords
memory
data
circuit
address
active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1280761A
Other languages
Japanese (ja)
Inventor
Teiichi Ishido
石戸 悌一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1280761A priority Critical patent/JPH03142534A/en
Publication of JPH03142534A publication Critical patent/JPH03142534A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain the double writing to both working and spare system memories even these two memories perform the refreshing operations independent of each other by providing a circuit to the spare system to write the data into the memory in a cycle except a refresh cycle of the memory. CONSTITUTION:The systems 0 and 1 are used as a working system and a spare system respectively. Thus a memory write signal 7 received from a processor 1 is written to its own system memory 17 after the conflict caused with a refresh signal 13 through a conflict circuit 15. In the same time band, an address and the data are written into a FIFO memory 6. In a spare system, the contents 10 of the memory 6 are read out and written into a spare system memory 18 after the conflict caused with a refresh signal 14. Therefore the spare system includes a circuit which writes the contents 10 into a memory in a cycle except a refresh cycle of the memory 18. As a result, the double write is possible to both systems even when the both system memories are carrying out the refreshing operations independent of each other.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、二重化構成のデータ処理シスtムに利用され
るメモリ二重書き方式に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a memory dual write method used in a data processing system with a dual configuration.

従来の技術 データ処理システム、特に実時間型のデータ処理システ
ムでは、処理の連続性や信頼性を確保する為に現用系と
予備系の二重化構成が採用され、現用系に障害が発生す
ると予備系に処理が引き継がれるようになっている。こ
の場合、障害発生前の処理データを現用系から予備系に
引き継がせる必要がある。
Conventional technical data processing systems, especially real-time data processing systems, employ a redundant configuration of an active system and a backup system to ensure continuity and reliability of processing, and when a failure occurs in the active system, the backup system is The processing is now taken over. In this case, it is necessary to have the processing data before the failure occur from the active system to the standby system.

この処理データの引継ぎ方法としては、現用系と予備系
で共通のメモリを使用する方法や、現用系と予備系の切
換え時に現用系のメモリから処理データを読み出して予
備系のメモリに書込むメモリコピ一方法などが採用され
ている。
Methods for taking over this processing data include using a common memory between the active and backup systems, and memory copying, which reads the processing data from the memory of the active system and writes it to the memory of the backup system when switching between the active and backup systems. One-sided methods are used.

しかしながら、共通メモリを利用する方法は、この共通
メモリに障害が発生すると現用系も予備系も処理不能に
なるという信頼性上の問題がある。
However, the method of using a common memory has a reliability problem in that if a failure occurs in the common memory, both the active system and the standby system will be unable to process.

また、メモリコピ一方法は、系切換え後のメモリコピー
の間通常の処理が中断されるので動作の連続性上の問題
がある。
Furthermore, the memory copy method has a problem in continuity of operation because normal processing is interrupted during memory copy after system switching.

そこで、メモリアドレス線とメモリデータ線から構成さ
れるバスを交絡信号線として設置し両系のメモリに同時
に処理データを書き込むメモリ二重書き方法が採用され
る。
Therefore, a memory double write method is adopted in which a bus composed of a memory address line and a memory data line is installed as a confounding signal line, and processing data is simultaneously written into the memories of both systems.

発明が解決しようとする課題 しかしながらメモリ二重書き方法は、メモリとしてダイ
ナミンクRAM(DRAM)を使用するシステムでは、
現用系と予備系のリフレッシュサイクルを同期させるこ
とが困難であるという問題がある。
Problems to be Solved by the Invention However, the memory dual write method has problems in systems that use dynamic RAM (DRAM) as memory.
There is a problem in that it is difficult to synchronize the refresh cycles of the active system and the backup system.

また、現用系メモリに書込んでから、同一内容を予備系
メモリに書込むという方法では、プロセッサからのメモ
リアクセス時間が2倍かがるという問題が生じる。
Furthermore, in the method of writing data into the active memory and then writing the same content into the backup memory, a problem arises in that the memory access time from the processor is doubled.

本発明は従来の上記実情に鑑みてなさり、たちのであり
、従って本発明の目的は、従来の技術に内在する上記諸
課題を解決することを可能とした新規なメモリ二重書き
方式を提供することにある。
The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel memory dual write method that makes it possible to solve the above-mentioned problems inherent in the conventional technology. It's about doing.

課題を解決するための手段 上記目的を達成する為に、本発明に係るメモリ二重書き
方式は、現用系プロセッサが現用系メモリにデータ書込
みを行う際、同時にそのアドレスとデータを書込むため
のFIFOメモリを有し、また予備系においては該FI
FOメモリに積み込まれたアドレスとデータをリフレッ
シュサイクル以外のサイクルで予備系メモリへ書込む回
路を備えて構成される。
Means for Solving the Problems In order to achieve the above object, the memory double write method according to the present invention provides a method for writing the address and data at the same time when the active processor writes data to the active memory. It has FIFO memory, and in the standby system, the FIFO memory
It is configured to include a circuit that writes the address and data loaded in the FO memory to the spare memory in a cycle other than the refresh cycle.

実施例 第1図は本発明の一実施例を示すブロック構成図、第2
図は現用系においてFIFOメモリへの積み込み回路の
一例を示すブロック図であり、第4図はその際のタイム
チャート例を示す図である。また第3図は予備系でのF
IFOメモリがら予備系メモリへの書込み信号生成回路
の一例を示すブロック図で有り、第5図はそのタイムチ
ャート例を示す図である。
Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
The figure is a block diagram showing an example of a loading circuit into the FIFO memory in the current system, and FIG. 4 is a diagram showing an example of a time chart at that time. Also, Figure 3 shows F in the standby system.
It is a block diagram showing an example of a write signal generation circuit from an IFO memory to a spare memory, and FIG. 5 is a diagram showing an example of a time chart thereof.

第1図を参照するに、O系を現用系、1系を予備系とす
ると、プロセッサ1からのメモリ書き込み信号7は、自
系メモリ17へはリフレッシュ信号13と競合回路15
により競合ののちに書込まれる。
Referring to FIG. 1, if the O system is the active system and the 1 system is the backup system, the memory write signal 7 from the processor 1 is sent to the own system memory 17 by the refresh signal 13 and the contention circuit 15.
written after a conflict.

これと同一時間帯で、FIFOメモリ6へそのアドレス
とデータが積込まれる。第2図のアドレス23とデータ
24は、それぞれラッチ回路21と22によりラッチさ
れ、又セレクタ20によって多重されてFIFOメモリ
6へ積込まれる。
At the same time, the address and data are loaded into the FIFO memory 6. Address 23 and data 24 in FIG. 2 are latched by latch circuits 21 and 22, respectively, and multiplexed by selector 20 and loaded into FIFO memory 6.

また予備系ではこのFTFOメモリ6の内容10を読出
しセレクタ12を経由し、更にリフレッシュ信号14と
競合ののちに予備系メモリ18へ書込まれる。
Further, in the standby system, the contents 10 of this FTFO memory 6 are read out, passed through the selector 12, and further written into the standby system memory 18 after competing with the refresh signal 14.

その際にFIFOメモリ6がらアドレスとデータをラッ
チ回路27.28により分離する回路が第3図に示す回
路であり、この際のタイムチャート例が第5図である。
At this time, the circuit that separates the address and data from the FIFO memory 6 by the latch circuits 27 and 28 is the circuit shown in FIG. 3, and an example of a time chart at this time is shown in FIG.

以上の説明はO系を現用系、1系を予備系とした場合の
ものであるが、逆に1系を現用系、0系を予備系とした
場合にも同様に動作することは明らかであり、但しその
場合にはFIFOメモリ6の代わりにFIFOメモリ5
が動作する。
The above explanation is for the case where the O system is the active system and the 1 system is the backup system, but it is clear that the same operation will occur if the 1 system is the active system and the 0 system is the backup system. Yes, but in that case, FIFO memory 5 is used instead of FIFO memory 6.
works.

発明の詳細 な説明したように、本発明によれば、現用系と予備系間
に、現用系プロセッサがらのメモリ書込みの際に、その
アドレスとデータを書込むためのFIFOメモリを有し
、予備系では、該FIFOメモリの内容を予備系メモリ
のリフレッシュサイクル以外のサイクルでメモリへ書込
むための回路を有することにより、両系のメモリは独立
したリフレッシュを行っていても、両系へのメモリ二重
書込みが行えると言う効果が得られる。
As described in detail, according to the present invention, a FIFO memory is provided between the active system and the standby system for writing addresses and data when the active system processor writes the memory, and The system has a circuit for writing the contents of the FIFO memory to the memory in a cycle other than the refresh cycle of the spare memory, so that even if the memories in both systems are refreshed independently, This provides the advantage of being able to perform double writing.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係るメモリ二重書き方式の一実施例を
示すブロックP4戒図、第2図及び第3図はFIFOメ
モリへの積込み回路例及びFIFOメモリからの読出し
回路例を示すブロック構成図、第4図及び第5図は第2
図及び第3図の動作タイムチャートである。
FIG. 1 is a block P4 diagram showing an embodiment of the memory dual write method according to the present invention, and FIGS. 2 and 3 are block diagrams showing an example of a circuit for loading into the FIFO memory and an example of a circuit for reading from the FIFO memory. The configuration diagram, Figures 4 and 5 are
FIG. 4 is an operation time chart of FIG. 4 and FIG. 3;

Claims (3)

【特許請求の範囲】[Claims] (1)、現用系と予備系から成るデータ処理システムで
あつて、それぞれの系はリフレッシュを必要とするメモ
リと、該メモリに書込み・読出しを行うプロセッサと、
これらのメモリ、プロセッサを接続するバスとにより構
成されていて、各系のメモリは非同期にリフレッシュを
行っている場合において、現用系プロセッサが現用系メ
モリにデータの書込みを行う際に同時にそのアドレスと
データを書込むためのFIFOメモリを有し、また予備
系においては該FIFOメモリに積込まれたアドレスと
データをリフレッシュサイクル以外のサイクルで予備系
メモリへ書込む回路を有し、現用系プロセッサより両系
のメモリへデータの書込みを行うことを特徴とするメモ
リ二重書き方式。
(1) A data processing system consisting of an active system and a backup system, each system including a memory that requires refreshing, and a processor that writes and reads from the memory;
These memories are composed of buses that connect the processors, and when the memory of each system is refreshed asynchronously, when the active processor writes data to the active memory, the address and It has a FIFO memory for writing data, and in the standby system, it has a circuit that writes the address and data loaded in the FIFO memory to the standby system memory in a cycle other than the refresh cycle. A memory dual write method characterized by writing data to both memory systems.
(2)、前記FIFOメモリに前記現用系メモリと同じ
書込アドレス及びデータを積込む積込み回路を、アドレ
スをラッチする第1のラッチ回路と、データをラッチす
る第2のラッチ回路と、該第1、第2のラッチ回路の出
力を多重するセレクタとにより構成し、前記予備系メモ
リへの書込み信号生成回路を、前記FIFOメモリから
出力されるアドレスをラッチする第3のラッチ回路と、
データをラッチする第4のラッチ回路とにより構成した
ことを更に特徴とする請求項(1)に記載のメモリ二重
書き方式。
(2) A loading circuit that loads the same write address and data as the active memory into the FIFO memory, a first latch circuit that latches the address, a second latch circuit that latches the data, and a loading circuit that loads the same write address and data as the active memory into the FIFO memory; 1. a selector that multiplexes the outputs of the second latch circuit;
2. The memory dual write system according to claim 1, further comprising a fourth latch circuit for latching data.
(3)、前記FIFOメモリに積込まれた前記アドレス
とデータをリフレッシュサイクル以外のサイクルで前記
予備系メモリへ書込む前記回路は、前記予備系メモリへ
の書込み信号生成回路の出力とリフレッシュ要求信号と
を競合させる競合回路を含むことを更に特徴とする請求
項(1)または(2)に記載のメモリ二重書き方式。
(3) The circuit for writing the address and data loaded in the FIFO memory to the spare memory in a cycle other than the refresh cycle is configured to output the output of the write signal generation circuit to the spare memory and a refresh request signal. The memory dual write system according to claim 1 or 2, further comprising a competition circuit for competing with.
JP1280761A 1989-10-28 1989-10-28 Memory double writing system Pending JPH03142534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1280761A JPH03142534A (en) 1989-10-28 1989-10-28 Memory double writing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1280761A JPH03142534A (en) 1989-10-28 1989-10-28 Memory double writing system

Publications (1)

Publication Number Publication Date
JPH03142534A true JPH03142534A (en) 1991-06-18

Family

ID=17629588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1280761A Pending JPH03142534A (en) 1989-10-28 1989-10-28 Memory double writing system

Country Status (1)

Country Link
JP (1) JPH03142534A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006268596A (en) * 2005-03-25 2006-10-05 Fujitsu Ltd Redundancy system of service system
JP2017532671A (en) * 2014-09-22 2017-11-02 ザイリンクス インコーポレイテッドXilinx Incorporated Memory management in multiprocessor systems.

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006268596A (en) * 2005-03-25 2006-10-05 Fujitsu Ltd Redundancy system of service system
JP4494263B2 (en) * 2005-03-25 2010-06-30 富士通株式会社 Service system redundancy method
JP2017532671A (en) * 2014-09-22 2017-11-02 ザイリンクス インコーポレイテッドXilinx Incorporated Memory management in multiprocessor systems.

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