JPH03141726A - Parity circuit - Google Patents

Abstract

PURPOSE:To make correspondence to the number of bits in an arbitrary data bit and to reduce man-hour for design by executing cascade connection to a deciding means, which is composed of a holding means to hold one bit of input data and a selecting output means, to an input in the next step. CONSTITUTION:A deciding means 9 is composed of a latch 1 to hold one bit of the input data and a selecting output means 2 to turn a first input 3 as a first output 8 while not-inverting or inverting the input corresponding to the output of the latch 1. The cascade connection is executed for the means 9 so that the number of bits in the input data and the output 8 can be connected to the input 3 in the next step. Thus, in the case of an even-number parity, when the total sum of '1' in the data bit is an even number, '0' is outputted as a parity bit and when it is an odd-number '1' is outputted as the parity bit. Similarly, in the case of an odd-number parity, the parity bit can be obtained by setting the input 3 in the initial step to '1'. Thus, since the parity circuit of regular circuit configuration can be constituted, the correspondence can be made to the number of bits in the arbitrary data bit and the man-hour for design can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parity circuit used for generating and inspecting parity pits.

[Prior Art] In the transmission of digital data, the transmission signal may be subject to interference such as noise or instantaneous interruptions depending on the condition and quality of the communication line, and errors may occur in the received data.
To this end, various methods have been used in the past, one of which is the parity check method, which is currently widely used. FIG. 2 is a block diagram of a circuit conventionally used for generating and checking parity bits in the parity check method. In this conventional example, the number of data bits is 8 bits, and latches 20 to 27 hold data bits. The number of "1" bits in the data bits is 28 to 32 exclusive NOR circuits and 35
．． 54's exclusive OR circuit determines whether the number is even or odd, and the output of 52 is "1" if the number of "1" bits is even, and "0" if it is odd. is output. Output 52 which is the result of determining whether the number of pits with "1" in the data bit is even or odd, and selection input 40 which selects and inputs "0" for even parity and "1" for odd parity. The parity bit is obtained at output 41.

[Problem to be solved by the invention] However, since the conventional circuit configuration shown in FIG. 2 does not have a regular structure on a bit-by-bit basis, the circuit configuration differs significantly when the number of data bits differs. Become something. Therefore, it is necessary to design individual circuits according to the number of data bits, which has been a major problem in reducing design man-hours.

Therefore, the present invention aims to solve such problems.

[Means for Solving the Problems] The Harrity circuit of the present invention includes a holding means for holding one pit of input data, and a first output by non-inverting or inverting a first input according to the output of the holding means. and a selection output means, which are connected in cascade such that the first output of the previous stage is connected to the first input of the next stage according to the number of bits of the input data. .

[Example] The present invention will be explained below based on the drawings. FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention. 1 is a latch which is a holding means for holding one pit in a data bit of transmitted data or received data, and an output 4 and an inverted output 5 are shown.
has. 2 is a selection output means in which a tri-state inverter 6 and a transmission gate 7 are connected in parallel between the first input 6 and the first output 8; Either transmission gate 6 or transmission gate 7 becomes active. The determination means 9 constituted by 1 and 2 have a circuit structure in units of 1 pit, and the number of determination means 9 corresponding to the number of data bits are cascaded so that the output 8 of the previous stage is connected to the input 3 of the next stage. . For example, in the case of even parity, a "0" input is input to the input 3 of the first stage. If the pit held in the latch 1 is "1", the tri-state inverter 6 in the selection output means 2 becomes active. , the input is inverted, and "1" is output to the output 8 of the first stage. Further, if the bit held in the latch 1 is "0", the transmission gate 7 becomes active, and the state "0" of the input 6 of the first stage is output as is to the output 8 of the first stage. Similarly, for the remaining data bits, the above operation is repeated using the output of the previous stage as input, and if the number of "1" bits in the data bits is even, the output of the first stage is sent to the output 8 of the final stage. input 3
Since the state of is inverted an even number of times, the state of the input of the first stage is ``
0" is transmitted as is, and if it is an odd number, it is inverted an odd number of times, so that the state "1", which is an inverted input, is transmitted. In other words, in the case of even harness, "1" in the data bit
If is an even number, rQJ is output as a parity bit, and if it is an odd number, "1" is output as a parity pit. Similarly, in the case of odd parity, input 3 of the first stage is set to "1".
By setting it to , it indicates the relationship between the input and output to be output.

Table 1 [Effects of the Invention] As described above, according to the present invention, a parity circuit having a circuit structure according to the rule f=IIJ can be constructed, so that it can accommodate any number of data bits, and the number of design man-hours is reduced. This has a significant effect on reducing

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 1...Latch which is holding means 2...Selection output means 3.
・・・・・・・・・・・・・・・First input 4・・・・・・
・・・・・・・・・Lunch output 5・・・・・・・・・
...Latch inversion output 68.・・・・・・・・・
・・・Tri-state inverter 7・・・・・・・・・
・・・・・・Transmission gate 8・・・・・・
・・・・・・・・・First output 9・・・・・・・・・
...Determination means 20-27...Latch 28-52...Exclusive NOR circuit 33,34...
・Exclusive OR circuit 35.36...in? Kuita 37.58...Logic seed circuit 39...NOR circuit 40...
......Selection input 41...
・・Output value/■

Claims (1)

[Claims] A determining means comprising a holding means for holding one bit of input data, and a selection output means for non-inverting or inverting a first input as a first output according to the output of the holding means. A parity circuit characterized in that the number of bits of data is cascaded so that the first output of the previous stage is connected to the first input of the next stage.