JPH0269022A - Counter - Google Patents

Abstract

PURPOSE:To test a counter in an extremely short time as compared with the test where the counter is tested es a whole by dividing the counter into plural divided counter sections and causing the divided counter sections to independently operate. CONSTITUTION:A whole counter section is divided into (n) pieces of counter sections 11-1n and input switching means 21--2n are respectively inserted into preceding stages of the counter sections 11-1n. The internal circuit of each input switching means 21-2n is switched between systems I and II based on control signals outputted from a control means 3. The control means 3 has at least two kinds of modes at the testing time. The control signals outputted from the control means 3 cause a 1st-stage input switching means 21 to select the system I and the means 22-2n of and after a 2nd stage to select a different system combination of the two kinds of nodes while a test is carried on. Therefore, test omission which is produced when the one piece of counter is tested in a divided state can be prevented surely and, in addition, the testing time can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a counter, and particularly to a counter having a test function.

(Prior art) The capacity of counters used in digital circuits has been increasing by increasing the length of bits in line with the increase in the capacity of other semiconductor devices. More tests will be required.

Testing of the counter is basically done by checking the output signal when the counter operates with a clock signal, but this is a 16-bit counter.

In the case of a long bit counter such as a 24-bit counter,
In order to operate the counter to the final stage.

Even a 16-bit counter requires 216 clock inputs, significantly increasing test time. For this reason,
In the case of a long bit counter, the counter 40 is divided into multiple stages and tested, as shown in FIG.

That is, in the case of a 16-bit counter, the counter 40 is divided into two 8-bit divided counter sections 401 .
402, an 8-bit counter section 40. .

A data selector 41 is interposed between 40□. When operating as an original 16-bit counter, the data selector 41 inputs the output signal of the counter section 4 (L) to the counter section 40t in accordance with the control signal CNTL.During a test, by controlling the control signal CNTL, the data selector 41 inputs the output signal of the counter section 4 (L) to the counter section 40t. A clock signal CLK is input to 4Ch and 40t, and two divided counter units 40.
．． 40□ operate independently. Two 8-bit counter sections 40. ．． If 40□ operates independently, the number of clock inputs will be 28, and the test time will be greatly shortened compared to the case where it operates as a 16-bit counter.

(Problem to be Solved by the Invention) However, when the plurality of divided counter units 40. , 40□ operate independently, the 5-division counter section 40. , 40□, and a so-called test failure occurs in this portion. As mentioned above, long-bit counters have complex structures and require more rigorous testing than counters with a small number of bits, so this missing test is a big problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a counter that reliably prevents test omissions that occur when a single counter is divided and tested, and that requires a short test time.

(Means for Solving the Problems) The counter of the present invention is a counter having a function of performing a test by dividing one counter into a plurality of divided counter sections, and each connecting section between the divided counter sections. input switching means for inputting either the output signal or the counted signal of the divided counter section in the preceding stage to the divided counter section in the subsequent stage based on the control signal, and the dividing means in the preceding stage for all input switching means. A first mode in which a control signal for inputting the output signal of the counter section to the subsequent divided counter is provided; Give a control signal to be input to.

a second operation mode in which a control signal is given to the other input switching means to input the output signal of the preceding divided counter section to the subsequent divided counter section; A control signal is applied to at least one input switching means of the input switching means other than the input switching means input to the divided counter section, and the other input switching means inputs the counted signal to the subsequent divided counter section. The control means has at least three types of operation modes including a third operation mode that provides a control signal for inputting the output signal of the divided counter section in the preceding stage to the divided counter section in the subsequent stage. The purpose is achieved.

(Operation) FIG. 1 is a block diagram showing a configuration example of a counter of the present invention.

In the counter shown in FIG. 1, the total counter section consists of n counter sections II to 1. ．． divided into.

Input switching means 21 to 27 are inserted upstream of the divided counter units II to 1□, respectively. The internal circuits of the input switching means 21 to 2 are switched between the system (2) and the system (2) based on the control signal output by the control means 3.

The first stage input switching means 21 is connected to the clock signal CL in the system 1.
The first stage divided counter section II uses K as the signal to be counted.
The input signal l5IG is inputted to the divided counter section 1. in the system ■. Enter. The input switching means 2□ to 27 in the second and subsequent stages interposed between the divided counter sections 1+-1- input the clock signal CLK as a counted signal to the subsequent divided counter sections 12 to lfi in the system ■. The front division counter section 1. The outputs O3I~OS, I of ~17-8 are input as they are to the subsequent divided counter units 1□~1, respectively.

When operating as an original counter, the control means 3 controls all the input switching means 21-2. Let the person select the system ■. This allows the 1-division counter section 1. 17 are connected in cascade and operate as one counter as a whole.

The control means 3 has at least two types of modes during testing. During the test, the control signal output from the control means 3 causes the first-stage input switching means 2° to select system I, and the second-stage and subsequent input switching means 2□ to 2n select two types of signals as shown below. Allows you to select different system combinations in the mode. Namely.

Input switching means 2□ to 2 in the second and subsequent stages select at least one system ■ in any mode, and when viewed through the first mode and second mode, select system ■ in at least one type of mode. select. In other words, the input switching means that selected system I in the first mode always selects system ■ in the second mode.

Now, as an example, in the first mode, the input switching means 2□, 24, . ...selects the system ■.

Even-numbered stage divided counter section 1□14. . . . Input switching means 2, t, 21. Suppose that ... selects system ■. Further, in the second mode, the input switching means 2□, 24 . ...selects system I.

Even-numbered stage divided counter sections 1□, 14. It is assumed that the input switching means 2 s, 2 s, . . . provided at the subsequent stage of .

In the first mode, the clock signal CLK is divided by the divided counter section 1 =, 13. . . are input to the two-division counter sections 1□, 14. ... has a counter section 11+ 13.・
Output signal from ...OS! , 053. ... are input respectively. Thus, the 1-division counter section 1. and 1□ is one counter, divided counter section 13 and 1. operates as one counter (the same applies hereafter).

In the second mode, the clock signal CLK is applied to the divided counter sections I1.1□, 14. . . are input into the 9-division counter section 1z, 14. ...'s output signal os,, o
s4. ... are input to the counter sections 1s, 1s, . As a result, the 9-division counter section 1. is one counter, divided counter 1□ section and 13 are one counter,
The divided counter units 14 and 1 operate as one counter (the same applies hereinafter).

Divided counter sections 1, ~1 in two types of modes as described above.
．． ．． If you operate and test the 4-division counter section 1. ~
Each connection between 17 is always connected in one of the modes, and no test omission occurs. The number of clock inputs required for the test is 21'×2 when the 16-bit counter is divided into four 4-bit counter sections, which is significantly reduced compared to 216 when the counter is not divided into one.

In addition, the first stage input switching means 2. is not required.

Input switching means 2. If not provided, the input signal l5IG
The divided counter section 11 may be tested using the following.

(Example) The invention will now be described with reference to examples.

FIG. 2(a) shows an embodiment of the present invention. The counter shown in FIG. 2 is a 24-bit counter, and is divided into six 4-bit counter sections Lot to 106.

Input switching circuit 20. 206 consists of two AND gates 21a, 21b and one OR gate 22, as shown in FIG. 3(a), and has input terminals A, B, control terminals C, D, and output terminal E. have. Figure 3 (
The operation will be explained with reference to the truth table shown in b).

When 0 and 1 are input to control terminals C and D, respectively, even if 1 is input to input terminal A, O is output from 21a, and A is output only when 1 is input to input terminal B.
ND gate 21b outputs 1, which is OR gate 22
It is output to output terminal E through. That is, at this time, the input to input terminal B is output to the output terminal. This becomes system ■. On the other hand, when 1.0 is input to control terminals C and D, respectively.

An input to input terminal A is output to output terminal A.

This becomes system ■. 0, 0 or 1 to control terminals C and D
, 1, respectively, does not appear in this embodiment.

The above input switching circuit 20. 206 are respectively inserted before the divided counter sections 10+ to 106, as shown in FIG. 2(a). These input switching circuits 201-2
0. In the input switching circuit 201, the input terminal A receives the input signal 15IG, and the input terminal B receives the clock signal CLK as a signal to be counted during testing.

Control signals from the control circuit 30 are input to control terminals C and D, respectively. Further, the output signal from the output terminal E is transmitted to the first stage divided counter section 10. is input.

Second and subsequent stage input switching means 20. 206, the input terminal A is connected to the previous stage divided counter section 10. The output signal 0SI-oss from ~10s is inputted, the clock signal CLX as a counted signal is inputted to the input terminal B, and the control signal from the control circuit 30 is inputted to the control terminals C and D, respectively. Output terminal E of input switching circuit 20□~20°
The output signal from the second and subsequent stage divided counter sections 10□~
10. are input respectively.

The control circuit 30 includes an AND gate 31, two NOT gates 32a, 32b, and four EXCLUSIVE-ORs.
Gate (hereinafter abbreviated as EX-OR gate) 3
It consists of 3a, 33b, 33c, and 33d. Control circuit 30
Two types of signals T,, T! Of these, signal T
, are the control terminals of the input switching circuit 201, and are input to the NOT gate 32a and the AND gate 31. NOT
The output of the gate 32a is the control terminal C of the input switching circuit 20.
and EX-OR gates 33a, 33b.

33c and 33d, respectively. The output of the AND gate 31 is input to the NOT gate 32b, and is also input to the input switching circuits 20z, 204, 206 (D control terminal,
It is input to EX-OR gates 33a and 33c. The output of NOT gate 32b is input switching circuit 20□,
20. ．． 20. control terminal C and EX-OR gate 33
b, 33d Constant input. EX-OR gate 33a,
The outputs of 33b, 33c, and 33d are respectively connected to input switching circuits 20. control terminals C, D, input switching circuit 20. It is input to control terminals C and D of.

The operation of the counter shown in FIG. 2(a) will be explained below with reference to the truth table shown in FIG. 2(b).

When the signal T1 input to the control circuit 30 is 0.

Nets 34a, 34b, regardless of the level of signal T2.
The signal at 34c becomes 1.0.1. the result,
Input switching circuit 20. , 20. , 204.20. 1.0 is input to control terminals C and D, respectively. Input switching circuit 2oz.

20, EX-OR gates 33a, 33c
Since a set of inputs of 0.1 is input to each of the EX-OR gates 33b and 33d, and a set of inputs of 1.1 is input to both of the EX-OR gates 33b and 33d, 1.1 is input to the control terminals C and D. 0 is input respectively. 1 to control terminals C and D. When O is inputted, the signal from the input terminal A is outputted to the output terminals of the input switching circuits 20□ to 206. In other words, system ■ is selected. As a result, six divided counter sections 10. ~10& are cascaded.

It operates as a normal 24-bit counter in response to input signal l5IG.

The test is performed when signal T1 is 1. That is, when the signal T1 is 1 and the signal T2 is O, NET) 34a.

The signals at 34b and 34c become 0 and 0.1, respectively. As a result, the input switching circuit 20. In this case, 0 and 1 are input to control terminals C and D, respectively. Input switching circuit 20. , 20. , 20. In this case, 1 is connected to control terminals C and D.
．． 0 is input respectively. Input switching circuit 203゜20
, in the case of smell, EX-OR gate 33a, 33
A pair of inputs of 0 and 0 in c is also an EX-OR game) 33b
, 1 on 33d. Since each set of 0 inputs is input, 0.0 is input to control terminals C and D. 1 is input respectively.

An input switching circuit 20 in which 0.1 is input to control terminals C and D, respectively. ．． 20. ．． At 20s, the clock signal CLK input to the input terminal B is output from the output terminal E, and the clock signal CLK is output from the output terminal E to the divided counter section 101. Lot, input in 10s. That is, system I is selected. control terminal C,
Input switching circuit 20□, in which 1.0 is input to D, respectively.
20. ．． 20. , the signal input to input terminal A is output from output terminal E, so the 9-division counter section 1
0+, 10+, 10s output signal OSI, O5
:1. O3S is a counter section 10z in the latter stage, respectively.
10. , 10. is input. In other words, system ■ is selected. Thus, the 1-division counter section 10. and 10□2
Divided counter section 10. and 104. The divided counter sections 10s and 1O4 are each connected to form one 8-bit counter, and a test is performed. The above is the first
This is a mode test.

When the test in the first mode is completed, the signal T2 is switched to 1 while the signal T1 remains 1. As a result, the signals at the nets 34a, 34b, and 34c become 0.1°O, and the signals input to the control terminals C and D are as follows.

In the input switching circuit 201, 0, 1 . Input switching circuit 2
0□, 204.206 is also 0.1. In the input switching circuits 203 and 205, a set of inputs of 0.1 is input to both EX-OR gates 33a and 33c, and a set of inputs of 0,0 is input to both EX-OR gates 33b and 33d. Therefore, the control terminal C,
1.0 is input to each D, and system ■ is selected.

(Then, the 1-divided counter sections 10. and 10b each have 1 counter, and the divided counter sections 10□ and 103 have 1 counter.
8-bit counters, divided counter sections 104 and 10
．． operates as one 8-bit counter. The above is the test in the second mode.

After the test in the first mode is completed, if the test is performed by switching to the second mode, the two-division counter sections 10, -10.
Since each connection point is always connected in one of the modes, no test omissions occur. The number of clock inputs required for the test is 2a times in the first mode and 2a times in the second mode.

The total was only 2@X2 = 29 times.

Although the above-described embodiment is an example in which a 24-bit counter is divided into six, the length of the counter and the number of division stages are not limited to this embodiment. Further, although there are two types of test modes, three or more modes may be used. The input switching circuit and the control circuit can also be constructed from logic circuits other than those shown in the above embodiments.

(Effects of the Invention) By dividing the counter into a plurality of divided counter sections and operating them independently, the counter of the present invention can be tested in a much shorter time than testing by operating the counter as a whole. Moreover, it is possible to reliably prevent test omissions, which are a problem when performing tests in independent operations, and is highly effective in improving counter test efficiency and quality.

Figure 1 is a block diagram showing an example of the configuration of a counter according to the present invention, and Figures 2 (a) and (b) are circuit diagrams showing the configuration of an embodiment of the present invention, respectively. 3(a) and Φ) are a circuit diagram showing the configuration of the input switching circuit used in the embodiment and a truth table showing its operation, and FIG. 4 is a conventional example. FIG.

1, ~1. %, 101-10. ...Divided counter section,
2+ to 27... Input switching means, 3... Control means, 2
0. ~20. ...Input switching circuit, 30...Control circuit.

Figure 3 <a>

Claims (1)

[Claims] 1. A counter having a function of performing a test by dividing one counter into a plurality of divided counter parts, the counter having a function of performing a test by dividing one counter into a plurality of divided counter parts, the counter having a function of performing a test by dividing one counter into a plurality of divided counter parts, the counter being provided with a control signal at each connection part between the divided counter parts. input switching means for inputting either the output signal or the counted signal of the previous-stage divided counter section to the subsequent-stage divided counter section based on a first mode for providing a control signal to be input to the divided counter of at least one of the input switching means;
A control signal is given to one input switching means to input the counted signal to the subsequent divided counter section, and the other input switching means inputs the output signal of the previous divided counter section to the subsequent divided counter section. at least one input switching means out of the input switching means excluding the input switching means for inputting the counted signal to the subsequent divided counter section in the second operation mode; A control signal is given to input the counted signal to the divided counter section in the subsequent stage, and a control signal is given to the other input switching means to input the output signal of the divided counter section in the former stage to the divided counter section in the subsequent stage. A counter comprising a control means having at least three operating modes including a third operating mode.