JPH03141669A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption while no chip is selected or a chip is on standby by connecting the discharge or charge path of an oscillator circuit with a resistor circuit composed of a series circuit of MOSFETs. CONSTITUTION:A back-bias generator includes a second generator Vbb-G2 that includes a resistor circuit RIG. The threshold voltage of n-channel MOSFETs Qr1-Qrn in the circuit RIG is steplessly adjusted according to the magnitude of the back bias voltage-Vbb. The back bias voltage -Vbb is converged without the intermittent operation of the second generator resistor circuit RIG. To make the operating interval of an oscillator OSC relatively short, therefore, there is no need for abrupt application of charge to the substrate, and circuit parameters do not have to be predetermined. As a result, power consumption can be reduced while a chip is not selected or is on standby.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit and a substrate back bias voltage generation circuit included therein.
The present invention relates to a technique that is effective when applied to AM, pseudo-static RAM, and the like.

[Prior art]

In a semiconductor integrated circuit composed of MOSFET (insulated gate field effect transistor), MOS FE
In order to reduce the parasitic capacitance between a circuit element such as T and a semiconductor substrate, there is a technique of generating a substrate back bias voltage using a built-in substrate bias generation circuit. With this technology, the power supply voltage to be supplied to semiconductor integrated circuits can be reduced to 5
can be converted into a voltage such as v, and the parasitic M
Malfunctions can be prevented by increasing the gate threshold voltage of the OS transistor.

A conventional substrate bias generation circuit includes an oscillation circuit such as a ring oscillator and a charge pump circuit that rectifies the periodic signal generated by this oscillation circuit, and adjusts the substrate bank bias voltage according to the oscillation frequency of the oscillation circuit. occurs.

By the way, the current flowing through the board is significantly different between the chip selection state in which the internal circuits start operating all at once and the chip non-selection state or standby state in which the internal circuits hardly operate. If a common substrate bias generation circuit is operated regardless of the state, the same operation will be performed even in the chip non-selected state as in the chip selected state, resulting in an increase in power consumption.

Therefore, as described in Japanese Patent Laid-Open No. 61-59688, a technique has been proposed in which the operation of the oscillation circuit is controlled to start and stop intermittently depending on the level of the substrate back bias voltage.

[Problem to be solved by the invention]

However, in the conventional technology that performs intermittent control in which the operation of the oscillation circuit is completely stopped and restarted depending on the substrate back bias voltage, charge must be suddenly supplied to the substrate when the operation is restarted intermittently. Therefore, the present inventor found that it is necessary to set the circuit constants in advance so that the operating cycle of the oscillation circuit is relatively short. In particular, in battery-backed semiconductor integrated circuits such as pseudo SRAMs, which are characterized by high power consumption, low power consumption during standby is essential.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that can steplessly control the oscillation frequency according to the substrate back bias voltage, thereby reducing power consumption when a chip is not selected or during standby. be.

The above and other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor integrated circuit including a substrate back bias circuit including an oscillation circuit whose oscillation period is determined according to a time constant of a charging path or a discharging path of a predetermined node and a charge pump circuit, the oscillation circuit A resistor circuit in which MOSFETs whose mutual conductance decreases as the absolute value of the generated substrate back bias voltage increases is connected in series in multiple stages is coupled to the discharge path or the charging path.

[For production]

According to the above means, a large number of MOs included in the resistance circuit
The threshold voltage of the SFET is controlled steplessly according to the level of the back bias voltage due to its substrate effect, and as the absolute value of the back bias voltage increases, the threshold voltage of the MOSFET increases and the oscillation circuit The CR time constant of the charging path or discharging path increases, which lengthens the oscillation period of the oscillation circuit and acts to reduce the absolute value of the back bias voltage, and conversely the absolute value of the back bias voltage decreases. As the threshold voltage of the MOSFET becomes smaller, the CR time constant of the charging path or discharging path of the oscillation circuit decreases, which shortens the oscillation period of the oscillation circuit and increases the absolute value of the back bias voltage. act. In this way, the substrate back bias circuit attempts to converge the substrate back bias pressure to a predetermined value without intermittently stopping/resuming its operation, so unlike the conventional technology, charges are suddenly supplied to the substrate. Since it is not necessary, it is possible to avoid the restriction that circuit constants must be set in advance so that the operating cycle of the oscillation circuit is relatively short.
As a result, power consumption can be reduced in the chip non-selected state or standby state.

Here, when the MOSFET included in the resistance circuit is constituted by an N-channel type MO5FET.

It is desirable to increase the fluctuation in threshold voltage due to the substrate effect for the MO3FET, and in that case, separate it from other N-channel MO3FETs and separate the MOSFET.
It is desirable to form the ET in a dedicated P-type well region into which impurities are introduced at a high concentration. When a resistor circuit is placed in the charging path, it is preferable to separate it from other P-channel type MO3FETs and form it in a dedicated N-type well region doped with impurities at a high concentration.

In order to simplify the configuration of the substrate back bias circuit including the resistor circuit, it is desirable to bias the gate electrode of the MOSFET included in the resistor circuit with a constant voltage.

〔Example〕

FIG. 2 shows a circuit block diagram of an embodiment of a pseudo-static RAM to which the present invention is applied. The circuit elements constituting each block in the figure are manufactured using CMO8 (complementary MO8) manufacturing technology.

It is formed on a single semiconductor substrate such as single crystal silicon. In the figures below, the MOSFET with an arrow added to the channel (back gate) part is a P-channel type, and is displayed to be distinguished from the N-channel MO8FET with no arrow added.

The pseudo-static RAM of this embodiment has a memory array composed of so-called one-element dynamic memory cells, thereby achieving higher circuit integration and lower power consumption. In addition, the X address signals AXO to AXi
and Y address signals AYO to AYj are input via separate external terminals, and chip enable signal CE, write enable signal WE, and output enable signal ○E are provided as control signals, making it compatible with ordinary static RAM. It has specific input/output interface conditions. The pseudo-static RAM further has a built-in refresh control circuit RFC, and has a self-refresh function that autonomously performs a refresh operation unique to dynamic memory cells. As a result, the pseudo-static type RAM of this embodiment can be used as a relatively expensive bipolar type RAM as long as its access time is not a problem.
It can be used in place of M or CMOS static type RAM.

In the pseudo-static RAM of this embodiment, the refresh control circuit RFC is a refresh address counter RCTR, as will be described later.

It includes a refresh timer circuit RTM and a refresh timing generation circuit RTG. The refresh control circuit RFC receives a refresh control signal R via an external terminal.
FSH is supplied. This refresh control signal RFS
When H is repeatedly changed from a high level to a low level at a predetermined period, the pseudo-static RAM is subjected to an auto-refresh cycle. In this auto-refresh cycle, the refresh control circuit RFC increments the refresh address counter RCTR one by one in accordance with the refresh control signal RFSH to perform a refresh operation for each word line. On the other hand, when the refresh control signal RFSH is kept at a low level for a predetermined period or longer, the pseudo-static RAM enters a self-refresh cycle. In this self-refresh cycle, the refresh control circuit RFC.

A series of refresh operations regarding all word lines is periodically executed according to a timing signal for activation supplied from the refresh timer circuit RTM.

In FIG. 2, the memory array M-ARY has a two-intersection (folded bit line) system, although it is not particularly limited, and has n+1 sets of complementary data lines Do arranged in the horizontal direction of the figure.
-Do~Dn-Dn and m+1 arranged in the vertical direction
(n+1)X (
m+1) memory cells.

Each memory cell of the memory cell array M-ARY is a so-called one-element dynamic memory cell, and each memory cell has an information storage capacitor Cs and an address selection M O
It is composed of S F E T Q m.

m+1 arranged in the same column of memory array M-ARY
MO3FE TQ for address selection of memory cells
The drain of m is connected to the corresponding complementary data line DO-DO”D
They are alternately coupled to n-Dn non-inverted signal lines or inverted borrowing lines with a predetermined regularity.

Also, MO8FETQ for address selection of n+1 memory cells arranged in the same row of the memory array M-ARY
The gates of m are each commonly coupled to the corresponding word line WO=W m. A predetermined self-plate voltage is commonly supplied to the other electrode of the information storage capacitor Cs of each memory cell, that is, the cell plate.

Word lines WO to Wm forming memory array M-ARY
is coupled to the row address decoder RDCR and is alternatively brought into a selected state.

The row address decoder RDCR receives a complementary internal address signal axo-axi of i+1 pin 1- from a row address buffer RADB, which will be described later. axO (the same applies hereafter) is supplied.

Further, a timing signal φX is supplied from the timing generation circuit TO. The timing signal φX is normally set to a low level, and is set to a high level at a predetermined timing when the pseudo-static RAM is brought into a selected state in a normal operation mode or a refresh mode.

The row address decoder RDCR is selectively brought into operation by the timing signal φX set to high level. In this operating state, the row address decoder RDCR outputs the complementary internal address signals aXO to axi.
is decoded, and one corresponding word line is alternatively set to a high level selection state.

Row address buffer RADB receives and holds a row address signal transmitted from address multiplexer AMX. Furthermore, the complementary internal address signals axO to axi are formed based on these row address signals.

One input terminal of the address multiplexer AMX has
An i+1-bit X address signal AXO-AXi is supplied via external terminals AXO-AXi. Further, the other input terminal of the address multiplexer AMX is supplied with an i+1-bit refresh address signal r from a refresh control circuit RFC, which will be described later, although it is not particularly limited.
xo to rxi are supplied. Address multiplexer A
MX is further supplied with a timing signal φref from a timing generation circuit TG. timing signal φre
f is set to a low level when the pseudo-static RAM is placed in a normal write or read operation mode, and set to a high level when placed in an auto-refresh or self-refresh mode.

The address multiplexer AMX selects the X address signal AXO=AXi supplied via the external terminal AO=A i in normal memory access when the timing signal φref is at a low level, and selects the X address signal AXO=AXi as the row address signal. Transfer to address buffer RADB. Furthermore, in each refresh mode in which the timing signal φref is at a high level, the refresh address signal rx supplied from the refresh control circuit IRFC is
O-rxi is selected and transmitted as a row address signal to the row address buffer RADB.

On the other hand, complementary data lines Do-DO''Dn-Dn forming memory array M-ARY are coupled at one end to a corresponding unit amplifier circuit USA of sense amplifier SA.

The sense amplifier SA is composed of n+1 unit amplifier circuits USA. Each unit amplifier circuit U of sense amplifier SA
SA includes P-channel MOSFETs QIO, Qll and N-channel MOSFETs MO8, as exemplarily shown in FIG.
FETQ30. The basic configuration is a CMOS latch circuit consisting of Q31.

The input/output nodes of these latch circuits are respectively coupled to the non-inverted signal line and the inverted signal line of the corresponding complementary data lines Do-Do to Dn-Dn. In addition, the unit circuit of the sense amplifier SA is supplied with the power supply voltage Vcc of the circuit via a P-channel drive MO5FETQ9, although it is not particularly limited, and a circuit power supply voltage Vcc is supplied to the unit circuit of the sense amplifier SA via a P-channel drive MO3FE
The ground potential of the circuit is supplied via TQ29.

Drive f! A timing signal φpa is supplied to the gate of IJMO3FETQ29 from a timing generation circuit TG. Further, an inverted signal of the timing signal φpa by the inverter circuit N5 is supplied to the gate of the drive MO8FETQ9. The timing signal φpa is normally set to a low level 1, and this pseudo-static RAM is placed in a selected state, and the minute read signal output from the memory cell coupled to the selected word line is established on the corresponding complementary data line. It is considered to be at a high level. By setting the timing signal φpa to a high level, the drive MO8F
Both ETQ9 and Q29 are turned on, and all n+1 unit amplifier circuits USA of the sense amplifier SA are put into operation.

In its operating state, each unit amplifier circuit USA of the sense amplifier SA has n+1 connected to the selected word line.
Complementary data lines DO and DO~ from each memory cell
The minute read signals outputted via Dn-Dn are respectively amplified and made into binary read signals of high level or low level. These binary read signals are rewritten into the corresponding memory cells when the pseudo-static RAM is placed in a read mode or in each refresh cycle, and a refresh operation of stored data is performed. In other words,
By selectively setting the word IX W OW - W m to a high level selection state and activating the unit amplifier circuits USA of the sense amplifiers SA all at once, a refresh operation of the dynamic memory cell can be realized. .

Complementary data line Do- forming memory array M-ARY
Do-Dn-Dn, on the other hand, is coupled to the corresponding switch MO8FET of column switch C8W. Column switch C8W connects complementary data line Do-Do-
n+1 pair of switches M provided corresponding to Dn-Dn
O3FETQ36, Q37~Q38. It is composed of Q39.

One of these switches MO3FET is coupled to the corresponding complementary data line, and the other is commonly connected to the non-inverted signal line CD and the inverted signal line CD of the complementary common data line, respectively. The gates of each pair of MO8FET switches are connected in common, and the column address decoder CDC
Corresponding data line selection signals YO=Yn are supplied from R, respectively.

As a result, each pair of switches MO8FET constituting the column switch C8W is turned on by the corresponding data line selection signals YO to Yn being alternatively set to high level, and a specified set of complementary data is selected. selectively connect the line and the common complementary data line CD-CD.

The column address decoder CDCR is supplied with a j+1-bit complementary internal address signal a y O= a 3/ j from a column address buffer CADB, which will be described later.
Further, a timing signal φy is supplied from a timing generation circuit TG. The timing signal φy is normally set to a low level, and is set to a high level when the pseudo-static RAM is selected and the amplification operation by the sense amplifier SA is completed.

The column address decoder CDCR is selectively brought into operation when the timing signal φy is set to a high level. In this operating state, the column address decoder CDCR outputs the complementary internal address signals ayo
-ayj is decoded, and the corresponding data line selection signal YO-Yn is alternatively set to high level.

Column address buffer CADB is connected to external terminal AYO-
It takes in and holds the Y address signal AYO-Ayj of j+1 pips I~ supplied via AYj. Furthermore, the complementary internal address signals ayo to ayj are formed based on these Y address signals AYO to AYj.

Complementary common data, IcD-CD, main amplifier MA
The input terminals of the data buffer DIB are coupled together, and the output terminal of the data manual buffer DIB is coupled thereto. The output terminal of main amplifier MA is further coupled to the input terminal of data output buffer DOB, and the output terminal of data output buffer DOB is coupled to data input/output terminal DIO. The input terminal of data manual buffer I) r B is also the above data input/output terminal DI.
Commonly connected to O.

Main amplifier MA is selectively brought into operation according to timing signal φma supplied from timing generation circuit TG. In this operating condition.

Main amplifier MA further amplifies the binary read signal outputted from the selected memory cell of memory array M-ARY via the corresponding complementary data line and complementary common data line CD-CD, and outputs it to data output buffer DOB. introduce.

The data output buffer DOB is a pseudo-static type RA
When M is placed in the read operation mode, it is selectively brought into operation according to the timing signal φr supplied from the timing generation circuit 1'G. In this operating state, the data output buffer DOB transfers the memory cell read signal transmitted from the main amplifier MA to the data input/output terminal DIO.
The data is sent to an external device via the .

When the dynamic RAM is in the write operation mode, the data driver cover sofa DIO uses the timing generation circuit T.
It is selectively activated from G.

In this operating state, the data person Capaffa DIO:
The write data supplied via the data input/output terminal DIO is used as a complementary write signal, and the complementary common data line CD-CD
supply to.

As mentioned above, the refresh control circuit RFC includes a refresh timer circuit RTM, a refresh address counter RCTR, and a refresh timing generation circuit R.
Contains TG. As described later, the refresh control circuit RFC selectively executes an auto-refresh cycle or a self-refresh cycle in accordance with a refresh control signal RF SH supplied via an external terminal.

In each refresh cycle, the refresh control circuit RFC supplies the timing generation circuit TG with a timing signal φrs for starting a refresh operation.

The timing generation circuit TG receives the timing signal φrs.
Accordingly, various timing signals necessary for refresh operations are formed and supplied to each circuit. Furthermore, every time the refresh operation for one word line is completed, a timing signal φre is supplied to the refresh control circuit RFC. This timing signal φre is used as a count pulse for incrementing the refresh address counter RCTR6.
, write enable signal WE and output enable signal O
Based on E, the various timing signals mentioned above are formed and supplied to each circuit. In addition, the refresh control circuit RFC
According to the timing signal φrs supplied from the circuit, various timing signals necessary for the refresh operation are formed and supplied to each circuit. Furthermore, the timing generation circuit TG.

When the refresh operation for one word line is completed, a timing signal φre is formed and supplied to the refresh control circuit RFC.

A substrate back bias circuit (hereinafter also simply referred to as a substrate bias generation circuit) Vbb-G is a circuit such as +5■ that is applied between a power supply terminal Vcc and a reference potential terminal (or ground terminal) GND, which constitute an external terminal of an integrated circuit. It is operated by a positive power supply voltage and outputs a negative bias voltage.

The bias voltage output from the substrate bias generation circuit Vbb-G is supplied to the MO3FETQm in the memory array and the semiconductor region serving as the substrate gate of the MOSFET constituting the illustrated circuit block.

Although not particularly limited, the CMO5 integrated circuit of this embodiment is formed on a semiconductor board made of single-crystal P-type silicon. An N-channel MO3FET such as MO3FETQm in the memory array M-ARY has a source region and a drain region formed on the surface of the semiconductor substrate, and a thin gate insulating film on the surface of the semiconductor substrate between the source region and the drain region. It consists of a gate electrode made of polysilicon formed through a polysilicon layer. P Chacinet 9M
The O3FET is formed in an N-type well region formed on the surface of the semiconductor substrate. This allows the semiconductor substrate to
It constitutes the base gate of a plurality of N-channel MO8FETs formed thereon.

The N-type well region has a P-channel M formed thereon.
Configures the base gate of O5FET. P Chacine 9MO
The base gate or N-type well region of the 3FET is
It is coupled to the power supply terminal Vcc in the figure.

Although not shown in the drawings, the CMO3 integrated circuit of this embodiment includes a surface portion of the main surface of the semiconductor substrate other than the surface portion to be used as an active region, that is, a surface portion where MOSFETs, MOS capacitors, semiconductor wiring regions, etc. are to be formed. The other surface portions are covered with a relatively thick field insulating film. The required wiring layer extends over the field insulating layer or extends over the active region through the insulating layer.

According to this structure, the back bias voltage -vbb output from the substrate bias generation circuit vbb-G is supplied to the body gate of the N-channel MOSFET formed on the surface of the semiconductor substrate.

The back bias voltage reduces the junction capacitance formed by the PN junction between the source/drain region of the 5N channel MO3FET and the semiconductor substrate and the junction capacitance formed by the PN junction between the semiconductor wiring region and the semiconductor substrate. Correspondingly, the integrated circuit can operate at high speed because the parasitic capacitances that limit its operating speed are reduced.

MOSFETs such as the address select MO8FET often produce leakage current even when it is turned off. The threshold voltage of this MOSFET is appropriately increased by the substrate bias effect when the back bias voltage -vbb is applied, and thereby,
Such leakage current is reduced. Address selection MO3FE
As a result of the reduced leakage current in T, the retained charge in the information storage capacitor Cs will be retained for a relatively long period of time.

In an integrated circuit, a structure consisting of a field insulating film and wiring such as signal wiring extending over it is a parasitic MOS.
It is considered to form part of the FET structure. The back bias voltage -vbb increases the threshold voltage of the parasitic MO3FET and prevents the parasitic MO8FET from operating.

The substrate bias generation circuit Vbb-G periodically generates a bias voltage by a charge pump action using a capacitor, as will become clear from the description later. This back bias voltage is smoothed by parasitic capacitance and stray capacitance that exist between the semiconductor substrate to which it is applied, the power supply wiring, and the semiconductor region.

The back bias voltage is reduced by leakage currents such as those generated between the source/drain regions of the MOSFET and the semiconductor substrate.

Here, leakage current to the semiconductor substrate is not necessarily constant and is influenced by circuit operation. This leakage current is
It is relatively small if the switch state of the MOSFET is not changed and remains fixed or stationary, such as in the chip non-selection state or standby state. On the other hand, this leakage current is caused by the MOS
If the switch state of the FET is changed, it will be increased accordingly. If necessary, please refer to John Willey and Sons (1981) regarding the mechanism of leakage current generation to the board.
Published by S.Y & 5ons), S.M.S.
, M, 5ze), Physics of Semiconductor Devices.

f semiconductor devices
), pages 480 to 487.

In the pseudo SRAM shown in Fig. 2, the substrate leakage current is
Timing control circuit TC, address buffer, decoder based on chip enable signal CE, output enable signal OE, etc.

When a circuit such as a sense amplifier is operated, it is increased accordingly.

According to this embodiment, the substrate bias generation circuit Vbb-a
In order to maintain the substrate bias potential at an appropriate value even when the substrate leakage current increases in the chip selection state, the first generating circuit Vbb has a relatively large current driving capability. -01 and a second generating circuit Vbb-02 with the minimum current driving capability required in the chip non-selection state or standby state.
It is equipped with In this way, by selectively using both circuits depending on the operating state of the pseudo SRAM, power consumption is reduced.

Although not particularly limited, according to this embodiment, the first generation circuit Vbb-0 in the substrate bias generation circuit Vbb-G
The operating states of the first generation circuit Vbb-G2 and the second generation circuit Vbb-G2 are controlled based on the control signal φQe and the refresh control signal φref output from the timing control circuit TG based on the chip enable signal CE. That is, when the chip enable signal CE is asserted to low level and is in the chip state, and the refresh control signal φref
When a refresh operation is instructed by
Operation b-02 is selected.

FIG. 1 shows an example of the second generation circuit Vbb-02 included in the substrate bias generation circuit Vbb-G.

The second generation circuit VBB-02 shown in the figure includes an oscillation circuit O8C and a CMO circuit that shapes and amplifies the output waveform of the oscillation circuit O8C.
An amplifier circuit AMP consisting of an S inverter circuit INVa and a charge pump circuit PUMP functioning as a rectifier circuit
It consists of

The oscillation circuit ○SC is operated by the power supply voltage Vcc,
For example, an odd-numbered CMOS inverter circuit INVI~IN
It is configured as a ring oscillator configured by coupling Vi in a ring shape.

The charge pump circuit PUMP includes a charge pump capacitor C1, and a gate electrode thereof which operates as a rectifying element, and a drain electrode thereof (depending on the polarity of the applied voltage, it may act as a drain electrode or a source electrode). N-channel MO5FETs Q40 and G4 (referred to as drain electrodes for convenience)
Consists of 1. Although not particularly limited, the capacitor C] is.

By making the structure similar to an N-channel MO8FET, it has a MOS capacitor structure.

One electrode of the capacitor C1, that is, the electrode corresponding to the gate electrode of the MOSFET, is coupled to the output terminal of the CMOS inverter circuit INVa. The other electrode of the capacitor C1, that is, the electrode corresponding to the source or drain electrode of the MOSFET, is MO8FETQ40.
and G41 are connected to the common connection point.

MO8FETQ40 as a rectifying element has a capacitor C
The MO8FETQ41 is provided between the other electrode of 1 and the ground point GND of the circuit, and the MO8FETQ41 is provided between the other electrode and the substrate bias electrode pad PAD. This electrode pad PAD is electrically connected to a semiconductor substrate or the like, and supplies a substrate bias voltage -vbb. Note that a parasitic capacitance cb (not shown) exists between this substrate and the ground potential point of the circuit, which substantially holds a back bias voltage.

The diode-type MO3FET Q40 is turned on when the oscillation pulse is at a high level (power supply voltage Vcc). Thereby, the capacitor C1 is precharged by the output high level. When the oscillation pulse is set to a low level (ground potential of the circuit), the other electrode of the capacitor C1 has a negative potential of -(Vcc-Vth). Here, Vth is the threshold voltage of MO5FETQ40. Due to this negative potential, the MO in diode form
The 3FET Q41 is turned on and applies a negative potential to the parasitic capacitance cb. As a result, a substrate bias voltage of -vb b is applied to the substrate and the like.

The current supply capability of the second generation circuit Vbb-G2 is substantially the same as the capacitance of the capacitor C1 and the oscillation circuit O8C.
is determined by the oscillation frequency of That is, the amount of charge injected into the semiconductor substrate or the like in response to one oscillation output pulse increases as the capacitance of the capacitor C1 increases. Furthermore, the number of times that charges are injected into the semiconductor substrate or the like per unit time increases as the oscillation frequency of the oscillation circuit SC increases.

According to this embodiment, the second generating circuit Vbb-02 only needs to have a relatively small current supply capacity that can compensate for the leakage current flowing to the substrate in the chip non-selected state or standby state. It has become. That is, the configuration is such that it exhibits low power consumption characteristics while ensuring the required relatively small current supply capability. The oscillation frequency of the oscillation circuit O8C is determined by setting an appropriate number of CMOS inverter circuits constituting the oscillation circuit and appropriately setting the signal delay characteristics of each, for example, 1.
to a relatively low value such as 2 MHz. The capacitance of capacitor C1 is set to a relatively small value.

Here, the power consumption in the oscillation circuit SC is proportional to the oscillation frequency. In other words, the operating current or current consumption of each CMOS inverter circuit constituting the oscillation circuit ○SC is similar to that of a well-known CMOS inverter circuit. It is proportional to the so-called transient current required for charging and discharging the inverter circuit (consisting of the input capacitance, etc.), and is substantially is 0. Since the transient current of each CMOS inverter circuit is proportional to the operating frequency, the power consumption of the low oscillation frequency oscillation circuit SC is originally smaller than that of the first generation circuit vbb-61.

Furthermore, this oscillation circuit ○SC can autonomously control its oscillation frequency according to the back bias voltage level,
This is intended to reduce the power consumption of the negative layer. This will be explained in detail below.

The output terminal of the CMOS inverter circuit INV2 included in the oscillation circuit O8C and the CMOS inverter circuit INV3
A capacitor C2 as a capacitive element having a predetermined capacitance is arranged between the input terminal and the input terminal of the capacitor C2. Although not particularly limited, this capacitor C2 may be an N-channel type MO
It is formed by the gate capacitance of a 3FET, or the capacitance of a structure in which a thin oxide film formed on a silicon substrate is covered with a metal electrode. One electrode of capacitor C2 is coupled to the circuit ground potential, and the other electrode is connected to node N1.
As output terminal of CMOS inverter circuit INv2 and C
It is coupled to the input terminal of the MOS inverter circuit INV3. Between the source electrode of the N-channel type MO5FET Q42 constituting the CMOS inverter circuit INV2 and the ground potential of the circuit, there is a resistor circuit R including N-channel type MO3FETs Qr 1 to Qrn connected in series in multiple stages.
EG is placed.

The P-channel MO8FET Q43 in the CMOS inverter circuit INV2 constitutes a charging path for charging the capacitor C2 to the power supply voltage Vcc, and
Said MOSFETQ42 and MO3FETQr 1-Q
r n constitutes a discharge path of capacitor C2. The CMOS inverter circuit INV3 whose input terminal is coupled to the node N1 functions as a level determination circuit that determines the level of the node N1 using a predetermined logical threshold.

CMOS inverter circuits I NV4 to I coupled between the output terminal of the CMOS inverter circuit INV3 and the input terminal of the CMOS inverter circuit INV2;
NVI functions as a reset circuit for charging capacitor C2 and initializing the voltage level of node N1 to power supply voltage Vcc.

Incidentally, an N-channel MOS F E whose gate electrode is coupled to the output terminal of the CMOS inverter circuit INV3 is used.
T Q 44 C, the CMOS inverter circuit INV
After the output level of C2 is inverted to a high level, the capacitor C2 is rapidly discharged to prevent malfunctions due to power supply noise or to expand the noise margin.

Here, before proceeding with the explanation of the resistance circuit REG, the basic operation of the oscillation circuit SC will be explained.

When the output of the CMOS inverter circuit INVI is set to a low level, the MO3FET Q43 is turned on in synchronization with this, and the node N1 is charged to a high level via the capacitor C2.

This state inverts the output signal of the inverter circuit INVI to a high level. As a result, the node N1 is gradually discharged via the MO8FET Q42 in the on state and the resistor circuit REG, and the level N1 becomes the level of the CMOS inverter circuit IN.
When the voltage is lowered to below the logical threshold voltage of V3, the output of the CMOS inverter circuit INV3 that detects this is inverted. This output change is sequentially fed back to the CMOS inverter circuit INV2, and the node N1 is charged to the initial level again. In this way, the charging and discharging operations for the node N1 are repeated, causing oscillation, and a pulse signal having a cycle corresponding to the oscillation cycle is applied to the charge pump circuit PUMP via the amplifier circuit AMP.

The period of this pulse signal is the CR time constant when the initial potential of the node N1 is discharged and the CMOS
The resistance component of the CR time constant τ is determined exclusively by the logic threshold voltage of the inverter circuit INV3, and the resistance component of the CR time constant τ is determined by the logic threshold voltage of the inverter circuit INV3.
It is determined by the on-resistance of FETQ42 and the resistance value of resistance circuit REG.

Here, MO5FETQr included in the resistance circuit REG
The gate electrodes l to Qrn are biased by a bias circuit VB, and a reference conductance is set for them. Furthermore, M O included in the resistance circuit REG
S F E T Q r 1 to Q rn and MOSF
Back bias voltage -v is applied to the back gate of ETQ42.
bb is now supplied. Thereby, the conductance of these MOSFETs is autonomously controlled by the substrate effect according to the back bias voltage -vbb. That is, a large number of MOSFETs included in the resistance circuit REG
The threshold voltages of Qr1 to Qrn are controlled steplessly according to the level of the back bias voltage -vbb due to the substrate effect, and as the absolute value of the back bias voltage -bb increases, the MOS F E T Q r1~Qr
The threshold voltage of n increases, and the CR time constant of the discharge path of the oscillation circuit O8C increases, which causes the oscillation circuit ○S
The oscillation period of C becomes longer and the back bias voltage -vbb
acts to reduce the absolute value of Conversely, as the absolute value of the back bias voltage -Vbb decreases, the MO8FE
The threshold voltages of TQr1 to Qrn become smaller and the CR time constant of the discharge path of the oscillation circuit O8C decreases, which shortens the oscillation period of oSC and lowers the back bias voltage -
It acts to increase the absolute value of vbb. In this way, the second generating circuit Vb of the substrate bias generating circuit vbb-G
Since the b-G2 attempts to converge the substrate back bias voltage -vbb to a predetermined value without intermittently stopping/resuming its operation, there is no need to suddenly supply charge to the substrate as in the prior art. , it is possible to avoid the restriction that circuit constants must be set in advance so that the operating cycle of the oscillation circuit is relatively short, and as a result, it is possible to achieve a reduction in power consumption in the chip non-selected state or standby state. can.

Here, the variation in threshold voltage due to the substrate effect in one N-channel MOSFET included in the resistance circuit REG is relatively small. In order to increase the amount of change in the resistance value of the entire resistance circuit REG obtained by the substrate effect by several times or about 10 times, a large number of MOSFEs are required according to the multiplication factor.
It is sufficient to connect T in series. Also individual MOSFET
In order to increase the fluctuation in the threshold voltage due to the substrate effect on the MOSFET, as shown in FIG.
It is preferable to form a P-type well region P-WELL dedicated to the resistance circuit REG into which impurities are introduced to a high degree of n. In this case, a double-well CMOS process is required, and other N-channel MO8FETQ
n is formed in a P-type semiconductor substrate P-SUB, and a representatively shown P-channel type MO3FET QP is formed in an N-type well region N-WELL. This N-type well region N-
WELL is coupled to the power supply terminal Vcc, and a back bias voltage -vbb is applied to the P-type well region P-WELL and the semiconductor substrate P-3UB. In FIG. 3, 1 is a field oxide film, 2 is a source/drain region of a MOSFET, and 3 is a MOS made of polysilicon, etc.
FET gate electrode, 4 is a gate oxide film, 5 is an insulating layer,
6 is an aluminum wiring layer, and the structure of the upper layer is omitted.

Although the circuit configuration for selecting the operation of the second generation circuit Vbb-02 is not shown in FIG. 1, for example, at least one CMOS included in the loop of the oscillation circuit oSC
Instead of the inverter circuit, a two-man NAND gate circuit or the like having an output terminal coupled to the loop may be provided. A control signal for operation selection is applied to one input terminal of this Nant gate circuit. When this control signal is set to high level, oscillation operation is enabled, and when set to low level, the operation of the oscillation circuit O8C is deselected. Further, although the first generating circuit vbb-61 is not particularly illustrated, it can be configured in the same manner as in FIG. 1 with the necessary current drive capability, or without providing the resistor circuit REG.

Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited thereto, and can be modified in various ways without departing from the gist thereof.

For example, in the above implementation, the oscillation circuit is described in which the node N1 is charged and then discharged in the initial state, but conversely, the operation of discharging the node N1 in the initial state and then charging the node N1 is repeated. You may also adopt the format of transmitting information. In this case, the resistor circuit connects the power supply terminal Vce to the node N1.
placed on the side.

Furthermore, as shown in FIG. 4, an N-channel MO3FET Q46 receiving a back bias voltage -vbb at its back gate may be inserted between the output terminal of the CMOS inverter circuit INVa and the capacitor C1. Such MO8FE
TQ46 connects the capacitor C1 with a voltage lower by the threshold voltage.
In order to increase can do.

Further, in the embodiment described above, the level determination circuit for detecting level changes due to charging and discharging of the node N1 is configured by a CMOS inverter, but an inverter having another circuit type or even another circuit type may be employed. In addition, the discharge path and charging path to node N1 are connected to CMOS inverter TNVI (7) N-channel type MO5FET and P
Although the circuit is basically constructed using a channel type MO5FET, the circuit format can be changed as appropriate.

In the circuit block shown in FIG. 2, the memory array M-ARY may be composed of a plurality of memory mats. However, in this case, one word line may be selected in each memory mat, so that refresh operations regarding a plurality of word lines may be performed simultaneously. Furthermore, the pseudo-static RAM may be capable of simultaneously inputting and outputting information of a plurality of bits, or each address decoder may be shared by the plurality of memory mats. The circuit block configuration, control signals, address signals, etc. of the pseudo-static RAM may take various other forms.

In the above explanation, the invention made by the present inventor was mainly applied to a pseudo-static type RAM, which is the background field of application, but the invention is not limited thereto.
It can be widely applied to various semiconductor integrated circuits such as semiconductor memory devices such as AM and microcomputers. The present invention is.

It can be widely applied to conditions that require at least a substrate back bias.

〔Effect of the invention〕

A brief description of the effects obtained by typical inventions disclosed in this application is as in Section F.

That is, a resistor in which MOS FETs whose mutual conductance decreases as the absolute value of the substrate back bias voltage increases is connected in series in multiple stages in the discharge path or charging path of an oscillation circuit whose oscillation period is determined by the charging and discharging time of a predetermined node. Combine the circuits.

By configuring a substrate back bias circuit together with a charge pump circuit, a large number of MOSFs included in a resistor circuit can be
Because the threshold voltage of ET is controlled steplessly according to the level of the back bias voltage due to its substrate effect, the substrate back bias circuit can control the substrate back bias voltage without intermittently stopping and restarting its operation. This allows the circuit to converge to a predetermined value, which eliminates the need to suddenly supply charge to the board as in the conventional technology that uses intermittent control. This has the effect of escaping the constraint of having to set a constant and, as a result, reducing power consumption in the chip non-selected state or standby state.

In addition, by separating the MOSFET included in the resistance circuit from other N-channel type MO8FETs and forming the MOSFET in a dedicated well region doped with impurities at a high concentration, the MOSFET included in the resistance circuit itself is free from the substrate effect. Fluctuations in threshold voltage can be increased. Therefore, MO included in the resistance circuit
The control range of the CR time constant of the charging path or the discharging path can be easily increased without unnecessarily increasing the number of series stages of SFETs.

By biasing the gate electrode of the MOSFET included in the resistor circuit with a constant voltage, the configuration of the resistor circuit can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing part of a back bias voltage generation circuit included in a pseudo SRAM according to an embodiment of the present invention. FIG. 2 is a circuit block diagram of the entire pseudo SRAM according to an embodiment of the present invention, and FIG. 3 is a partial cross-sectional view of the device structure of the pseudo SRAM. FIG. 4 is a circuit diagram in which a MOSFET whose threshold voltage is controlled by receiving a back bias voltage is arranged between an oscillation circuit and a charge pump circuit in a back bias voltage generating circuit. M-ARY...Memory array, Qm...Selection MO
3FET, Cs... Information storage capacitor, TG...
Timing generator, Vbb-G... substrate back bias generation circuit, Vbb-G1... first generation circuit,
Vbb-02...Second generation circuit, -vbb...Substrate back bias voltage, oSC...Oscillation circuit, AMP.
...Amplification circuit, PUMP...Charge pump circuit. INV2...CMOS inverter, C2...capacitor, REG...resistance circuit, Qrl~Qrn...N
Chan*) Lt type MOS FET, VB...Gate bias circuit, P-WELL...P type well region, N-WELL...N type well region, P-SUB
...Semiconductor substrate. Figure I Vbb-62 No. REG Chu Pit Excursion

Claims (1)

[Claims] 1. A semiconductor integrated circuit including a substrate back bias circuit including an oscillation circuit and a charge pump circuit that rectifies a periodic signal generated by the oscillation circuit, wherein the oscillation circuit is included in the semiconductor integrated circuit. The oscillation period is determined according to the time constant of the charging path or the discharging path of a predetermined node, and the transconductance is increased in the discharging path or the charging path according to the increase in the absolute value of the generated substrate back bias voltage. 1. A semiconductor integrated circuit comprising a resistance circuit in which MOSFETs are connected in series in multiple stages, the resistance of which is reduced. 2. The MOSFET included in the resistance circuit is
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is formed in a well region independent of the OSFET, and a substrate back bias voltage can be applied to the well region. 3. The semiconductor integrated circuit according to claim 2, wherein the gate electrode of the MOSFET included in the resistor circuit is biased with a constant voltage.