JP2645296B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a technology effective for a semiconductor memory device having a built-in substrate back bias voltage generating circuit such as a random access memory (hereinafter referred to as a RAM). It is about.

[0002]

2. Description of the Related Art In a semiconductor memory device composed of a MOSFET (insulated gate type field effect transistor),
It is known that a substrate back bias voltage is formed by a built-in substrate back bias voltage generation circuit in order to reduce a parasitic capacitance between a circuit element such as a MOSFET and a semiconductor substrate (for example, published by Nikkei McGraw-Hill, Inc. Nikkei Electronics, May 14, 1979, pages 77 to 79). By incorporating the substrate back bias voltage generation circuit in this manner, the power supply voltage to be supplied to the semiconductor memory device can be made a single voltage such as 5 V, and the number of external terminals can be reduced. it can. In this case, the use of a circuit for rectifying the output pulse continuously generated by the oscillation circuit causes the following problem to be clarified by the research of the present inventor. That is, the current flowing through the substrate is greatly different between the selected state in which the circuits start operating simultaneously and the non-selected state in which the internal circuit performs no operation. Therefore, in the case where the oscillation pulse generated irrespective of the circuit operation is rectified to form the substrate back bias voltage, the current supply capability is necessarily set assuming the worst conditions. Therefore, a relatively large capacitor, a rectifying element, and a driving circuit are required, and the degree of integration in the semiconductor memory device is reduced. At the same time, the current consumption increases. (For the substrate back bias voltage generating circuit, see, for example, Japanese Patent Application Laid-Open No. 55-13566).

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device with high integration and low power consumption.

[0004] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, the output signal of the oscillation circuit is
First buffer circuit and second buffer circuit received respectively
Of which is connected to the first buffer circuit through a gate circuit.
And transmitting the oscillation signal to the first buffer circuit.
Generates a negative voltage by receiving the output of the circuit and the second buffer circuit
First and second rectifiers to supply current to the substrate gate
The circuit constitutes the substrate back bias voltage generation circuit,
Level of substrate back bias voltage by level detection
To generate a control signal, and the oscillation circuit operates.
State, the gate circuit is controlled by the control signal.
To stop the operation of the first rectifier circuit.

[0006]

By controlling the transmission of the output of the oscillation circuit to the buffer circuit by the gate circuit, the level of the substrate back bias voltage is monitored, and the level detection output forms the oscillation circuit for forming the substrate back bias voltage and its rectification. By selectively stopping the operation of the circuit, it is possible to suppress substantially wasteful current consumption, thereby achieving low power consumption of a semiconductor memory device having a built-in substrate back bias voltage generation circuit. .

[0007]

FIG. 1 shows a dynamic type R according to the present invention.
A circuit diagram of one embodiment of the AM is shown. Each circuit element or circuit block shown in FIG. 1 is formed on a single semiconductor substrate such as single crystal silicon, although not particularly limited by a known semiconductor integrated circuit manufacturing technique. Various MOSFETs formed on a semiconductor substrate are in an enhancement mode (the same applies to other embodiments described later).

The memory array MARY includes a plurality of memory cells MC arranged in a matrix and a plurality of data lines DL,
It comprises a DLB and a plurality of word lines. Here, those which become active on the load side are denoted by B (bar). Although not particularly limited, the memory array MAR
Y is a folded bit line (data line) system.

[0009] Each of the memory cell MC, and the address which is provided between the reference potential point is supplied to the information storage capacitor C _s and the information storage capacitor C _s and the data lines, such as power supply terminal of the one end of the circuit Selection MOSFET Q _m
Consists of Logic stored in memory cell MC "
1 "," in the information reading. Information corresponding to whether or no charge in the capacitor C _s is present 0 ", the data line DL in the memory array MARY, nearly circuit by DLB is first pre-charge circuit PC power Voltage _Vcc
Precharged at a level close to. The precharge circuit PC includes, for example, data lines DL, DL as shown in the figure.
B and a precharge MO provided between the power supply terminal _Vcc
It consists of SFETs Q _c1 and Q _c2 . Precharge MOSFE
The conduction and non-conduction of TQ _c1 and Q _c2 are controlled by a precharge pulse φ _pc . Note that the precharge circuit P
C is, together with the precharge MOSFETs Q _c1 and Q _c2 ,
Equalize M provided between paired data lines DL and DLB and controlled by precharge pulse φ _pc
OSFETs may be included.

One of a plurality of word lines WL in the memory array MARY is selected after each data line is precharged. In response, MOSFET Q _m in the memory cell corresponding to the selected word line
Data lines DL, or D but is turned on capacitor C _s
Coupled to LB. In response, the potential of data line DL or DLB to which that memory cell MC is coupled is changed. At this time, the potential of the data line DL or DLB is changed in accordance with the amount of charge stored in the capacitor C _S. This change in the potential of the data line is sensed by the sense amplifier SA. In a large-capacity memory array, a memory cell M
C is formed with a small size, and many memory cells are coupled to each data line DL, DLB. Therefore, the ratio C _s / C ₀ between the capacitor C _s and the stray capacitance C ₀ (not shown) of the common data line DL has a very small value. Therefore, the potential change that is, the signal supplied to the data line DL or DLB corresponds to the charge stored in the capacitor C _s is a very fine level.

Although not particularly limited, according to this embodiment, one dummy cell DC is provided for each data line similarly to that of a well-known dynamic RAM for detecting such a small signal. I have. The dummy cell DC, except that the capacitance value of the capacitor C _D is approximately half capacitors C _s of the memory cell MC, and
It is manufactured under the same manufacturing conditions and the same design constants as the memory cell MC. Capacitor C _D, prior to its addressing, is charged to the ground potential by MOSFET Q _d for receiving a timing signal phi _d. Since the capacitance value of the capacitor C _D is set to approximately half the capacitance value of the capacitor C _s, a reference voltage that is substantially equal to half of the read signal from the memory cell MC is formed.

In FIG. 1, SA is a sense amplifier which expands such a difference in potential change caused by the addressing into a sense period determined by timing signals (sense amplifier control signals) φ _pa1 and φ _pa2 (the operation thereof is as follows). A pair of complementary data lines DL, D arranged in parallel.
The input / output node is coupled to LB. The number of memory cells coupled to the complementary data lines DL and DLB is made equal to each other in order to increase data detection accuracy in data reading.

In the above addressing, when a memory cell MC coupled to one of the pair of complementary data lines DL and DLB is selected, a dummy cell DC coupled to the other data line is correspondingly selected. One of the pair of dummy word lines DWL and DWLB is selected.

The sense amplifier SA has a pair of MOSFETs Q ₁ and Q ₂ whose gates and drains are cross-connected, and the complementary data lines DL and
A small signal appearing in the DLB is differentially amplified. The amplification operation is divided into two stages by the operation of the MOSFET Q ₈ which is adapted to a relatively large conductance and MOSFET Q ₇ which is adapted to a relatively small conductance. That is, the first-stage amplification operation is performed by the MOSF by the relatively early timing signal φ _pa1 .
It starts accordingly when ETQ ₇ begins to conduct. The second-stage amplification operation is started when the timing signal φ _pa2 is generated at a timing when the difference potential between the complementary data lines DL and DLB has increased to some extent.
That is, the amplification operation of the second stage is performed by the timing signal φ _pa2
Initiated accordingly the MOSFET Q ₈ is turned by. Such two-stage operation of the sense amplifier SA enables error-free amplification of the potential difference between the complementary data lines DL and DLB and high-speed amplification. As a result of the amplification by the sense amplifier SA, one of the pair of data lines is set to a high potential slightly lower than the power supply voltage _Vcc , and the other is set to a low potential substantially equal to the ground potential (0 V) of the circuit. .

At the time of the above addressing, the storage information of the memory cell MC that has been about to be destroyed is restored by supplying the high-level or low-level potential obtained by this sensing operation to the memory cell MC as it is. That is, the stored information once read is rewritten to the memory cells.

The active restore circuit AR provided between the complementary data lines DL and DLB applies a high level potential to be rewritten to the memory cell MC to the power supply voltage V of the circuit.
_Provided to raise to a level substantially equal to _CC . The active restore circuit AR has a function of selectively boosting only the high-level signal to the potential of the power supply voltage V _CC without affecting the low-level signal. Since the specific circuit configuration of such an active restore circuit AR is not directly related to the present invention, a detailed description thereof will be omitted.

Between the data line pair DL, DLB and the common complementary data lines CDL, CDLB, MOSFETs Q ₃ ,
Column switch CW comprising a Q ₄ are provided. Similarly, the other data line pairs and the common complementary data lines CDL, CL
A column switch CW composed of similar MOSFETs Q ₅ and Q ₆ is provided between the column switch CW and the DLB. The pair of common complementary data lines CDL and CDLB are connected to an input terminal of a data output buffer DOB including an output amplifier and an output terminal of a data input buffer DIB.

A row decoder and a column decoder R, C-
The DCR receives the internal complementary address signal formed by the address buffer ADB, and forms a selection signal for selecting one word line and a dummy word line and a column switch selection signal to be supplied to a column switch. Thus, addressing of the memory cells and the dummy cells is performed.

The operation of the address buffer ADB is controlled by timing signals φ _ar and φ _ac , and the operation of the row decoder and column decoders R and C-DCR is controlled by timing signals φ _x and φ _y . That is,
External address signals AX _{0 to} AX _i are timing signals φ _ar formed by row address strobe signal RASB.
In synchronization with the address buffer R-ADB. The internal address signal formed by the address buffer R-ADB is transmitted to the row decoder R-DCR. The address decoder R-DCR decodes the internal address signal supplied from the address buffer R-ADB, to one by one of the word lines and dummy word lines to a selection level at a timing in accordance with the word line select timing signal phi _x .

Further, the external address signal AY ₀ ~AY _l addresses in synchronism with the timing signal phi _ac formed by the column address strobe signal CASB buffer C-A
The data is taken into the DB and transmitted to the column decoder C-DCR. The column decoder C-DCR outputs a column select signal for selecting a predetermined data line at a timing in accordance with the data line selection timing signal phi _y.

The timing control circuit TC receives a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied from external terminals. And other various timing signals necessary for the operation.

Although not particularly limited, in order to reduce the power consumption of the device and to enable continuous read operation by switching the column address signal while the word line is selected, the column-based address buffer and the address are used. Decoder and data output buffer DOB are CMOS
It is composed of (complementary) static type circuits.

Substrate back bias voltage generating circuit V _bb -G
Is operated by a positive power supply voltage such as +5 V applied between a power supply terminal V _CC constituting an external terminal of the integrated circuit and a reference potential terminal (or ground terminal) GND, and outputs a negative bias voltage.

Substrate back bias voltage generating circuit V _bb -G
Bias voltage output is supplied to the semiconductor region serving as a common substrate gate of the MOSFET constituting the circuit block being MOSFET Q _m and illustrated in the memory array from.

Although not particularly limited, the CMO of this embodiment
The S integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. MOSF in memory array MARY
N-channel MOSFET such as ETQ _m was formed through such a semiconductor substrate formed on the surface of the source regions, thin gate insulating film of the semiconductor substrate surface between the drain region and the source region and the drain region It is composed of a gate electrode made of polysilicon. The P-channel MOSFET is formed in an N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate has a plurality of N-channel MOSs formed thereon.
Construct a common substrate gate for the FET. The N-type well region forms a base gate of the P-channel MOSFET formed thereon. The base gate of the P-channel MOSFET, that is, the N-type well region is connected to the power supply terminal V _{CC of} FIG.
Is combined with

Although not shown, the CMOS integrated circuit of this embodiment has a main surface of the semiconductor substrate other than a surface portion to be an active region, that is, a MOSFE.
Surface portions other than the surface portions where the T, MOS capacitors, semiconductor wiring regions and the like are to be formed are covered with a relatively thick field insulating film. The required wiring layers are
It extends over the field insulating film or over the active region via the insulating film.

[0027] According to this structure, a substrate back-bias voltage is output from the substrate back-bias voltage generation circuit V _bb -G - V _bb is supplied to a common substrate gate of the N-channel MOSFET formed on the surface of the semiconductor substrate You.

The substrate back bias voltage is a junction capacitance formed by the PN junction between the source / drain region of the N-channel MOSFET and the semiconductor substrate and a junction formed by the PN junction between the semiconductor wiring region and the semiconductor substrate. Decrease capacity. In response, the integrated circuit:
Since the parasitic capacitance that limits the operation speed at that time is reduced, high-speed operation is possible.

MOS such as address selection MOSFET
FETs often have leakage current, even when they are turned off. In this MOSFET, the threshold voltage is appropriately increased by a substrate bias effect when a substrate back bias voltage −V _bb is applied,
Thereby, the leakage current therein is reduced. As a result of the reduction of the leakage current in the address selection MOSFET, charges held in the information storage capacitor C _s will be retained over a relatively long period of time.

In an integrated circuit, a structure including a field insulating film and a wiring such as a signal wiring extending thereon is considered to constitute a part of a parasitic MOSFET structure. The substrate back bias voltage −V _bb is a parasitic MOSFE
The threshold voltage of T is increased so that the parasitic MOSFET does not operate.

As is well known, the rate of increase in the threshold voltage due to the body effect of the MOSFET becomes smaller as the body back bias voltage increases.
Therefore, the threshold voltage of the N-channel MOSFET is regardless of the characteristic variation based on manufacturing variation of the integrated circuit, the substrate back bias voltage - a value within a relatively narrow range when V _bb is generated.

Substrate back bias voltage generating circuit V _bb -G
Generates a substrate back bias voltage periodically by a charge pump function using a capacitor, as will be apparent from the description below. The substrate back bias voltage is smoothed by a parasitic capacitance and a stray capacitance existing between a semiconductor substrate to which the substrate is applied and a power supply line, a semiconductor region, and the like.

The substrate back bias voltage is determined by the MOSFET
Is reduced by a leak current generated between the source / drain region of the semiconductor device and the semiconductor substrate.

Here, the leak current to the semiconductor substrate is not always constant and is affected by the circuit operation. This leakage current is relatively small if the switch state of the MOSFET is fixed or stationary without being changed. On the other hand, when the switch state of the MOSFET changes, the leak current increases accordingly.
As for the mechanism of the generation of the leak current to the substrate, if necessary, published in 1981 by Jon Willy & Sons,
M. S. SM Sze, Physics of Semiconductor Devices, 480
See pages 487 to 487.

In the dynamic RAM shown in FIG.
The substrate leak current is determined by the row address strobe signal RAS
B, when the circuits such as the timing control circuit TC, the address buffer, the decoder, and the sense amplifier are operated based on the column address strobe signal CASB and the like, the value is increased accordingly.

According to this embodiment, the substrate back bias voltage generating circuit V _bb -G is used to maintain the substrate bias potential at an appropriate value even when the substrate leakage current is increased. , Having a relatively large driving capability. At the same time, the substrate back bias voltage generation circuit V _bb -G is made to exhibit low power consumption characteristics.

The substrate back bias voltage generation circuit V _bb -G of this embodiment includes a circuit part for a steady operation and a circuit part for an intermittent operation, although not particularly limited, in terms of driving capability and power consumption. To be. The circuit part of the stationary operation has a relatively small driving capability capable of maintaining the substrate back bias voltage −V _bb at a desired value when the circuits of FIG. 1 are substantially inactivated. Be made to have.

[0038] In contrast, the circuit portion of the intermittent operation, in order that the substrate back-bias voltage -V _bb even when the substrate leakage current is increased can be maintained at a desired value, a relatively large It is made to have driving ability.

For controlling the operation of the intermittent operation circuit,
A level detection circuit VLD as shown in FIG. 1 is provided. Level detection circuit VLD is a substrate back bias voltage - detecting the V _bb, the substrate back bias voltage - when V _bb is smaller than the desired level, and outputs a signal for operating the circuit portion of the intermittent operation.

Although not particularly limited, according to this embodiment, the circuit portion of the intermittent operation in substrate back bias voltage generation circuit V _bb -G includes control signal R output from timing control circuit TC based on external control signal RASB.
The operation is also controlled by AS ₁ B.

According to this mechanism, the following circuit operation becomes possible.

That is, the dynamic RAM of the embodiment
Is started by the row address strobe signal RASB, the operation of the illustrated circuit is started accordingly, so that the substrate leakage current increases. The level of the substrate back bias voltage −V _bb decreases as the substrate leakage current increases. In this case, the substrate back bias voltage is controlled by the control signal RAS.
Even without the control of the circuit operation by ₁ B, it is controlled so as to be again desired level by the feedback path constituted by the circuit section of the level detection circuit VLD and the intermittent operation.
However, in this case, the time until the substrate back bias voltage is restored to the desired level again becomes slightly longer according to the output change speed of the intermittent operation circuit portion.

On the other hand, as shown in this example, the control signal R
In the case where AS ₁ B, that is, an earlier timing control signal among the control signals output from the timing control circuit TC is used, the circuit part of the intermittent operation is substantially at the same timing as the timing at which the substrate leakage current is sharply increased. Operation can be started. As a result,
A large level change of the substrate back bias voltage can be prevented.

The substrate back bias voltage generation circuit V
The circuit portion of the intermittent operation in _bb- G is controlled by the control signal RAS ₁
When control is performed by a control signal such as B, the level detection circuit VLD can be omitted. However, when doing so, it is necessary to pay attention to the following points.

That is, the substrate back bias voltage −V _bb
Is preferably changed from approximately 0 volts to a predetermined level within a relatively short time when the power is turned on. In order to accelerate the generation of the substrate back bias voltage when the power is turned on, it is necessary to operate the intermittent operation circuit portion of the substrate back bias voltage generation circuit V _bb -G.
For this purpose, it is necessary to apply a row address strobe signal for executing a dummy operation cycle to the external terminal RASB at the time of power-on.

When the detection output of the level detection circuit VLD is used, the circuit portion of the intermittent operation is immediately activated by the detection output, so that the substrate back bias voltage is applied to the external terminal RASB when the power is turned on. Regardless of the signal applied, it is changed to a predetermined level within a relatively short time.

When the output of the level detection circuit VLD is not used, the level of the substrate back bias voltage may be undesirably reduced due to an increase in substrate leakage current accompanying an increase in the operating temperature of the integrated circuit. Is generated.

FIG. 6 is a circuit diagram showing one embodiment of the substrate back bias voltage generating circuit V _bb -G. In FIG. 1, the MOSFET in which a straight line is added between the source and the drain is a P-channel type.

In this embodiment, two types of substrate back bias voltage generating circuits, that is, a substrate back bias voltage generating circuit forming a circuit portion of a steady operation and a substrate back bias voltage generating circuit forming a circuit portion of an intermittent operation are provided. Is provided. Substrate back bias voltage generating circuit of one of the steady operation is configured to include an oscillation circuit OSC _2, the CMOS inverter circuit IV _4, IV ₅ and the rectifier circuit for amplifying and waveform shaping of the output.

The oscillator circuit OSC 2 is operated by the power supply voltage V _CC, for example, a plurality of CMOS inverter circuits from the ring oscillator configured by being coupled in a ring shape.

The rectifier circuit has a capacitor C ₂ for a charge pump and a gate electrode for operating as a rectifying element. The gate electrode functions as a drain electrode or a source electrode depending on the applied voltage polarity. different consists MOSFET Q ₂₀ and Q ₂₁ Metropolitan coupled for convenience referred to as the drain electrode). Although not particularly limited, the capacitor C ₂ is an N-channel MOSFET
By adopting a structure similar to that described above, a MOS capacitor structure is obtained. One electrode of the capacitor C _2, i.e. electrodes corresponding to the gate electrode of the MOSFET, CMOS inverter circuits I as the output buffer
It is coupled to the output terminal of the V _5. Electrodes and the other of the source electrode i.e. MOSFET also be associated with the drain electrode of the capacitor C ₂ is connected to a common connection point of the MOSFET Q ₂₀ and Q _21.

[0052] MOSFET Q ₂₀ as a rectifying element is provided between the ground point GND of the other electrode and the circuit of the capacitor C _2, MOSFET Q ₂₁ is provided between the other electrode and the semiconductor substrate.

Between this substrate and the ground potential point of the circuit,
In effect, there is a parasitic capacitance C _sb (not shown) that holds the substrate back bias voltage.

The diode type MOSFET Q
₂₀ is turned on when the oscillation pulse is at a high level (power supply voltage V _CC ). Thus, the capacitor C ₂ precharge is performed by the output high level. Then when the oscillation output pulse is at a low level (ground potential of the circuit), the other electrode of the capacitor C ₂ is, - (V _CC -V
_th ). Here, V _th is the MOSFET Q ₂₀
Threshold voltage. MOSFET Q ₂₁ of diode configuration by the negative potential is set to the ON state, conveys a negative potential to the parasitic capacitance C _sb. As a result, a substrate bias voltage of −V _bb is applied to the substrate. The substrate bias voltage generating circuit in the steady operation has a relatively small current supply capability capable of compensating for a leakage current flowing to the substrate when the RAM is set to the chip non-selection state. .

The current supply capability of the substrate bias voltage generating circuit in a steady operation is substantially determined by the capacitance of the capacitor C ₂ and the oscillation frequency of the oscillation circuit OSC 2 . That is, the amount of charge injected into the semiconductor substrate in response to one of the oscillation output pulse, the larger the capacitance of the capacitor C _2, increases accordingly. Also,
The number of times charges are injected into the semiconductor substrate per unit time is
The larger the oscillation frequency of the oscillation circuit OSC 2 increases accordingly.

According to this embodiment, the substrate back bias voltage generating circuit in a steady operation is configured to exhibit a low power consumption characteristic while securing a required relatively small current supply capability. Oscillation frequency of the oscillation circuit OSC 2 includes a set of appropriate number of CMOS inverter circuits constituting the oscillating circuit, by the appropriate setting of the respective signal delay characteristics, for example, relatively low such as 1 to 2 MHz Valued. The capacitance of the capacitor C ₂ is set to a relatively small value.

[0057] Here, the power consumption in the oscillator circuit OSC 2 is proportional to the oscillation frequency. That is, the oscillation circuit OS
Operating current or current consumption of the respective CMOS inverter circuits constituting the C 2 is well-known CMOS
Similar to that of the inverter circuit, it is proportional to the so-called transient current required for charging / discharging the load capacitance (including the wiring capacitance and the input capacitance of the subsequent inverter circuit) coupled to each output. Is substantially 0 in a quiescent state in which each input or output is at a high level or a low level. Since transient current of each CMOS inverter circuit it is proportional to the operating frequency, power consumption of the oscillation circuit OSC 2 of the low oscillator frequency is smaller.

According to this embodiment, a CMOS inverter circuit I as an output buffer for driving a rectifier circuit is provided.
Drivability of V _5, since the capacitor C ₂ is relatively small, may be relatively small. Therefore, this CMO
Since S P-channel MOSFET and the N-channel MOSFET (not shown) constituting the inverter circuit IV ₅ is not required to have a low on-resistance may be to a smaller size. P channel MO (not shown) forming CMOS inverter circuit IV ₄ as a waveform rectifier circuit
SFET and N-channel MOSFET may if driven relatively light capacitive load by MOSFET constituting the CMOS inverter circuit IV ₅ is small. Therefore MOSFET constituting the CMOS inverter circuit IV ₄ may be a small size.

[0059] substrate back-bias voltage generation circuit of the intermittent operation, a controllable oscillator circuit or operable intermittently oscillation circuit OSC 1, a CMOS inverter circuit IV ₂ as waveform rectifier circuit, a CMOS inverter circuit IV as an output buffer ₃ and a rectifier circuit.

Although not particularly limited, the oscillation circuit OSC1
Is a CMOS gate circuit G_TwoNot
G_FourIt is composed of Gate circuit G_TwoOr G_FourIs
Are connected in a ring shape. That is, the gate circuit G_TwoAbsent
G_FourOutput terminals are connected to the gate circuit of the subsequent stage.
Connected to the other input terminal. Last stage gate circuit G_Four
The output terminal of the first stage gate circuit G_TwoOne input terminal of
Is joined to. Gate circuit G_TwoOr G_FourEach of
The other input terminal is connected in common and connected to the operation control terminal.
Have been.

[0061] In the oscillation circuit OSC 1, each gate circuit, the control signal supplied to the operation control terminal if the high level (logic "1"), essentially performing the operation as an inverter accordingly. Therefore, the oscillation circuit OSC ₁
Performs an oscillating operation as a ring oscillator. Control signal if a low level (logic "0"), the respective outputs of the gate circuits G ₂ through G ₄ are fixed to the high level.

The rectifier circuit includes a capacitor C ₁ as shown in the figure.
And a and MOSFET Q ₁₈ and Q _19.

[0063] If the oscillation circuit OSC 1 is in the operating state by the high level of the control input, the rectification circuit is operated to a capacitor C ₁ and MOSFET Q ₁₈ and Q ₁₉ accordingly. In response, charges for applying a substrate back bias voltage to the semiconductor substrate are injected. At this time, the substrate back bias voltage is determined by the co-operation of the substrate back bias voltage generation circuit in the steady operation and the substrate back bias voltage generation circuit in the intermittent operation.

[0064] If the oscillation circuit OSC 1 is a non-operating state by the low level of the control input, a rectifier circuit composed of capacitors C ₁ and MOSFET Q ₁₈ and Q ₁₉ are not operated. At this time, the CMOS inverter circuit IV
The output of _{No. 3} is maintained at a high level by the high level output of the oscillation circuit OSC1. Capacitor C ₁ is maintained in charged state by the high level output of the inverter IV _3. This configuration allows for charge injection into the substrate at an early timing when the operation of the oscillation circuit OSC 1 is started.

The CMOS NAND gate circuits G ₂ to G ₄ constituting the oscillating circuit OSC 1 do not consume current as long as each of them is at rest, similarly to the CMOS inverter circuit. Therefore the power consumption of the substrate back-bias voltage generation circuit of the intermittent operation becomes substantially zero in the period during which operation of the oscillation circuit OSC 1 is stopped.

This intermittent operation of the substrate back bias voltage generating circuit has a relatively large current supply capability for compensating for a relatively large leakage current flowing through the substrate when the RAM is in the operating state. Therefore, the capacitor C
₁ capacitance is relatively large value, the oscillation frequency of the oscillation circuit OSC 1 is a relatively large value such as, for example, 10 to 15 megahertz.

A not-shown P-channel MOSFET and N-channel M which constitute the CMOS inverter circuit IV ₃
The OSFET is made to have a relatively large size, corresponding to the fact that the rectifier circuit will constitute a relatively heavy load. P-channel MOSFET and the N-channel MOSFET (not shown) constituting the CMOS inverter circuit IV ₂ are thereby in order to provide a thorough drive the CMOS inverter circuit IV _3, it is to have a relatively large size.

In this example, in order to operate the substrate bias voltage generating circuit only when necessary,
FETs Q ₁₀ to Q ₁₇ and the CMOS inverter circuit IV
₀ and a level detecting circuit consisting of IV _1, the control circuit is provided comprising a CMOS NAND gate circuit G ₁ Tokyo.

[0069] The level detection circuit, the substrate back bias voltage - is provided to detect the V _bb is absolutely the value and drastically beyond a certain level required for high-speed operations of the RAM. In the level detection circuit, P-channel MOSFET Q ₁₀ is the ground potential of the constantly circuit to the gate to act as a constant current load by supplying, it is steadily turned on state. This MO
The SFETQ _10, P-channel M for level clamp
OSFETQ ₁₁ are connected in series. This MOSFET
Q ₁₁ is the ground potential of the steadily circuit to the gate is in the constantly turned on by being supplied. Source potential i.e. MOSFE of This MOSFET Q ₁₁
The potential of the electrode coupled to the drain of TQ ₁₀ is at least at a level higher than the circuit ground potential, and the drain is substantially at the circuit ground potential. Drain and substrate of the MOSFET Q ₁₁ - between the _{(V bb), MOSFETQ 12 ~Q} 14 of diode configuration is connected in series.

As a result, the detection level of the level detection circuit is changed to the threshold voltage V _{th of the} MOSFETs connected in series.
_3Vth is substantially equal to the sum of Now, the substrate back bias voltage −V _bb is equal to the diode type MOSFET Q
If the sum of the threshold voltage 3V _th smaller level by ₁₂ ~Q _14, MOSFETQ ₁₂ ~Q ₁₄ is turned off. At this time, the potential of the connection point between the MOSFET Q ₁₁ and Q ₁₀ becomes a high level, such as approximately the power supply voltage V _CC. On the other hand, the substrate back bias voltage - if V _bb is a larger level than the threshold voltage 3V _th of the total by MOSFET Q ₁₂ to Q ₁₄ of the diode configuration, MOSFET Q ₁₂ to Q ₁₄ is turned on .
At this time, the potential at the connection point between the MOSFET Q ₁₁ and Q ₁₀ are,
Is only high low threshold voltage V _th of the MOSFET Q ₁₁ relative to the ground potential of the circuit. At this time, the current flowing from the power supply terminal V _CC to the substrate lowers the substrate back bias voltage −V _bb in absolute value. Order to minimize the current flowing to the substrate through the level detection circuit, and in order to sufficiently reduce the low level appearing at the common connection point of the MOSFET Q ₁₀ and Q _11, the conductance of the load MOSFET Q ₁₀ is a very small value Is set. That, MOSFET Q ₁₁ is set to a very small conductance as drains only small current.

[0071] The high and low levels of the detection output, as described above, is determined by the CMOS inverter circuit constituted by a P-channel MOSFET Q ₁₅ and N-channel MOSFET Q _16. Although not particularly limited,
In order to enable a high-speed change of the detection output to be obtained, especially when the substrate back bias voltage is reduced, the oscillation circuit OSC
_In order to operate ₁ at an earlier timing, MOSFET
An inverter circuit consisting of Q ₁₅ and Q ₁₆ are, MOSFET
With Q ₁₇ and the CMOS inverter circuit IV ₀ is adapted to constitute a Schmitt circuit. That is, MOS
The output of the inverter circuit composed of FETs Q ₁₅ and Q ₁₆ are,
It is transmitted to the input of the CMOS inverter circuit IV ₀ similar configuration. The output of the CMOS inverter circuit IV ₀ is supplied to the gate of the P-channel MOSFET Q ₁₇ provided between the input and the supply voltage V _cc. As a result, positive feedback is applied. Detection signal output from the inverter circuit IV ₀ when the detection output of the low level is formed, is changed to the low level at a high speed. The detection output formed by the inverter circuit IV ₀ is CM
Through OS inverter circuit IV ₁ is supplied to one input of a CMOS NAND gate circuit G _1. An internal row address strobe signal RAS ₁ B formed by the timing control circuit TC of FIG. 1 is supplied to the other input of the NAND gate circuit G ₁ . The output of the Nangeto circuit G ₁ is supplied to the other input of the NAND gate circuit G ₂ ~G ₄ constituting the ring oscillator OSC 1.

Next, the operation of the circuit of FIG. 2 will be described with reference to the timing chart of FIG.

If the RAM is in a chip non-selected state, that is, the internal address strobe signal RAS ₁ B
There if is in the high level, the output of the gate circuit G ₁ is responsive to the detection output of the level detection circuit.

[0074] In the chip non-selection state, the substrate back bias voltage - the V _bb is absolute value smaller than the threshold voltage 3V _th of the sum of the MOSFET Q ₁₂ to Q _14, these MOSFET Q ₁₂ to Q ₁₄ are off State. As a result, the detection output is set to the high level. Therefore the detection output supplied to the NAND gate circuit G ₁ becomes a low level (logic "0"). Accordingly, the output of the NAND gate circuit G ₁ is a high level (logic "1"), the oscillation circuit OSC ₁ is in the oscillation state. The rectifier circuit receiving the output pulse allows the substrate back bias voltage −V _bb
Is increased in absolute value. By such an operation,
Substrate back bias voltage - V _bb is the threshold voltage 3V
exceeds _th, since the MOSFET Q ₁₂ to Q ₁₄ is turned on, the detection output is at a low level. Accordingly, the detection output supplied to the NAND gate circuit G ₁ becomes high level (logic "1"). In response to this, the low level output of the NAND gate G ₁ is all of the NAND gate circuit G ₂ output of ~G ₄ is a high level to form an oscillation circuit OSC 1 because it is (logic "0") (logical "1") Is done. That is, the oscillation operation is stopped. By stopping the oscillation operation, the operation of the rectifier circuit (C ₁ , Q ₁₈ , Q ₁₉ ) is also stopped. Accordingly, the operation of the oscillation circuit that consumes a large level of power and the operation of the rectifier circuit are stopped, so that low power consumption can be achieved. Immediately after the power is turned on, the substrate back bias voltage is at a level similar to the ground potential of the circuit. It can be started up to a desired level.

When chip selection is instructed by setting the row address strobe signal RASB to low level, the internal signal RAS ₁ B is set to low level in response to this, so that the output of the NAND gate circuit G ₁ is set to the level detection circuit. High level (logic “
Is. This is to 1 "), when the RAM is writing / reading, etc., the oscillation circuit OSC 1 is in the operating state unconditionally. This is because the operation of the RAM is started as described above The substrate back bias voltage −V
_This is to prevent _bb from suddenly decreasing in absolute value. It is possible to prevent a sudden drop in V _bb - advance to the oscillation circuit OSC 1 to the operating state when the substrate back bias voltage when the RAM is in the operation state as in Example.

FIG. 4 is a circuit diagram of a dynamic RAM including the substrate back bias generation circuit of FIG. The circuits not shown in FIG. 4 are made substantially the same as those in FIG.

The RAM of this example includes a refresh control circuit REFC and a multiplexer MPX to enable auto-refresh of a memory cell.

Although not shown, the refresh control circuit REFC includes a refresh timer and a refresh address counter.

The refresh timer indicates a refresh operation when the row address strobe signal RASB supplied to the external terminal is at the high level and the refresh control signal REFHB is at the low level, in other words, when the chip is not selected. And periodically outputs a refresh control signal φ _ref during the operation period.

[0080] Refresh address counter receives a control signal output from the refresh timer as stepping pulse, to no refresh signal ax ₀ B to form the ax _i.

The multiplexer MPX outputs the control signal φ _ref
Its operation is controlled, to the internal address signals ax ₀ no B outputted from the address buffer R-ADB if the control signal phi _ref is not output select ax _i by,
If the control signal φ _ref has been output, the refresh address signal ax _{0 #} B to axi _{i #} are selected.

The timing control circuit TC controls the row address strobe signal R supplied to the external terminal in the same manner as in the above example.
In response to the ASB, the column address strobe signal CASB, etc., various timing signals similar to those in the above example are output. However, the timing control circuit TC is somewhat different from that of the embodiment in that the internal circuit is formed point to be responsive to the refresh control signal phi _ref. The timing control circuit TC supplies the refresh control signal φ _ref
Is generated, the row circuit of FIG.
That is, the timing signal φ _x for controlling the operations of the row address decoder R-DCR, the precharge circuit PC, the sense amplifier SA, and the active restore circuit AR,
Output φ _pc , φ _pal , φ _pa2 , φ _ra .

According to this configuration, the refresh operation
It is executed every time the refresh control signal _φref is generated. That is, when the refresh control signal phi _ref is generated, the refresh address counter of the refresh address signal a _x0 B through ax _i is the row address decoder of FIG. 1 via a multiplexer MPX accordingly R-
Supplied to the DEC. A timing control circuit TC by the control signal phi _ref is activated, the timing control circuit T
1 according to a row-related timing signal output from C.
Precharge circuit PC, row address decoder RD
EC, sense amplifier SA and active restore circuit A
R is driven sequentially. As a result, the word line corresponding to the refresh address is selected, and the information held in the memory cell connected to the word line is refreshed.

The substrate back bias voltage generation circuit V _bb -G and the level detection circuit VLD of this embodiment are substantially the same as the circuit of FIG.

[0085] According to this embodiment, the substrate even by the refresh control signal phi _ref back bias voltage generating circuit V
_In order to control the operation of _bb- G, CMOS
A logic synthesis circuit including a gate circuit G ₅ and CMOS inverter circuits IV ₆ and IV ₇ is provided. The output of the logic synthesis circuit is set to a low level when a chip is selected (when the row address strobe signal RASB is set to a low level) and during a refresh operation.

[0086] This circuit portion of the intermittent operation of the substrate back-bias voltage generation circuit V _bb -G when the substrate leakage current is increased by the execution of the refresh operation, i.e., the timing control circuit TC by the refresh control signal phi _ref When the row-related circuit is operated, the circuit is operated in synchronization with the circuit.

When it is necessary to enable the battery backup of the dynamic RAM, the external terminals V _CC and GN
D and a battery E together with a power supply PS that forms a predetermined DC voltage based on, for example, a commercial AC power supply.
And a series circuit composed of a diode D. When the power supply PS is shut off, the power supply voltage required by the RAM for retaining information or data is supplied from the battery E.

In the dynamic RAM of the example, the refresh operation at the time of battery backup is automatically performed without requiring a special external control signal. Therefore, the RAM does not require the operation of other external devices during battery backup.

The dynamic RAM of this embodiment has low power consumption as a whole because the substrate back bias voltage generation circuit V _bb -G in the dynamic RAM can reduce the power consumption. Therefore, the battery life at the time of battery backup can be extended.

FIG. 5 is a circuit diagram of the level detection circuit VLD and the substrate back bias voltage generation circuit of the present invention.

As shown, the level detection circuit VLD
Channel MOSFET Q ₂₆ , N-channel MOSFET
It is no TQ ₂₇ and a Q _29, and CMOS inverter circuit IV _10. The substrate gate of MOSFETQ ₂₆ is,
As in the previous embodiment, it is coupled to the power supply terminal V _CC . MO
Substrate gate of SFETQ ₂₇ to Q ₂₉ is composed of a P-type semiconductor substrate.

The detection output VD of the level detection circuit VLD is
In the same manner as in the previous embodiment, depending on the level of the substrate back bias voltage −V _bb , the level is almost equal to the high level of the V _CC level or almost zero.
It is set to the low level of V.

The CMOS NAND gate circuit G ₆ receives the detection output VD of the level detection circuit VLD and the control signal VCN ₁ . Control signals VCN ₁ is generated from a circuit such as an inverter circuit IV ₇ shown in FIG. 4, for example. The output of the NAND gate circuit G ₆ is supplied to the substrate back-bias voltage generation circuit V _bb -G.

Substrate back bias voltage generating circuit V _bb -G
Are the common oscillation circuit OSC and C as a waveform shaping circuit.
A MOS inverter circuit IV _8, and CMOS NAND gate circuit G _7, a CMOS inverter circuit IV _11, CMOS inverter circuits IV ₉ and I as a buffer amplifier
And V _12, composed of a rectifier circuit CPC ₁ and CPC ₂ Metropolitan.

[0095] CMOS inverter circuit IV _9, the output of the CMOS inverter circuit IV ₈ is supplied directly to its input, and outputs a steady pulse signal. This rectifier circuit CPC ₁ is operated constantly.

[0096] CMOS inverter circuit IV _12, the gate circuit G ₇ and CMOS inverter circuit IV ₁₁ at its input
The output of the CMOS inverter circuit IV ₈ is supplied via the. Therefore the output pulses of the CMOS inverter circuit IV ₁₂ are intermittently. Rectifier circuit CPC ₂ is intermittently operated in accordance with the output of the inverter circuit IV _12.

[0097] Current supply capacity of the semiconductor substrate by the rectification circuit CPC ₁ steady operation may likewise relatively small with the embodiment. Therefore, the capacitor C ₃ for the charge pump may be relatively small size.

On the other hand, the intermittent operation rectifier circuit CPC ₂
Capacitor C ₄ of the charge pump in is a relatively large size.

The capacitors C ₃ and C ₄ are formed in, but not limited to, an N-type well region (not shown) formed on the surface of the P-type semiconductor substrate, and a P-channel MOSF
The configuration is similar to ET. The N-type well region where the capacitors C ₃ and C ₄ are formed is, for example, a power supply terminal V _{CC of the} circuit.
Is maintained at the potential. This configuration is somewhat advantageous in reducing substrate leakage current.

According to this embodiment, the oscillation circuit OSC
It is shared by a rectifier circuit CPC ₁ and CPC _2. As described above, the bias current supplied to the semiconductor substrate is related to the operating frequency of the rectifier circuit. The oscillation frequency of the oscillation circuit OSC is limited and the power supply capacity to be obtained by the rectifier circuit CPC ₁ of steady operation, the current supply capacity to be obtained by the rectifier circuit CPC ₂ of the intermittent operation. Therefore, the lower limit of the oscillation frequency of the oscillation circuit OSC is somewhat limited relative to that of the oscillator OSC 2 of the steady operation of FIG.

[0102] However, in this embodiment, an oscillator circuit consumes power in its in own operation as the oscillation circuit OSC 1 of the intermittent operation of Figure 6 is not provided.

Therefore, the number of circuit elements can be reduced. Further, the power consumption of the common oscillation circuit OSC, for example be slightly larger than that of the oscillation circuit OSC 2 of FIG. 6, it is possible to reduce the average power consumption of the entire RAM sufficiently.

FIG. 2 is a circuit diagram of a substrate back bias voltage generating circuit V _bb -G of another embodiment.

The illustrated substrate back bias voltage generation circuit V
_bb -G the oscillation circuit OSC, the waveform shaping circuit CMOS inverter circuit IV _13, CMOS NAND gate circuit G _8, C
MOS inverter circuits IV ₁₄ and IV ₁₆ , CMOS inverter circuits IV ₁₅ and IV ₁₇ as buffer amplifiers,
Capacitors C ₅ and C ₆ for the charge pump, and to N-channel MOSFET Q ₃₅ not as the rectifying element consisting Q _38.

That is, the outputs of the gate circuit G ₈ and the inverter circuit IV ₁₇ are set to the high level regardless of the output of the oscillation circuit OSC. Capacitor C ₆ is charged by the high level output of inverter IV ₁₇ .

[0106] The output of the inverter IV _15, the oscillation circuit OS
It is changed to a high level and a low level in accordance with the output of C. In this state, the capacitor C ₅ and the MOSFE
Rectifier circuit is operated consisting TQ ₃₇ and Q ₃₈ Metropolitan. In response, the substrate back bias voltage _VBB is supplied to the semiconductor substrate. MOSFET Q _35, since the maximum positive level appearing at node N ₁ is clamped by the MOSFET Q ₃₇ as the rectifying elements is substantially maintained in the OFF state.

[0107] The output of the inverter IV _15, the oscillation circuit OS
It is changed to a high level and a low level in accordance with the output of C. In this state, the capacitor C ₅ and the MOSFE
Rectifier circuit is operated consisting TQ ₃₇ and Q ₃₈ Metropolitan. Substrate back-bias voltage -V _bb is supplied to the semiconductor substrate accordingly. MOSFET Q ₃₅ is, MOSFET Q ₃₇ of the positive maximum level appearing at node N ₁ as the rectifying element
, So that it is substantially kept in the off state.

[0108] Referring now the output of the inverter circuit IV ₁₃ is at the low level, the output of the inverter circuit IV ₁₅ is accordingly at a low level of approximately 0 volts. Node N ₅
Since the capacitor C ₅ is charged in advance the boost level, the output of the inverter circuit is at a negative potential larger accordingly when it is at a low level. The potential of this node, supplied to the semiconductor substrate through the MOSFET Q _38. The output of the inverter circuit IV ₁₇ is a high level of approximately the power supply voltage V _CC in response to the low level output of the inverter circuit IV _13. Further, MOSFET Q ₃₆ by a positive potential applied to the node N ₂ via a capacitor C ₆ is conductive. As a result, the capacitor C ₆ is charged again.

[0109] Operation as described above by a change in the output of the inverter circuit IV ₁₃ are repeated. As a result,
A large bias current is supplied to the semiconductor substrate during a period when the control signal VCN ₂ is at a high level.

According to this embodiment, two inverter circuits IV ₁₅ and IV ₁₅ having a relatively large driving capability are provided.
Since V ₁₇ are operated complementarily, it is possible to reduce the size of the transient current flowing through the power supply wiring in the RAM.
Accordingly, noise generated in the power supply wiring can be reduced.

[0111]

【The invention's effect】

(1) By monitoring the level of the substrate back bias voltage and selectively stopping the operation of the oscillating circuit for forming the substrate back bias voltage and the rectifier circuit thereof, it is possible to suppress substantially wasteful current consumption. it can. This makes it possible to reduce the power consumption of a semiconductor memory device having a built-in substrate back bias voltage generation circuit.

(2) A substrate back bias voltage generating circuit having only a small current driving capability to compensate for a leakage current when not selected, and a substrate back bias selectively operated by the level monitor output of the substrate back bias voltage Providing a voltage generation circuit, and disabling the monitor output when the internal circuit is activated, thereby forming a substantially constant substrate back bias voltage with low power consumption. The effect that it can be obtained is obtained.

(3) According to the above (1) and (2), the power consumption of the substrate back bias voltage generating circuit is reduced, so that the battery life can be extended during the battery backup operation. The effect is obtained.

(4) The level limiter function of the P-channel MOSFET whose gate is supplied with the ground potential of the circuit and the use of a diode-type N-channel MOSFET enable a simple circuit configuration and a substantially positive power supply voltage. The effect of being able to detect the level of the negative voltage with reference to the ground potential only by using V _CC is obtained.

The invention made by the present inventor has been specifically described based on the embodiments. However, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say. For example,
In the semiconductor memory device such as a RAM that is in the operating state by the chip select signal, the circuit of FIG. 2, instead of the internal control signal RASB _1, to disable the monitor output of the substrate back bias voltage by the chip select signal It may be something. In addition, an oscillating circuit and a rectifying circuit that operate constantly when the power supply voltage is turned on are not particularly required. The configuration in which the substrate back bias voltage generation circuit is divided into a circuit portion for a steady operation and a circuit portion for an intermittent operation as in the embodiment is in that unnecessary enlargement of the circuit elements constituting the circuit portion for the intermittent operation is prevented. desirable. However, if necessary, a circuit having a weak current supply capability and a circuit having a strong current supply capability may be operated alternatively. A plurality of circuit portions for the intermittent operation may be provided and each may be individually controlled.

In the present invention, the substrate of the term “substrate back bias voltage generating circuit” means one semiconductor region such as a base gate of a field effect element.
It does not mean only a semiconductor substrate. For example, in order to reduce a soft error of a memory based on α rays, a memory cell is formed in a P-type well region formed on the surface of an N-type semiconductor substrate, and a substrate back bias voltage is applied to the P-type well region. Then, the substrate means a P-type well region.

The reference voltage for reading the memory cells constituting the dynamic RAM is obtained by short-circuiting the complementary data lines of the high impedance state and the low level in the high impedance state without using the dummy cells in addition to using the dummy cells. It may be formed. In this case, the reference voltage is at an intermediate level. Peripheral circuits such as an address buffer and an address decoder are constituted by CMOS static circuits.
An address signal is supplied from independent external terminals, and a detection circuit is provided for detecting a change timing of the address signal. Various detection signals are used to generate various timing signals necessary for the operation of the internal circuit. Can be taken.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram of another embodiment .

FIG. 3 is a timing chart for explaining operation;

FIG. 4 is a circuit diagram of another embodiment.

FIG. 5 is a circuit diagram of another embodiment.

FIG. 6 shows an embodiment of a substrate back bias voltage generation circuit.
FIG . Tsu

[Explanation of symbols]

MC: memory cell, DC: dummy cell, CW: column switch, SA: sense amplifier, AR: active restore circuit, R, C-DCR: row / column decoder, AD
B: address buffer, DOB: data signal buffer,
DBI ... data input buffer, TC ... timing control circuit, V _bb -G ... substrate back-bias voltage generation circuit. ,

Claims (3)

(57) [Claims] A first circuit including an insulated gate field effect transistor having a substrate gate to which a substrate back bias voltage is supplied; an oscillation circuit; a first buffer circuit receiving an output signal of the oscillation circuit; A buffer circuit, a gate circuit for controlling transmission of an output of the oscillation circuit to the first buffer circuit, and a negative voltage generated by receiving the outputs of the first and second buffer circuits, respectively. Due to such negative voltage
And the substrate back bias voltage generating circuit including a first and a second rectifier circuit for supplying current to the substrate gate Ri, a level detecting circuit for outputting a control signal by detecting a level of the substrate back-bias voltage at the substrate gate A semiconductor memory device, wherein the operation of the first rectifier circuit is stopped by controlling the gate circuit based on the control signal while the oscillation circuit is operating. 2. The semiconductor device according to claim 1, wherein said first rectifier circuit has a relatively small current supply capability corresponding to a leak current of a substrate. Storage device. Wherein said first circuit is a dynamic random access memory, such a dynamic run
2. The first rectifier circuit according to claim 1, wherein said gate circuit is controlled by a RAS control signal and a refresh control signal supplied to said dumb access memory, and said first rectifier circuit is activated. Semiconductor storage device.