JPH0314023Y2 - - Google Patents

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Publication number
JPH0314023Y2
JPH0314023Y2 JP15287684U JP15287684U JPH0314023Y2 JP H0314023 Y2 JPH0314023 Y2 JP H0314023Y2 JP 15287684 U JP15287684 U JP 15287684U JP 15287684 U JP15287684 U JP 15287684U JP H0314023 Y2 JPH0314023 Y2 JP H0314023Y2
Authority
JP
Japan
Prior art keywords
conductor
ferrite
printed
sheet
sheets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15287684U
Other languages
Japanese (ja)
Other versions
JPS6166911U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15287684U priority Critical patent/JPH0314023Y2/ja
Publication of JPS6166911U publication Critical patent/JPS6166911U/ja
Application granted granted Critical
Publication of JPH0314023Y2 publication Critical patent/JPH0314023Y2/ja
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 〔産業上の利用分野〕 この考案は、積層型ビーズチツプインダクター
の改良に関する。
[Detailed Description of the Invention] [Industrial Application Field] This invention relates to an improvement of a multilayer bead chip inductor.

〔従来の技術〕[Conventional technology]

従来、この種インダクターの製造工程は、先ず
第5図及び第6図に示すように、導体02が印刷
されたフエライトシート01と、導体が印刷され
ていないフエライトシート03とを積層し、これ
を焼成することでフエライトシート01,03を
一体化してビーズチツプ素子04を得る。次い
で、この素子04の両端に外部電極05,05を
設けることで第7図のようなビーズチツプインダ
クターを完成する。
Conventionally, in the manufacturing process of this type of inductor, as shown in FIGS. 5 and 6, first, a ferrite sheet 01 on which a conductor 02 is printed and a ferrite sheet 03 on which no conductor is printed are laminated, and then the ferrite sheet 03 is laminated. By firing, the ferrite sheets 01 and 03 are integrated to obtain a bead chip element 04. Next, by providing external electrodes 05, 05 at both ends of this element 04, a bead chip inductor as shown in FIG. 7 is completed.

〔考案が解決しようとする問題点〕[Problem that the invention attempts to solve]

上記構成のインダクターにおいては、焼成工程
において印刷導体02のフエライトシート01,
03への拡散及び蒸発が発生し、直流抵抗の増大
によるQ値の低下が生じ、品質の安定化を損う大
きい原因となつていた。
In the inductor with the above configuration, the ferrite sheet 01 of the printed conductor 02,
Diffusion and evaporation into 03 occur, and the Q value decreases due to an increase in DC resistance, which is a major cause of impairing quality stability.

この考案は、フエライトシートの積層構造に改
良を加えることで上記従来欠点を解消しようとし
たものである。
This invention attempts to solve the above-mentioned conventional drawbacks by improving the laminated structure of ferrite sheets.

〔問題を解決するための手段〕[Means to solve the problem]

そこで本考案においては、主導体を印刷したフ
エライトシートを、中央で絶縁分断されたダミー
導体を印刷した一対のフエライトシートで挾み込
んで焼成した構造とした。
Therefore, in the present invention, a ferrite sheet on which a main conductor is printed is sandwiched between a pair of ferrite sheets on which a dummy conductor, which is insulated and separated at the center, is printed, and then fired.

〔作用〕[Effect]

上記構造によると、焼成時において中央の主導
体に対して外層となるダミー導体の拡散及び蒸発
も同時に起こり、主導体の周囲に導体雰囲気濃度
が高まり、主導体の拡散及び蒸発が抑制されるこ
とになる。
According to the above structure, during firing, the diffusion and evaporation of the dummy conductor, which is the outer layer relative to the central main conductor, occur simultaneously, increasing the conductor atmosphere concentration around the main conductor, and suppressing the diffusion and evaporation of the main conductor. become.

〔実施例〕〔Example〕

本考案による積層型ビーズチツプインダクター
の製造工程を第1図乃至第4図に基づいて順に説
明する。
The manufacturing process of the multilayer bead chip inductor according to the present invention will be explained in order with reference to FIGS. 1 to 4.

このインダクターは7枚のフエライトシートが
積層焼成されたものである。中央のフエライトシ
ート1には主導体2がH字状に印刷形成され、こ
の中央フエライトシート1の上下に、H字形の中
央が絶縁分断された一組のダミー導体3,3を印
刷した一対のフエライトシート4,4が配置さ
れ、更に、これらの上下に導体が印刷されていな
いフエライトシート5,6が2枚づつ配置され、
これらフエライトシート1,4,5,6群を第2
図に示すように積層して焼成することでビーズチ
ツプ素子7を形成し、その後に、素子7の両端
に、主導体2の両端に接続された外部電極8,8
が設けられる。
This inductor is made by laminating and firing seven ferrite sheets. A main conductor 2 is printed in an H-shape on the central ferrite sheet 1, and a pair of dummy conductors 3, 3 are printed on the upper and lower sides of the central ferrite sheet 1, and the center of the H-shape is insulated and separated. Ferrite sheets 4 and 4 are arranged, and two ferrite sheets 5 and 6 each having no conductor printed above and below these are arranged,
These ferrite sheets 1, 4, 5, and 6 groups are
As shown in the figure, a bead chip element 7 is formed by laminating and firing, and then external electrodes 8, 8 are connected to both ends of the element 7 and to both ends of the main conductor 2.
is provided.

尚、実施例では各フエライトシートとして同一
厚さのものを用いたために7層構造となつている
が、上記フエライトシート5,5及び6,6を
夫々2倍の厚さの1枚シートにして、全体的に5
層構造にするもよく、更にフエライトシート4,
6,6を1枚シートにするとともにフエライトシ
ート5,5を1枚にして、全体的に4層構造にす
ることもできる。また逆にシート厚みを薄くし、
フエライトシート5,5及び6,6の積層枚数を
増やし、主導体2及びダミー導体3,3を中心部
に集中させることも可能である。
In the example, each ferrite sheet had the same thickness, resulting in a seven-layer structure, but the ferrite sheets 5, 5 and 6, 6 were each made into a single sheet with twice the thickness. , overall 5
It is also possible to have a layered structure, and furthermore, a ferrite sheet 4,
It is also possible to make the ferrite sheets 5, 5 into one sheet together with the ferrite sheets 5, 5 into one sheet, resulting in a four-layer structure as a whole. On the other hand, by reducing the sheet thickness,
It is also possible to increase the number of laminated ferrite sheets 5, 5 and 6, 6 and to concentrate the main conductors 2 and dummy conductors 3, 3 in the center.

〔考案の効果〕[Effect of idea]

以上説明したように、本考案においてはダミー
導体を導入することで、焼成時の導体拡散蒸発の
ほとんどを、このダミー導体に担わせ、これによ
り主導体の拡散蒸発を抑制し、品質の安定した積
層型ビーズチツプインダクターを得ることができ
るようになつた。
As explained above, in this invention, by introducing a dummy conductor, most of the conductor diffusion and evaporation during firing is carried out by this dummy conductor, thereby suppressing the diffusion and evaporation of the main conductor and ensuring stable quality. It is now possible to obtain a multilayer bead chip inductor.

しかも、ダミー導体自体は両端外部電極に導通
しないように中央で予め絶縁分断してあるので、
絶縁分断していない場合に起こりうる等価的導体
総断面積の増加によるインダクタンス値の低下と
いう恐れが無く、主導体のみによる所定の性能を
発揮させることができるのである。
Moreover, the dummy conductor itself is pre-insulated and separated at the center so that it does not conduct to the external electrodes at both ends.
There is no fear that the inductance value will decrease due to an increase in the total cross-sectional area of the equivalent conductor, which would occur if insulation is not separated, and it is possible to achieve the desired performance using only the main conductor.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案にかゝる積層型ビーズチツプイ
ンダクターの組成を示す分解斜視図、第2図は積
層状態での斜視図、第3図はその縦断側面図、第
4図は完成品の外観図である。第5図は従来品の
分解斜視図、第6図は積層状態での斜視図、第7
図は完成品の外観図である。 1…フエライトシート、2……主導体、3……
ダミー導体、4……フエライトシート。
Fig. 1 is an exploded perspective view showing the composition of the multilayer bead chip inductor according to the present invention, Fig. 2 is a perspective view of the laminated state, Fig. 3 is a vertical side view thereof, and Fig. 4 is the finished product. FIG. Fig. 5 is an exploded perspective view of the conventional product, Fig. 6 is a perspective view of the stacked state, and Fig. 7 is an exploded perspective view of the conventional product.
The figure is an external view of the finished product. 1... Ferrite sheet, 2... Main conductor, 3...
Dummy conductor, 4...ferrite sheet.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 表面に主導体2が印刷されたフエライトシート
1を、中央で絶縁分断されたダミー導体3,3が
印刷された一対のフエライトシート4,4で挾み
込んで焼成してある積層型ビーズチツプインダク
ター。
A laminated bead chip in which a ferrite sheet 1 with a main conductor 2 printed on its surface is sandwiched between a pair of ferrite sheets 4, 4, each printed with a dummy conductor 3, which is insulated and separated at the center, and fired. Ductor.
JP15287684U 1984-10-09 1984-10-09 Expired JPH0314023Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15287684U JPH0314023Y2 (en) 1984-10-09 1984-10-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15287684U JPH0314023Y2 (en) 1984-10-09 1984-10-09

Publications (2)

Publication Number Publication Date
JPS6166911U JPS6166911U (en) 1986-05-08
JPH0314023Y2 true JPH0314023Y2 (en) 1991-03-28

Family

ID=30710922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15287684U Expired JPH0314023Y2 (en) 1984-10-09 1984-10-09

Country Status (1)

Country Link
JP (1) JPH0314023Y2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258813A (en) * 1988-08-24 1990-02-28 Murata Mfg Co Ltd Layer-built inductor
JP6451689B2 (en) 2016-05-06 2019-01-16 株式会社村田製作所 High frequency noise countermeasure circuit

Also Published As

Publication number Publication date
JPS6166911U (en) 1986-05-08

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