JPH031397A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To access a redundant cell in advance and to execute efficient inspection by inputting an external select signal from an external pad before work to cut plural fuses is executed. CONSTITUTION:When the select signal to instruct the prescribed redundant cell is inputted form an external pad 6, a redundancy forcible selecting circuit 5 outputs a select instructing signal to select and instruct the redundant cell. The select instructing signal sets an address decoder 4 in the side of the redundant cell to an activated state regardless of compared and decided results from a redundancy comparator circuit 1 and a redundancy deciding circuit 2. Accordingly, since the redundant cell can be accessed and the quality of the said redundant cell can be immediately inspected, it is not necessary to execute the complicated fuse cutting work when the redundant cell is decided to be defective in advance. Thus, the efficient inspection can be executed.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor integrated circuit, and more specifically to a redundant cell selection circuit for selecting a redundant cell provided in a semiconductor memory device.
The purpose of the present invention is to provide a semiconductor integrated circuit that can efficiently test semiconductor memory devices, and to provide a control signal that instructs the address of a defective cell by a combination of cutting and non-cutting of multiple fuses, and an external address signal. A redundancy comparison circuit that compares the In a semiconductor integrated circuit comprising a redundancy determination circuit that deactivates an address decoder on a cell side and activates an address decoder on a redundant cell side, a redundant cell is selected and instructed by a select signal from an external pad, A redundancy forced selection circuit is provided which activates the address decoder on the redundant cell side using the selection instruction signal.

[Industrial Field of Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a redundant cell selection circuit for selecting redundant cells included in a semiconductor memory device.

In recent years, as the degree of integration of semiconductor integrated circuits has increased, it has become essential to provide redundant cells. Furthermore, if a redundant cell is defective due to its purpose of use, it means that the semiconductor memory device itself is defective. Therefore, it is important to know in advance whether or not a redundant cell itself is defective in order to improve the efficiency of testing time in a semiconductor memory device.

[Prior Art] Conventionally, in a semiconductor memory device, when one of a large number of cells constituting a storage area is defective, the defective cell is switched to a redundant cell. As a switching means, the semiconductor memory device is provided with a redundant cell selection circuit, and the selection circuit disconnects a fuse provided in the semiconductor memory device and performs switching using a control signal generated based on the disconnection.

As shown in FIG. 4, the redundant cell selection circuit is composed of a redundancy comparison circuit 1, a redundancy determination circuit 2, a normal address predecoder 3, a redundancy address decoder 4, etc. A control signal (if the fuse is cut, a control signal with a logical value rHJ) and an external address signal are input, the two are compared, and the comparison result is determined by the redundancy determination circuit 2 in the next stage.

When it is determined that a redundant cell is not selected without disconnecting the fuse, the determination circuit 2 outputs an activation/deactivation signal for activating the normal address predecoder 3 and deactivating the redundant address decoder 4. On the other hand, when it is determined that a redundant cell is selected by cutting the fuse, the determination circuit 2 outputs a selection signal for activating the redundant address decoder 4 and deactivating the address predecoder 3.

When a redundant cell is selected in this manner, the selected redundant cell is inspected for quality, and if it is found to be defective, the semiconductor memory device is considered unusable and discarded.

[Problem to be Solved by the Invention] Accordingly, when a defective cell is discovered during the inspection of a semiconductor memory device, the fuse is cut to compensate for the defect and the fuse is cut and the cell is switched to a redundant cell. After that, the defective cell is inspected to see if it is defective. , they were forced to perform extremely inefficient inspection work.

In other words, if a redundant cell can be accessed in advance without cutting its fuses to determine whether it is good or bad, if the redundant cell is defective, the defective cell will be discovered and the fuse will be cut to compensate for the defective cell, and the switch will be made to the redundant cell. This eliminates the need for work and the need for meaningless work and inspection. In particular, the work of cutting fuses is very time consuming and has been an obstacle to improving the efficiency of inspections.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that allows access to redundant cells in advance and allows efficient testing of semiconductor memory devices.

Means to solve problem C] FIG. 1 is a diagram explaining the principle of the present invention.

In a semiconductor memory device equipped with redundant cells, a redundancy comparison circuit l is provided which compares a control signal instructing the address of a defective cell with an external address signal by a combination of cutting and non-cutting of a plurality of fuses. A redundancy determination circuit 2 is provided which determines whether or not the external address signal is accessing the address of a defective cell based on the comparison result from the circuit 1. When accessing the address of a defective cell, the redundancy determination circuit 2 deactivates the address decoder 3 on the defective cell side and activates the address decoder 4 on the redundant cell side.

Further, the semiconductor memory device includes a redundancy forced selection circuit 5 which instructs selection of a redundant cell using an external puff draw and a select signal from the same pad, and activates an address decoder 4 on the redundant cell side with the selection instruction signal. It is provided.

[Function] When the redundancy forced selection circuit 5 receives a selection signal from an external puff drawer that designates a predetermined redundant cell, it outputs a selection designation signal that designates the selection of that redundant cell. The address decoder 4 on the redundant cell side is activated regardless of the comparison/determination result of the redundancy determination circuit 2.

[Embodiment] An embodiment in which the present invention is embodied in a redundant cell selection circuit provided in a semiconductor memory device will be described below with reference to the drawings.

For convenience of explanation, the external address signal of the semiconductor memory device of this embodiment is composed of 8 bits, and there are 4 systems of redundant cells in the row direction and 2 systems of redundant cells in the column direction, for a total of 6 systems. Redundant cells for the grid are provided.

FIG. 2 shows a forced selection circuit diagram, in which the forced selection circuit 11 has six
NAND circuits 12a to 12f and three NOT circuits 13
A 3-bit external select signal is input from three external pads 14a to 14C provided on the substrate of the semiconductor memory device. The forced selection circuit 11 is a decoder circuit that receives a 3-bit external selection signal (
When a logic value (excluding rL, L, LJ and rH, H, HJ) is input, only the output of a predetermined one of the six NAND circuits 12a to 12f is output based on the select signal. The logical value becomes "L".

The output terminals of each of the NAND circuits 12a to 12f correspond to the redundant cells of the six systems, respectively, and when the output of the NAND circuit has a logical value rLJ, the redundant cell of the system corresponding to the NAND circuit with the logical value rLJ is selected. It is designed to be instructed. Therefore, by applying a test probe to each of the external pads 14a to 14c and outputting an external selection signal via the probe, the forced selection circuit 11 selects one system of redundant cells from among the six systems of redundant cells. The selection can be instructed.

Next, the redundancy determination circuit 15 which activates the redundant cells of the corresponding system based on the selection instruction signal from the forced selection circuit 11 will be explained with reference to FIG. Note that the redundancy determination circuit 15 is provided for each redundant cell of each system,
The circuit configurations are substantially the same, so for convenience of explanation, the third
In the figure, only the redundancy determination circuit 15 of one system of redundant cells is shown.

First, the redundancy comparison circuit 16 provided in the preceding stage of the redundancy determination circuit 15 will be explained. The comparison circuit 16 is composed of a comparison circuit section 16a provided for each beat/) of the 8-bit external address signal. The circuit section 16a includes two gate circuits 1 consisting of P-type and N-type MOS transistors.
7.18 and one knot circuit 19. A corresponding bit signal in the external address signal is input to one gate circuit 17, and a bit signal obtained by inverting the bit signal is input to the other gate circuit 18.

Further, both gate circuits 17 and 18 input directly and via the knot circuit 19 a control signal for determining whether or not to disconnect a fuse provided corresponding to the bit as a gate signal. The logical value of the control signal is "H" when the fuse is disconnected, and "L" when it is not disconnected. As a result, only when the control signal and the bit signal have the same logical value, the comparison circuit section 16a outputs a comparison signal having the logical value rHJ.

Therefore, when each fuse is disconnected or not disconnected according to the logical value of each bit signal of the external address signal, the redundancy comparison circuit 16 detects that each fuse is disconnected in accordance with the address of the defective cell. , when an external address signal for accessing the address of a defective cell is input, all comparison signals output from each comparison circuit section 16a become rHJ.

The redundancy determination circuit 15 consists of three NAND circuits 20°21.22
and one software circuit 23, and a NAND circuit 2
0 inputs the comparison signals of each comparison circuit section 16a of the redundant comparison circuit 16, and when all the comparison signals of the comparison circuit section 16a are rHJ, the external address signal accesses the address corresponding to the defective cell; That is, it outputs a determination signal of logical value "L" which means accessing a redundant cell to replace a defective cell. On the contrary, the judgment signal has a logical value rHJ
When , it means that the external address signal does not access the address corresponding to the defective cell, that is, the redundant cell is not accessed.

The next-stage NAND circuit 21 receives the determination signal and the selection instruction signal output from the corresponding NAND circuit of the forced selection circuit 11. When at least one of the logical values of the selection instruction signal or the determination signal is rLJ, the external address signal or the external pads 14a to 14c
The NAND circuit 21 outputs an output signal of logical value rHJ assuming that the redundant cell is being accessed from at least one of the external select numbers Hg from . Further, when neither the external address signal nor the external select signal accesses a redundant cell, the NAND circuit 21 outputs an output signal of logical value rLJ.

The NAND circuit 22 at the next stage manually generates the activation signal, the fuse determination signal, and the output signal from the NAND circuit 21 at the previous stage.

Note that the output of the activation signal and the fuse determination signal has a logical value rHJ when the semiconductor memory device is in an operating state and an external address signal or external select signal is input.

Therefore, when the output signal is rHJO, the output of the NAND circuit 22 becomes the logical value rLJ, and the output of rLJ directly becomes an "L" predecoder activation/inactivation signal that deactivates the predecoder (not shown). At the same time, it becomes an rHJ predecoder activation/inactivation signal that activates a redundant decoder (not shown) via the software circuit 23. On the contrary, when the output signal is rLJ, the output of the NAND circuit 22 becomes the logical value rHJ, and its "H" output becomes the rHJ predecoder activation/deactivation signal that activates the predecoder, and also serves as the redundant decoder activation/inactivation signal. This is a predecoder activation/inactivation signal for rLJ that deactivates the rLJ.

In the redundant cell selection circuit configured in this way, a predetermined redundant cell is inspected for quality before cutting a plurality of fuses as appropriate and creating a control signal that instructs the address of a defective cell by a combination of cutting and non-cutting. When an external select signal is output from the external pads 14a to 14c to the forced selection circuit 11 in order to perform the
A selection instruction signal is output. In the NAND circuit 21, the redundancy determination circuit 15 outputs the rHJ output signal to the next stage NAND circuit 22 based on the rLJ selection instruction signal, regardless of the logical value of the comparison signal from the comparison circuit 16. Then, the NAND circuit 22 activates the redundant decoder and puts the redundant cell in an access state.

As described in detail above, in this embodiment, the external pads 14a to 14 are
By simply inputting External Select No. 1 from C, you can access the redundant cell and immediately check whether the redundant cell is good or bad, so if the redundant cell is determined to be defective in advance, you can eliminate the troublesome fuse There is no need for cutting work, making it possible to perform very efficient inspections.

It should be noted that the present invention is not limited to the embodiment described above, and for example, in the embodiment described above, the selection instruction signal of the forced redundancy selection circuit 11 is inputted together with the determination signal to the NAND circuit 21 of the redundancy determination circuit 15, and the redundancy determination circuit Although the redundant cells are accessed through the redundancy determination circuit 15, the redundancy decoder may be activated without going through the redundancy determination circuit 15.

[Effects of the Invention] As described in detail above, the semiconductor integrated circuit of the present invention can access redundant cells in advance, and exhibits an excellent effect of being able to efficiently test a semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a diagram showing a forced selection circuit in a redundant cell selection circuit embodying the present invention. FIG. 3 is a redundancy comparison in a redundant cell selection circuit embodying the present invention. FIG. 4 is a diagram showing a conventional redundant cell selection circuit. In the figure, 1 is a redundancy comparison circuit, 2 is a redundancy determination circuit, 3 is an address decoder, 4 is a redundancy address decoder, 5 is a redundancy forced selection circuit, and 6 is an external pad. Figure 1 Detailed explanation of the present invention

Claims (1)

[Claims] 1. A redundancy comparison circuit (1) that compares a control signal instructing the address of a defective cell with an external address signal by a combination of cutting and non-cutting of a plurality of fuses; ), it is determined whether the external address signal is accessing the address of a defective cell or not, and when the address of the defective cell is being accessed, the address decoder (3) on the defective cell side is inactivated. In a semiconductor integrated circuit comprising a redundancy judgment circuit (2) which activates an address decoder (4) on the redundant cell side, the redundancy determination circuit (2) selects a redundant cell using a select signal from an external pad (6), and selects the redundant cell. A redundancy forced selection circuit (
5) A semiconductor integrated circuit characterized by providing the following.