JPH02210686A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve redundancy efficiency by providing a shared spare line substitutable a defective word line or bit line on an ordinary cell array selectively in a redundant cell array. CONSTITUTION:It is assumed that either the word lines WL in the ordinary cell array 3 is defective. The row address data RA and the inverse of RA of a defective cell are compared with row defective cell address data RRA and the inverse of RRA from a row defective cell address memory 7x at a row address comparator 8x. When both data coincide, the comparator 8x outputs a coincidence signal RRS. In the signal RRS, command information to perform redundancy and information to instruct which spare line of spare lines RWL0-7 in the redundant cell array 16 should be used are included. A row decoder 2 becomes inactive by the signal. The coincidence signal is inputted to a row selection circuit 14, and since no column selection signal CRS from the comparator 8x exists at that time, the circuit 14 outputs a signal representing a content corresponding to the coincidence signal to a redundant X decoder 15x, an address switching circuit 17, and an input/output buffer 15. The decoder 15x decodes the coincidence signal, and selects the spare line RWL0-7 in the array 16.

Description

[Detailed Description of the Invention] (II!E required) The present invention relates to a semiconductor memory device, and an object of the present invention is to provide a semiconductor memory device that can maximize the function of redundant memory and improve redundancy efficiency. , a semiconductor memory device comprising a normal cell array and a redundant cell array capable of replacing a defective portion in the normal cell array, wherein the redundant cell array selectively replaces a defective word line or a defective bit line in the normal cell array. Constructed with a replaceable shared spare line.

[Industrial application field]

The present invention relates to semiconductor memory devices.

As semiconductor memories become smaller and have larger capacities, the number of defective cells in the semiconductor memory manufacturing process also increases. Due to the existence of such defects, even though there are many non-defective parts, the entire chip is judged to be defective, resulting in a decrease in yield. Therefore, in order to save chips from such defects, semiconductor memories are provided with redundant circuits.

The redundant circuit programs the address of a defective cell detected during a wafer probing test among the memory cells of a semiconductor memory (hereinafter referred to as a normal cell array) into a defective cell address memory, and when the defective cell is accessed, Based on the programming data of the defective cell address memory, the defective cell is stored in the redundant memory (hereinafter referred to as
This is called a redundant cell array. ) to make the chip accessible and save the chip.

[Conventional technology]

FIG. 8 shows an outline of a conventional SRAM redundancy circuit.

First, the access operation to the normal cell array 3 during normal operation will be explained. External address data ADD is applied to row address buffer 1 and column address buffer 4, respectively.

Row address buffer 1 and column address buffer 4 each amplify external address data ADD from TTL level to MOS level, generate address signals A, A of positive phase and reverse phase, and send them to row decoder 2 and column decoder 5. send to

Row decoder 2 and column decoder 5 decode each address signal A, A and select the designated word line WL and bit line BL. In this way, the memory cell MC at the intersection of the selected word line WL and bit line BL
is specified and a read operation is performed. Note that the write operation is basically the same as above, but the write data
The signal flows from lo to the turnout buffer 12, the data switching circuit 9, the column decoder 5, and the sense amplifier 6.

Next, if there is a defective cell due to a bit line defect in the normal cell array 3, the address of the defective cell is known at the time of the wafer probing test, so it is stored in advance in the defective cell address memory 7 (details will be described later). Figure 9 of
(See Figure 10). If the external address data ADD is for a defective cell, the defective cell address memory 7
The address comparison circuit 8 compares the defective address signals F, F and the address signals A, A from the address comparison circuit 8; a match signal ACC is output to the data switching circuit 9. The output of the match signal ACC means that the memory cell MC accessed by the external address data ADD is a defective cell, so the data switching circuit 9 selects the redundant sense amplifier 10 instead of the data from the column decoder 5. The data is switched to the data from the redundant cell RMC of the redundant cell array 11 through the redundant cell array 11.

In this way, the data of the defective cell is replaced with the data of the redundant cell RMC, and even if there is a defective cell in the normal cell array 3, the chip can operate as a good product in appearance. The case of writing is the same as above, and the data flow is as shown above. In the above configuration, the portion surrounded by a broken line is a redundant circuit.

If the number of defects in either bit lines or word lines exceeds the allowable number for the redundant cell array, the chip cannot be considered as a good product even if other healthy lines remain. For example, assuming a redundant cell array with one spare word line and one spare bit line, if only two word lines become defective, it is no longer possible to salvage the chip, and the remaining spare bit line becomes defective. The line is wasted.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that can maximize the function of a redundant cell array and improve redundancy efficiency and therefore yield.

[Problem to be solved by the invention]

The problem with the above-mentioned conventional redundant circuit is that it can only be repaired in a manner set in the redundant cell array, and lacks a degree of freedom.

That is, a defective cell may be caused by a defect in either or both of the bit line and word line corresponding to a certain address.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a semiconductor memory device comprising a normal cell array (3) and a redundant cell array (16) capable of replacing a defective portion in the normal cell array (3), The redundant cell array (16) includes a shared spare line that can selectively replace a defective word line (WL) or defective bit line (BL) in the normal cell array (3).

[Effect]

According to the present invention, since the redundant memory (16) is shared, even if more word lines (WL) or bit lines (BL) become defective, they can be replaced by the remaining spare lines. It is possible to salvage and achieve the purpose.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

First Embodiment FIG. 1 shows a first embodiment of the present invention. In this embodiment, parts that overlap with those in FIG. 3 are given the same reference numerals, and their explanations will be omitted.

In comparing Figures 1 and 3, the differences between the two are:
Row defective cell address memory 7, column defective cell address memory 7, row address comparison circuit 8X1 column address comparison circuit 81, row redundant spare line memory 13, column redundant spare,
It is equipped with a line memory 13, a row Y column selection circuit 14, a redundant X decoder 15, a redundant Y decoder 15, a row and column common redundant cell array (hereinafter simply referred to as redundant cell array) 16, and an address switching circuit 17.

The row defective cell address memory 7x stores the address of a defective word line in the normal cell array 3, and the column defective cell address memory 7Y stores the address of a defective bit line in the normal cell array 3. As the memory cell, a current-blown polysilicon fuse, a laser-blown polysilicon fuse, or the like is used.

The row redundant spare line memory 3
The spare line address is stored in advance in the memory that specifies whether to replace the line. Similarly, the column redundant spare line memory 3Y is a memory for specifying which spare line RWL to RWL in the redundant cell array 16 should replace a defective bit line. Similarly, a polysilicon fuse or the like can be used as the memory cell.

The matrix selection circuit 14 cannot select two redundant spare lines at the same time, so when row and column redundancy are required at the same time, the matrix selection circuit 14 is used to prioritize one of them, and the priority can be set arbitrarily. It is.

The redundant X decoder 15x decodes the data from the column selection circuit 14 to select one of the spare lines RWL-RWL7 of the redundant cell array 16. Redundant Y decoder 15. is a decoder for decoding data from the address switching circuit 17 and selecting the bit line BL.

The redundant cell array 16 is a cell array in which spare lines RWL, to RWL7 and bit lines BL are arranged in a matrix, and can be used to repair either word lines or bit lines. Normally, the cell array 3 is, for example, 4K (rows) x 4K (
Assuming that the redundant cell array 16 is a memory of 8 (rows) x 4K (columns) bits, for example, the redundant cell array 16 uses a memory of 8 (rows) x 4K (columns) bits.

The row address comparison circuit 8x is connected to the row defective cell address memory 7.
Row defective cell address data RRA, RRA from x and row address data RA, RA from row address buffer 1
and spare line designation data DRR from the row redundant spare line memory 13X, and outputs a row selection signal RR5 to the matrix selection circuit 14. Column address comparison circuit 8. compares the column defective cell address data CCA, CCA from the column defective cell address memory 7Y, column address data CA, CA from the column address buffer 4, and spare line designation data DCR, and selects a column for the matrix selection circuit 14. Signal CR8
Output.

Next, the operation will be explained.

Now, it is assumed that one of the word lines WL of the normal cell array 3 is defective. The row address data RA, RA of the defective cell and the row defective cell address data RRA, RRA from the row defective cell address memory 7x are input to the row address comparison circuit 8X, and both data are compared.

When both data match, the row address comparison circuit 8x outputs a match signal RR3. This coincidence signal RR5 includes command information for redundancy and which spare line RW of the redundant cell array 16.
Contains information on whether to use L-RWL7.

Row decoder 2 is inactivated by this match signal RR3. The coincidence signal RR3 is input to the matrix selection circuit 14, and since there is no column selection signal CRS from the row address comparison circuit 8X at this time, the matrix selection circuit 14 switches the signal corresponding to the coincidence signal RR3 to the redundant X decoder 15x1 address. It outputs to the circuit 17 and the input/output buffer 12.

Redundant X decoder 15x decodes match signal RR9 and selects one of spare lines RWLo to RWL7 of redundant cell array 16.

In this way, if there is a defect in the word line WL of the normal cell array 3, the defective word line WL is replaced with one of the spare lines RWLo to RWL7 of the redundant cell array 16, so that the chip can be saved.

On the other hand, if any of the bit lines BL of the normal cell array 3 is defective, the same operations as described above are performed such as the column defective cell address memory 7, the column redundant spare line memory 13, the column address comparison circuit 8, and the matrix selection Y folding circuit 14. , processed by the address switching circuit 17 system,
The defective bit line BL is replaced with any bit line BL of the redundant cell array 16 via the redundant X decoder 15X.

Now, suppose that seven word lines WL in the normal cell array 3 are defective and one bit line BL is defective. In this case, in the redundant cell array 16, the spare line RWL-RWL6 replaces the defective word line WL of the normal cell array 3, and the spare line RWL7 relieves the defective bit line BL of the normal cell array 3. At this time,
Spare line RWL7 and bit line BL are orthogonal to each other,
90'' must be rearranged, but this is done by transferring information to the redundant X decoder 15x via the address switching circuit 17 to the redundant Y decoder 15.

Further, when the coincidence signal RR3 and the column selection signal CR3 are generated simultaneously and compete with each other, the matrix selection circuit 14 processes one of them (for example, the coincidence signal RR8) with priority, and then processes the other (for example, the column selection signal CR8). ).

Thus, according to this embodiment, the word line WL.

It is possible to repair both defects with one redundant cell array 16 without providing a dedicated redundant cell array for each bit line BL, which eliminates the waste of spare lines and improves repair efficiency compared to the conventional method, thereby improving chip yield. can be improved.

Second example Next, FIG. 2 shows a second embodiment of the present invention.

This second embodiment has a redundant cell array 16 of 8 (rows)×4
An array of K (columns) bits is made into an array of 16 (rows) by 2K (columns) bits.

That is, the redundant cell array 16 does not necessarily have the same number of rows as the normal cell array 3. This is a restriction due to the fact that the structure of the redundant cell array 16 requires a larger area than the normal cell array 3.

For example, if the cells of the redundant cell array 16 are constructed of polysilicon layer floating gate type EPROMs, an area is required to form the floating gates with the polysilicon layer.

Therefore, in this embodiment, in order to double the area in the arrangement direction of the word lines WL, which has less restrictions on the occupied area, the spare line RWL
-RWL7. 16 (rows) of bit line B
The arrangement direction of L is 172 2K (columns), and the capacity is also 32 bits.

In this way, since the number of - word lines WL has doubled, an identification bit area 15xa is formed in the redundant X decoder 15x in correspondence with this, and the identification bit area 15xa is logically distributed by '0'al'.

By configuring the cell arrangement of the redundant cell array 16 as described above, the layout on the chip can be made rational.

Third Embodiment This embodiment is an example in which the normal cell array 3 is a mask ROM.

The mask ROM is usually formed of a polysilicon layer, so the redundant cell array 16 is replaced by the normal cell array 3.
In order to form the cell array without significantly changing the manufacturing process, it is necessary to form it with a polysilicon layer in the same way as the normal cell array 3. Must be writable memory.

Therefore, as in this embodiment, the redundant cell array 16 is
OM, and (7) EPROM is made of polysilicon.
It is formed of layers.

FIG. 3(a) is a plan view of the redundant cell array 16 in this embodiment, FIG. 3(b) is a sectional view thereof, and FIG.
) shows an explanatory diagram of the correspondence between a normal EFROM and an EFROM of the present invention.

As shown in FIGS. 3(a) and 3(b), a field oxide film (S i 02 ) 27 is formed on the P-type substrate 28, and a bloating gate FG made of a polysilicon layer is formed on it. There is. An interlayer insulating film (SiO2) 26 is formed on the floating gate FG, and a word line WL is formed via this interlayer insulating film 26. 2
9 is a diffusion layer (N) forming a spare bit line BL, and 30 is a transistor region serving as a redundant cell RMC.

The above structure is electrically equivalent to the EPROM shown in FIG. 3(C). That is, the word line WL is connected to the interlayer insulating film 26.
Since it is arranged to face the floating gate FG through the field oxide film 27, it is equivalent to the control gate CG, and because the floating gate FG is formed on the transistor region 30 through the field oxide film 27, it is a floating gate. 3(b) and (c), the interface between the floating gate FG on the transistor region 30 and the field oxide film 27 is point A, and the interface between the floating gate FG on the diffusion layer 29 and the field oxide film 27 is the point A. The interface with the film 27 corresponds to point B.

The redundant cell formed in this way stores charge in the floating gate FG by the voltage applied between the word line WL and the spare bit line BL, and stores data for the defective cell instead of the normal cell array 3. It turns out.

Thus, according to the third embodiment, it is possible to form a redundant cell that satisfies the requirements of being able to be formed using a polysilicon layer when applied to a mask ROM, and that it is writable. achieve the purpose of

〔Effect of the invention〕

As described above, according to the present invention, the redundant cell array can be shared by word lines and bit lines, so even if the number of defective word lines and bit lines is different, it is restricted to the one with the greater number of defective lines. Relief efficiency can be improved without As a result, the yield of semiconductor memory chips can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram of a third embodiment of the present invention.
FIG. 4 is a block diagram of a conventional SRAM redundant circuit. 1... Row address buffer 2... Row decoder 3... Normal cell array 4... Column address buffer 5... Column decoder 7x... Row defective cell address memory 7Y... Column defective cell address memory 8X... Row address comparison circuit 8,... Column address comparison circuit 13x... Row redundant spare line memory 13,... Column redundant spare line memory 14... Matrix selection circuit 15x... Redundant X decoder 15,...Redundant Y decoder WL...Word line BL...Bit line MC...Memory cell RMC...Redundant cell Fig. 2

Claims (6)

[Claims] 1. Normal cell array (3) and the normal cell array (3)
A semiconductor memory device comprising a redundant cell array (16) capable of replacing a defective portion therein, the redundant cell array (16) being a part of the normal cell array (16).
3) A defective word line (WL) or defective bit line (B
1. A semiconductor memory device comprising a shared spare line that can selectively replace L). 2. 2. The semiconductor memory device according to claim 1, further comprising an address switching circuit (17) for selecting either a row address or a column address and sending the selected address to a decoder of a redundant cell array. Device. Redundant cell array (
16) A semiconductor memory device comprising: 3. A normal cell array (3) and a redundant cell array (3) that can replace defective parts in the cell array (3).
16), wherein the redundant cell array (16) includes the normal cell array (16).
The defective word line (WL) and defective bit line (WL) in 3)
1. A semiconductor memory device comprising a plurality of shared spare lines that can be individually and selectively replaced. 4. 4. The semiconductor memory device according to claim 3, wherein the spare line of the redundant cell array is formed by a word line. 5. 4. The semiconductor memory device according to claim 3, wherein the spare line of the redundant cell array is formed by a bit line. 6. 4. The semiconductor memory device according to claim 3, further comprising an address switching circuit (17) for selecting either a row address or a column address and sending the selected address to a decoder of a redundant cell array. memory device. 7. In the semiconductor memory device according to claim 3, a circuit (13X, 13Y) stores the defective address of the defective word line and the defective bit line, and also stores information on whether to switch to one of the plurality of spare lines. ) A semiconductor memory device characterized by having: 8. In the semiconductor memory device according to claim 3, if the external address coincides with an address stored in the row defective address memory and an address stored in the column defective address memory at the same time, either the row or the column is selected. A semiconductor memory device characterized by comprising a matrix selection circuit (14) for redundancy.