JPH03136474A - Feedback type peak clamp circuit - Google Patents

Abstract

PURPOSE:To reduce the number of pins providing a capacitor for clamp to be one by forming a peak clamp circuit to be a feedback type. CONSTITUTION:A video signal is supplied from an input terminal 1 to a differential amplifier 2 composed of transistors 28 and 29 and in a comparator circuit 4, the output signal of the differential amplifier 2 is compared with a reference voltage 3 for clamp. In a clamp capacitor 7, the output current of the comparator circuit 4 is converted to a voltage and held. In an inverted amplifier 8, the voltage held in the clamp capacitor 7 is inverted and the output voltage of the inverted amplifier 8 is supplied to the transistor 29 constituting the differential amplifier 2. Then, a clamp output is taken out from the output of the differential amplifier 2. Thus, the number of IC pin terminals for connecting the clamp capacitor 7 can be reduced to be one and even when using a power source which power supply voltage is low and stability is lacked, a feedback type peak clamp circuit, which is not affected by the fluctuation of the power supply voltage, can be obtained with a sufficiently wide dynamic range.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a feedback type peak clamp circuit that clamps an input signal such as a video signal to a predetermined voltage and outputs the clamped signal.

[Conventional technology]

As means for clamping an input signal such as a video signal to a predetermined voltage, there is a peak clamp circuit that sets the lowest or highest voltage of the input signal to a predetermined voltage, and a peak clamp circuit that clamps the input signal for a predetermined period (for example, a part of the pedestal period or a synchronization signal). There is a synchronous clamp circuit that sets a predetermined voltage during a part of the period.

Among the above-mentioned clamp circuits, an example of a conventional configuration of a synchronous type clamp circuit is described in Japanese Patent Application Laid-Open No. 63-305577, but the peak clamp circuit is not considered.

FIG. 3 shows an example of a conventional peak clamp circuit. Third
In the figure, 101i02,10! 1 is an NPN transistor. A reference voltage source 105 is connected to the base of the transistor 1010. A collector of transistor 101 is connected to power supply terminal 104. The emitter of the transistor 101 is connected to the input terminal 1 via the IC pin terminal 111, the capacitor 106, and the IC pin terminal 110.
07 and to the pace of transistor 102. The emitter of transistor 102 is connected to the pace of transistor 103, and transistor 102
The collectors of 1 and 103 are commonly connected, and transistors 102 and 103 constitute a Cedarlington-connected emitter 7 lower transistor. A common connection point of transistors 102 and 103 is connected to power supply terminal 104. The emitter of the transistor 103 is the current source 108
An output terminal 109 is connected to the ground through the emitter of the transistor 103 .

The pace emitter voltage of the transistor 101 is V□1
01, when the voltage of the reference voltage source 105 is "11", the voltage "12" of the emitter of the transistor 101 becomes V12 "vll VBllol. Therefore, the 'α pressure supplied from the input terminal 107 is the voltage V1
When the voltage is lower than 2, the current flowing through the transistor 101 charges the υ capacitor 106, and the transistor 102
The voltage applied to 0 base is raised to voltage V12. The voltage supplied from the input terminal 107 is voltage "12"
When higher, transistor 101 cuts off.

The charge stored in the capacitor 106 is gradually discharged by the pace current of the transistor 102, and the voltage applied to the pace of the transistor 102 is gradually lowered.

The peak clamp circuit charges T to the capacitor 106.
! Since the L'fjL current is large and the discharge current is small, a signal at a level lower than the clamp voltage is clamped instantaneously, and a response to a signal at a level higher than the clamp voltage is slow. In this way, the sync tip level in the synchronization signal of the video signal supplied from the input terminal 107 is clamped to the voltage V12, and the transistor 102
and is taken out from the output terminal 109.

[Problem to be solved by the invention]

As mentioned above, in the conventional peak clamp circuit, in order to connect the clamp capacitor which is an external component of the circuit C, the I
When converted to C, at least two pin terminals are required.

The present invention has a single IC pin terminal for connecting a clamp capacitor which is an external part of the IC, and a t
#An object of the present invention is to provide a feedback type peak clamp circuit that has a sufficiently wide dynamic range and is not affected by power supply voltage fluctuations even when a power supply with low voltage and lacking stability is used.

[Means to solve the problem]

The present invention provides a differential amplifier including a first transistor and a second transistor to which an input signal is supplied; a comparison circuit that compares the output signal of the differential amplifier with the voltage of a first reference voltage source; A second transistor that includes a clamp capacitor that converts the output current of the comparator circuit into a voltage and holds it, and an inverting amplifier that inverts the voltage held by the clamp capacitor, and that configures a differential amplifier that converts the output voltage of the inverting amplifier into a voltage. This is achieved by supplying the differential amplifier to the differential amplifier and extracting the clamp output from the output of the differential amplifier, and by using the clamp capacitor grounded.

[Effect]

From input terminal 1, transistor 28 and transistor 29
A video signal is supplied to a differential amplifier 2 consisting of a comparator circuit 4, which compares the output signal of the differential amplifier 2 with a reference voltage for clamping, and a clamp capacitor 7 converts the output current of the comparator circuit 4 into a voltage and holds it. The voltage held by the clamp capacitor 7 is inverted by the inverting amplifier 8, the output voltage of the inverting amplifier 8 is supplied to the transistor 29 constituting the differential amplifier 2, and the clamp output is taken from the output of the differential amplifier 2. υ is released.

〔Example〕 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a basic block diagram of a feedback type peak clamp circuit according to the present invention. In Fig. 1, 1 is a signal input terminal, 2 is a differential amplifier, 3 is a reference voltage source for clamping, 4 is a comparison circuit, and 5 is only when the voltage in comparison circuit 4 becomes lower than the voltage of reference voltage source 3 for clamping. A voltage-current conversion circuit that converts the error output into a current, 6 is an IC pin terminal when integrated, 7 is a clamp capacitor that converts the current of the voltage-current conversion circuit 5 into voltage and holds it, 8 is a clamp 9 is an output terminal of an inverting amplifier for inverting the voltage held by the capacitor.

Next, the operation of the principle block diagram shown in FIG. 1 will be explained.

When the voltage at the output terminal 9 is lower than the voltage at the clamp reference voltage source 3, that is, when the voltage supplied from the input terminal 1 is lower than the output voltage from the inverting amplifier 8, the comparator circuit 4
It is converted into a current at the voltage-current conversion port wr5, and the current flows into the clamp capacitor 7. Therefore, the input voltage of the inverting amplifier 8 increases, and therefore the output voltage of the inverting amplifier 8 decreases. Therefore, the voltage at the negative phase input terminal of the differential amplifier 2 decreases. The feedback described above works until the voltages at the positive-phase and negative-phase input terminals of the differential amplifier 2 become equal. At this time, the voltage at the output terminal 9 becomes almost equal to the reference voltage of the clamping reference voltage source 30. When the voltage is higher than the voltage of the clamp reference voltage source 3, that is, when the voltage supplied from the input terminal 1 is high, current is not supplied from the comparator circuit 4 and the voltage constant current conversion circuit 5 to the clamp capacitor 7. stops. Therefore, the input voltage of the inverting amplifier 8 is held by the charge accumulated in the clamp capacitor 7. Therefore, the output of the inverting amplifier 8, ie, the negative phase input voltage of the differential amplifier 2, is also held. In this way, the sync tip level in the synchronization signal of the video signal supplied from the input terminal 1 is clamped to the voltage of the clamping reference voltage source 3 and taken out from the output terminal 9.

FIG. 2 shows a specific circuit of the feedback type peak clamp circuit according to the present invention. 1 is an input terminal, 2 is a differential amplifier, 3 is a reference voltage for clamping, 4 is a comparison circuit, 5 is a voltage-current conversion circuit, 6 is an IC bin terminal, 7 is a capacitor for clamping, 8 is an inverting amplifier, 9 is an output terminal, 14 to 17 are resistors,
18-27 are NPN) transistors, 28-35 are PNP
) transistors, 56 to 42 are current sources, and 44 is a power supply terminal.

In the figure, a transistor 28.29Kl differential amplifier 2 is configured, and the base of the transistor 28 is connected to the input terminal 1.
The base of the transistor 29 is connected to the resistor 17, the collector of the transistor 27, and the current source 42, respectively. The collector of the transistor 2B is connected to the collector and base of the diode-connected transistor 18 and the base of the transistor 21, and the transistors 18 and 21 form a dual current mirror.

The emitter of the transistor 28 is connected to a current source 36 and one end of the resistor 14), and the other end of the resistor 14 is commonly connected to a current source 37 and the emitter of the transistor 29. The collector of the transistor 29 is connected to the collector and base of the diode-connected transistor 19 and the base of the transistor 20, and the transistors 19 and 20 constitute the dynoelectrode 2. The collector of the transistor 20 is connected to the collector and base of a diode-connected transistor 30 and to the base of a transistor 31, and the transistors 30 and 31 form a dual current mirror.

The collector of the transistor 31 is the output terminal 9, the collector of the transistor 21, the base of the transistor 22, and the resistor 1.
5 and are commonly connected to one end of the 5. The other end of this resistor 15 is commonly connected to the reference voltage 3, the base of the transistor 25.35, and the opposite end of the resistor 17. The emitter of the transistor 22 and the emitter of the current source 38 are commonly connected to form a comparator circuit 4. The collector of the transistor 23 is commonly connected to the collector and base of the diode-connected transistor 32 and the base of the transistor 33, and the transistors 32 and 33 form a dielectric current collector. The collector of the transistor 33 is
The base of the transistor 24 is commonly connected to one end of a clamp capacitor 7 via the IC pin terminal 6, and the other end of the clamp capacitor 7 is grounded. The emitter of the transistor 24 is connected to the base of the transistor 25, and the collector of the transistor 24 and the collector of the transistor 25 are commonly connected and connected to the power supply terminal 44, thereby forming a Darlington-connected emitter follower transistor. The emitter of transistor 25 is commonly connected to transistor 540 and current source 39 . The emitter of this transistor 34 is connected to a current source 40 and a resistor 1.
It is commonly connected to one end of 6. The other end of this resistor 16 is
It is commonly connected to the emitter of the transistor 35 and the current source 41 . The collector of the transistor 55 is commonly connected to the collector and base of the diode-connected transistor 26 and the base of the transistor 27, and the transistors 26 and 27 form a current mirror. The transistors 34 and 55 constitute an inverting amplifier 8.

Next, the operation of the configuration shown in FIG. 2 will be explained.

3 of the current connected to the emitter of transistor 28
The current value of the transistor 6 and the current value of the current 57 connected to the emitter of the transistor 29 are set to be approximately equal. Further, the current values of the current source 40 connected to the emitter of the transistor 34, the current source 41 connected to the emitter of the transistor 35, and the current source 42 connected to the collector of the transistor 27 are also set approximately equal. has been done.

When the voltage No. 48 supplied from the input terminal 1 is lower than the base voltage of the transistor 290, current flows from the current source 37 to the emitter of the transistor 28 via the resistor 14. A current also flows from the current source 36 into the emitter of the transistor 28, and when the base voltage of the transistor 28 and the base voltage of the transistor 29 are equal, the current flowing into the emitter of the transistor 2B increases.

However, since the transistors 18 and 21 constitute a dyad current mirror, the collector current of the transistor 21 increases. On the other hand, since current flows from the current source 67 to the resistor 14, the current flowing into the emitter of the transistor 29 decreases. Since transistors 19 and 20 and transistors 30 and 31 each constitute a current mirror, the collector current of transistor 61 is reduced. Therefore, as a difference current between the collector current of the transistor 21 and the collector current of the transistor 31, a current flows from the clamping reference voltage source 3 to the collector of the transistor 21 via the resistor 15, and the base voltage of the transistor 22 becomes the clamping reference voltage. The voltage of the voltage source 5 becomes lower.

In the comparison circuit 4, when the base voltage of the transistor 220 becomes lower than the base voltage of the transistor 25, the transistor 22 is turned off and the transistor 23 is turned on. Therefore, the current of the current source 38 is supplied via the transistor 23 to the collector of the transistor 62 constituting the current mirror, and this current flows into the capacitor 7, causing the base voltage of the transistor 24 to rise to 9. The base voltage also increases.

When the base voltage of the transistor 34 becomes higher than the base voltage of the transistor 35, a current flows into the emitter of the transistor 35 via the current source 40 and the υ resistor 16. Since the current value of the current source 41 and the current value of the current source 42 are set to be approximately equal, the current flowing into the emitter of the transistor 35 via the current source 40 and the resistor 16 is transferred to the clamping reference voltage source 5. It flows into the collector of the transistor 27 via the resistor 17t-. Therefore, the base voltage of transistor 29 decreases. In this way, when the voltage supplied from the input terminal 1 decreases, the voltage fed back to the base of the transistor 29 also decreases. This return is
It acts until the voltage at the input terminal 1 and the base voltage of the transistor 29 become almost equal, and the voltage at the output terminal 9 becomes almost equal to the voltage of the clamping reference voltage source 3.

Further, when the voltage of the signal supplied from the input terminal 1 is higher than the base voltage of the transistor 29,
A current flows from the resistor 14 to the emitter of the transistor 29. Current also flows from the current source 37 into the emitter of the transistor 29. Therefore, the current flowing into the emitter of transistor 29 increases. Transistors 19 and 20 and transistors 30 and 31 constitute current mirror 2, so transistor 3
1's collector current increases. Furthermore, since current flows from the current source 36 to the resistor 14, the current flowing into the emitter of the transistor 28 decreases. Transistor 18.21
Since a current mirror is configured, the collector current of the transistor 21 is reduced. transistor 31
A difference current between the collector current of the transistor 21 and the collector current of the transistor 21 flows into the crank reference voltage source 3 via the resistor 15. Therefore, the base voltage of the transistor 22 becomes higher than the voltage of the crank reference voltage source 5. In the comparison circuit 4, when the base voltage of the transistor 22 becomes higher than the base voltage of the transistor 23, the transistor 2
2 is on, and transistor 23 is off. Therefore, no current is supplied to the clamp capacitor 7 from the comparison circuit 4 and the voltage-current conversion circuit 5. For this reason,
Due to the charge accumulated in the clamp capacitor 7, the input voltage of the inverting amplifier 8 is maintained. Therefore, the output of the inverting amplifier 8, that is, the negative phase input voltage of the differential amplifier 2 is also held.

In this way, the sync tip level in the synchronizing signal of the video signal supplied from the input terminal 1 is clamped to the voltage of the crank reference voltage source 3, and is taken out from the output terminal 9.

〔Effect of the invention〕

As explained above, according to the present invention, by making the beak clamp circuit a feedback type, the number of pins on which clamp capacitors are provided can be reduced to one pin, which is ideal for IC implementation.

Furthermore, since the differential amplifier, comparator circuit, and inverting amplifier are current outputs, the dynamic range is wide, making it ideal for applications that require low power supply voltage operation, such as a camera-integrated VTR.

Furthermore, by using a configuration in which the clamp capacitor is grounded, it is not affected by power supply voltage fluctuations, so the power supply smoothing capacitor can be made smaller.
It is possible to downsize a camera-integrated VTR and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a feedback type peak clamp circuit according to the present invention, FIG. 2 is a diagram showing an embodiment of a feedback type peak clamp circuit according to the present invention, and FIG. 3 is an example of a conventional clamp circuit. FIG. １・・・・・・・・・Input terminal, ３・・・・・・・・・
・・Basis voltage source, 7・・・・・・・・・Capacitor,
9. Old: Output terminal, 18: Transistor, 36: Self: Current source. Volume 10

Claims (1)

[Claims] 1. A differential amplifier comprising a first transistor and a second transistor to which an input signal is supplied, and a comparison circuit that compares the output signal of this differential amplifier with a first reference voltage. a capacitor that converts the output current of the comparator circuit into a voltage and holds it; and an inverting amplifier that inverts the voltage held by the capacitor, the output voltage of the inverting amplifier forming the differential amplifier. 1. A feedback type peak clamp circuit, characterized in that the feedback type peak clamp circuit is configured to supply a clamp output to a second transistor, and extract a clamp output from the output of the differential amplifier.