JPH03136353A - Removing device of semiconductor element - Google Patents
Removing device of semiconductor elementInfo
- Publication number
- JPH03136353A JPH03136353A JP27676689A JP27676689A JPH03136353A JP H03136353 A JPH03136353 A JP H03136353A JP 27676689 A JP27676689 A JP 27676689A JP 27676689 A JP27676689 A JP 27676689A JP H03136353 A JPH03136353 A JP H03136353A
- Authority
- JP
- Japan
- Prior art keywords
- tool
- chip
- substrate
- semiconductor element
- pushed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 229910000679 solder Inorganic materials 0.000 abstract description 17
- 230000002950 deficient Effects 0.000 abstract description 10
- 238000002844 melting Methods 0.000 abstract description 4
- 230000008018 melting Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、基板上に搭載されたＩＣチップ等の半導体素
子を取り外す装置に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an apparatus for removing a semiconductor element such as an IC chip mounted on a substrate.
〈従来の技術〉
以下、図面を参照して半導体素子の従来の取り外し装置
を説明する。第５図および第６図は、従来の半導体素子
の取り外し装置を説明するための図面であって、第５図
は平面図、第６図は正面図である。<Prior Art> Hereinafter, a conventional semiconductor device removal device will be described with reference to the drawings. FIGS. 5 and 6 are drawings for explaining a conventional semiconductor element removal apparatus, in which FIG. 5 is a plan view and FIG. 6 is a front view.
第５図および第６図に示すように、良品のＩＣチップ１
および不良のＩＣチップ２を搭載した基板４をヒータ８
上に載せて半田融点近くまで加熱する。次に、ＩＣチッ
プの取り外し装置のツール本体１１に取り付けたツール
レバー１３をツールピン１４を支点にして左（第６図上
で左）に回すと、ツールレバー１５がツールバネ１６の
弾力に抗して左に動き、ツールレバー１５の先端がＩＣ
チップ２を左方向に押すので、半田バンプ３が、基板配
線５の端部に設けられた基板電極６側で破断し、ＩＣチ
ップ２が基板４から外れる。このようにして、不良のＩ
Ｃチップ２を取り外していた。なお、７は基板ストッパ
ーである。As shown in FIGS. 5 and 6, a good IC chip 1
And the board 4 on which the defective IC chip 2 is mounted is heated to the heater 8.
Place it on top and heat it to near the melting point of the solder. Next, when the tool lever 13 attached to the tool body 11 of the IC chip removal device is turned to the left (left in FIG. 6) using the tool pin 14 as a fulcrum, the tool lever 15 resists the elasticity of the tool spring 16. the tip of the tool lever 15 to the left.
Since the chip 2 is pushed to the left, the solder bumps 3 are broken on the side of the board electrode 6 provided at the end of the board wiring 5, and the IC chip 2 is separated from the board 4. In this way, the defective I
C-chip 2 had been removed. Note that 7 is a substrate stopper.
〈発明が解決しようとする課題〉
しかしながら、従来の方法では、不良のＩＣチップ２の
側面に左右均等な外力を加えるのが難しく、また、ＩＣ
チップ２の左半分と右半分にある半田バンプ３の数が同
じでないことが多いので、第５図に２点鎖線で示すよう
に、片側だけ半田バンプ３が破断して取り外しが不十分
であったり、また、極端な場合には、ＩＣチップ２が隣
接する良品のＩＣチップ１に接触して良品のＩＣチップ
１の半田バンプ部分で接続不良を引き起こすことがある
。<Problems to be Solved by the Invention> However, in the conventional method, it is difficult to apply an external force equally on the left and right sides of the defective IC chip 2, and
Since the number of solder bumps 3 on the left and right halves of the chip 2 is often not the same, the solder bumps 3 on one side may be broken and removed insufficiently, as shown by the two-dot chain line in Figure 5. Or, in extreme cases, the IC chip 2 may come into contact with an adjacent good IC chip 1, causing a connection failure at the solder bump portion of the good IC chip 1.
本発明は上記事情に鑑みて創案されたものであって、不
良のＩＣチップ２等の半導体素子の一つの側面に左右均
等な外力を加えることができる半導体素子の取り外し装
置を提供することを目的としている。The present invention was devised in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor element removal device that can apply an external force equally on both sides to one side of a semiconductor element such as a defective IC chip 2. It is said that
く課題を解決するための手段〉
上記課題を解決するために本発明の半導体素子の取り外
し装置は、基板に搭載された半導体素子の一つの側面に
外力を与えて基板から半導体素子を取り外す装置におい
て、前記外力は、前記側面に一側面が対向するように基
板に搭載された三角柱状のツールを介して与えられ、且
つ、前記一側面は、基板と平行な任意の平面によるツー
ルの断面が形成する三角形の最長辺を含む一側面である
ようにしている。Means for Solving the Problems> In order to solve the above problems, the semiconductor element removal apparatus of the present invention is an apparatus for removing a semiconductor element from a substrate by applying an external force to one side of the semiconductor element mounted on the substrate. , the external force is applied via a triangular prism-shaped tool mounted on the substrate such that one side faces the side, and the one side has a cross section of the tool formed by an arbitrary plane parallel to the substrate. This is one side of the triangle that includes the longest side.
〈作用〉
外力はツールを介して半導体素子の前記した一つの側面
に与えられる。従って、半導体素子のこの側面に左右均
等な外力を与えるので、半導体素子は外力を加えられた
方向に移動して基板から取り外される。<Operation> External force is applied to the above-mentioned one side surface of the semiconductor element via the tool. Therefore, since an equal external force is applied to the side surfaces of the semiconductor element on both sides, the semiconductor element moves in the direction in which the external force is applied and is removed from the substrate.
〈実施例〉
以下、図面を参照して本発明の詳細な説明する。半導体
素子の従来の取り外し装置で説明したものと同等のもの
には、同一の符号を付して説明する。<Example> Hereinafter, the present invention will be described in detail with reference to the drawings. Components equivalent to those described in the conventional semiconductor device removal apparatus will be described with the same reference numerals.
まず、第１の実施例を説明する。第１図および第２図は
本発明の第１の実施例を説明するための図面であって、
第１図は平面図、第２図は正面図である。First, a first example will be described. 1 and 2 are drawings for explaining a first embodiment of the present invention,
FIG. 1 is a plan view, and FIG. 2 is a front view.
第１図に示すように、基板４上には、良品のＩＣチップ
１、不良のＩＣチップ２および別の良品のＩＣチップ１
が搭載されている。ＩＣチップ２は、第２図に示すよう
に、基板４上に形成された基板配線５の端部の基板電極
６に、ＩＣチップ２の半田バンプ３を介して接続されて
いる。ＩＣチップ１もＩＣチップ２と同様に半田バンプ
を介して基板電極に接続されている。７は基板４のスト
ッパである。As shown in FIG. 1, on the substrate 4 are a good IC chip 1, a bad IC chip 2, and another good IC chip 1.
is installed. As shown in FIG. 2, the IC chip 2 is connected to a substrate electrode 6 at the end of a substrate wiring 5 formed on a substrate 4 via solder bumps 3 of the IC chip 2. Like the IC chip 2, the IC chip 1 is also connected to the substrate electrode via solder bumps. 7 is a stopper for the substrate 4.
不良のＩＣチップ２を取り外す装置は、ツール本体１１
と、ツールピン１４を支点として回動自在にツール本体
１１に取り付けられたツールレバー１３と、ツール本体
１１に摺動自在に貫通して取り付けられており、ツール
レバー１３によって押されてＩＣチップ２の方向に移動
するツールバー１５と、ツールバー１５を元の位置に復
帰させるツールバネ１６を備えている。The device for removing the defective IC chip 2 is a tool body 11.
and a tool lever 13 that is rotatably attached to the tool body 11 with the tool pin 14 as a fulcrum, and a tool lever 13 that is attached to the tool body 11 so as to be able to slide through it. The tool bar 15 is provided with a tool bar 15 that moves in the direction of , and a tool spring 16 that returns the tool bar 15 to its original position.
９は三角柱状のツールであって、このツール９は、基板
４に平行な任意の平面がツール９と交叉して形成される
三角形（本実施例ではこの三角形が、第１図に示すよう
に２等辺三角形であるが、これにこだわるものではない
）の最長辺を含む面（以下一側面という） ９ａが、）
Ｃチップ２の例語の内、ＩＣＣチップ上隣り合はない一
つの側面２ａに対向するように基板４上に搭載される。Reference numeral 9 denotes a triangular prism-shaped tool, and this tool 9 has a triangular shape formed by intersecting an arbitrary plane parallel to the substrate 4 with the tool 9 (in this embodiment, this triangle is as shown in FIG. 1). The surface containing the longest side (hereinafter referred to as one side) of the isosceles triangle (but is not limited to this) is 9a)
In the example of the C chip 2, the ICC chip is mounted on the substrate 4 so as to face one side surface 2a which is not adjacent to the other.
従って、ツール９の前記三角形の最長辺以外の辺を含む
二つの側面同士の交線９ｂがツールバー１５の先端に対
向している。Therefore, the intersection line 9b between the two side surfaces of the tool 9 including sides other than the longest side of the triangle faces the tip of the tool bar 15.
基板４をヒータ８で半田の融点近くまで加熱する。次い
で、ツールレバー１３をツールビン１４を支点として左
（第２図上で左）に回すと、ツールバー１５は左方に押
され、ツールバー１５の先端はツール９の交線９ｂを押
すので、ツール９およびツール９に押されたＩＣチップ
２は、第１図の二点鎖線に示すように、左方へ移動する
。即ち、ツール９の一側面９ａがＩＣチップ２の側面２
ａに当接し、側面２ａに左右均等な力を加える。従って
、ＩＣチップ２は、良品のＩＣＣチップ上接触すること
なく押された方向に移動し、半田バンプ３が基板電極６
側で破断して基板４から取り外される。The substrate 4 is heated with a heater 8 to near the melting point of the solder. Next, when the tool lever 13 is turned to the left (left in FIG. 2) using the tool bin 14 as a fulcrum, the tool bar 15 is pushed to the left, and the tip of the tool bar 15 pushes the intersection line 9b of the tool 9, so the tool 9 and the IC chip 2 pushed by the tool 9 moves to the left as shown by the two-dot chain line in FIG. That is, one side 9a of the tool 9 is the side 2 of the IC chip 2.
a and applies equal force to the left and right side surfaces 2a. Therefore, the IC chip 2 moves in the direction in which it is pushed without making contact with the good ICC chip, and the solder bumps 3 move onto the substrate electrodes 6.
It is broken at the side and removed from the substrate 4.
なお、ツール９の材質を樹脂製（ポリイミド、シリコン
樹脂等）にすることにより、基板配線５および基板電極
６に傷をつけないようにしている。Note that the tool 9 is made of resin (polyimide, silicone resin, etc.) to prevent damage to the board wiring 5 and the board electrode 6.
次に、第２の実施例を説明する。第３図および第４図は
本発明の第２の実施例を説明するための図面であって、
第３図は平面図、第４図は正面図である。Next, a second example will be described. 3 and 4 are drawings for explaining a second embodiment of the present invention,
FIG. 3 is a plan view, and FIG. 4 is a front view.
第３図に示すように、基板４上には、良品のＩＣチップ
１１不良のＩＣチップ２および別の良品のＩＣチップ１
が搭載されている。ＩＣチップ２は、第４図に示すよう
に、基板４上に形成された基板配線５の端部の基板電極
６に、ＩＣチップ２の半田バンプ３を介して接続されて
いる。Ｉｃチップ１もＩＣチップ２と同様に半田バンプ
を介して基板電極に接続されている。As shown in FIG. 3, on the board 4 there are a good IC chip 11, a defective IC chip 2, and another good IC chip 1.
is installed. As shown in FIG. 4, the IC chip 2 is connected to a substrate electrode 6 at the end of a substrate wiring 5 formed on a substrate 4 via a solder bump 3 of the IC chip 2. Like the IC chip 2, the IC chip 1 is also connected to the substrate electrode via solder bumps.
不良のＩＣチップ２を取り外す装置は、ＩＣチップ２と
後述するツール１９とを把持するために両端で折曲され
て一端に折曲部２１ａ、他端に折曲部２１ｂを設けたほ
ぼコ字状のツール本体２１と、基板４の周縁部分に固定
されるほぼコ字状に形成されたツール２３と、ツール２
３とツール本体２１の折曲部２１ｂとを連結し、ツール
本体２１をツール２３の方向に付勢するバネ２２とを備
えている。The device for removing the defective IC chip 2 has a substantially U-shaped device that is bent at both ends and has a bent portion 21a at one end and a bent portion 21b at the other end in order to grip the IC chip 2 and a tool 19 to be described later. A tool main body 21 having a shape, a tool 23 formed in a substantially U-shape fixed to the peripheral edge of the substrate 4, and a tool 2
3 and the bent portion 21b of the tool body 21, and a spring 22 that biases the tool body 21 in the direction of the tool 23.
１９は、第１の実施例で説明したツール９と同様に形成
されたツールであって、このツール１９のツール９の一
側ｍ９ａに対応する一側面１９ａの両端近辺に突起１０
が設けられている点がツール９と異なっている。そして
、ツール１９は、一側面１９ａがＩＣチップ２の側面２
ａに対向するように、また、突起ｌＯが側面２ａに接触
するように基板４上に搭載される。１９ｂはツール９の
交線９ｂに対応する交線である。Reference numeral 19 denotes a tool formed similarly to the tool 9 described in the first embodiment, and the tool 19 has protrusions 10 near both ends of one side 19a corresponding to the one side m9a of the tool 9.
This differs from tool 9 in that it is provided with . One side 19a of the tool 19 is the side 2 of the IC chip 2.
It is mounted on the substrate 4 so as to face the side surface 2a and so that the protrusion 1O contacts the side surface 2a. 19b is an intersection line corresponding to the intersection line 9b of the tool 9.
基板４をヒータ８によって半田融点近くまで加熱する。The substrate 4 is heated by a heater 8 to near the solder melting point.
次いで、ツール２３を基板４の端部に固定し、ツール本
体２１をＩＣチップ２とツール１９との上に搭載し、Ｉ
Ｃチップ２とツ・−ル１９とを把持してツール本体２
１の折曲部２１ａをツール１９の交線９ｂに当接させる
。すると、バネ２２によってツール本体２１が左方（第
４図上で左方）に引っ張られ、ツール本体２１の折曲部
２１ａがツール１９の交線１９ｂを左方に押すので、ツ
ール１９の突起ｌＯがＩＣチップ２の側面２ａに左右均
等な力を加える。従って、ＩＣチップ２は、第３図の二
点鎖線で示すように、良品のＩＣチップｌに接触するこ
となく押された方向に移動し、半田バンプ３が基板電極
６側で破断して基板４から取り外される。Next, the tool 23 is fixed to the end of the substrate 4, the tool body 21 is mounted on the IC chip 2 and the tool 19, and the I
Grip the C tip 2 and the tool 19 and remove the tool body 2.
The bent portion 21a of the tool 19 is brought into contact with the intersection line 9b of the tool 19. Then, the tool body 21 is pulled to the left by the spring 22 (to the left in FIG. 4), and the bent portion 21a of the tool body 21 pushes the intersection line 19b of the tool 19 to the left, so that the protrusion of the tool 19 IO applies equal force to the side surfaces 2a of the IC chip 2 on the left and right sides. Therefore, as shown by the two-dot chain line in FIG. 3, the IC chip 2 moves in the pushed direction without contacting the good IC chip 1, and the solder bumps 3 break on the substrate electrode 6 side, causing the substrate removed from 4.
なお、第１の実施例と同様に、ツール１９の材質を樹脂
製（ポリイミド、シリコン樹脂等）にすることにより、
基板配線５および基板電極６に傷をつけないようにしで
いる。Note that, similarly to the first embodiment, by making the material of the tool 19 resin (polyimide, silicone resin, etc.),
The board wiring 5 and the board electrode 6 are prevented from being damaged.
〈発明の効果〉
以上説明したよう６．に本発明の半導体津子の取り外し
装置は、基板に搭載された半導体素子の一つの側面に外
力を与えて基板から半導体素子を取り外す装置において
、前記、外力は、前記側面に一側面が対向するように基
板・に搭載された三角柱状のツールを介して与えられ、
且つ、前記一側面は、基板と平行な任意の平面・による
ツールの断面が形成する三角形の最長辺を含む二側面で
ある。<Effects of the invention> As explained above, 6. The semiconductor element removal device of the present invention is an apparatus for removing a semiconductor element from a substrate by applying an external force to one side surface of a semiconductor element mounted on a substrate, in which the external force is applied with one side facing the side surface. It is given through a triangular prism-shaped tool mounted on the board,
Further, the one side surface is two side surfaces including the longest side of a triangle formed by a cross section of the tool taken by an arbitrary plane parallel to the substrate.
従って、本発明の半導体素子の取り外し装置は、不良の
ＩＣチップ等の半導体素子の一つの側面に左右均等な外
力を与えることができるので、半導体素子は外力を与え
た方向に移動して基板から取り外される。故に、半導体
素子の片側だけ半田バンプ等が破断して取り外しが不十
分であったり、或いは、不良の半導体素子が隣り合う良
品の半導体素子に接触して良品の半導体素子の半田バン
プ部分等で接続不良を引き起こすことがない。Therefore, the semiconductor element removal device of the present invention can apply an external force equally on both sides of a semiconductor element such as a defective IC chip, so that the semiconductor element moves in the direction in which the external force is applied and is removed from the substrate. removed. Therefore, the solder bumps, etc. on one side of the semiconductor element may be broken and removal may not be sufficient, or the defective semiconductor element may come into contact with an adjacent good semiconductor element and be connected by the solder bumps, etc. of the good semiconductor element. Does not cause defects.
゛ 第、１図および第２図は本発明の第１の実施例を乎
明するためめ図面であ・て・第１図は平面図・第２図は
正面図である。第３図および第４図は本発明の第２の実
施例を説明するための図面であって、第３図は平面図、
第４図は正面図である。第５図および第６図は、半導体
素子の従来の取り外し装置を説明するための図面であっ
て、第５図は平面図、第６図は正面図である。
２ ・・・半導体素子、２ａ・・・側面、４ ・・・基
板、９．１９ ・・・ツール、９ａ、 １９ａ ・・
・一側面。1, and 2 are drawings for explaining the first embodiment of the present invention; FIG. 1 is a plan view, and FIG. 2 is a front view. 3 and 4 are drawings for explaining the second embodiment of the present invention, in which FIG. 3 is a plan view,
FIG. 4 is a front view. 5 and 6 are drawings for explaining a conventional device for removing semiconductor elements, with FIG. 5 being a plan view and FIG. 6 being a front view. 2...Semiconductor element, 2a...Side surface, 4...Substrate, 9.19...Tool, 9a, 19a...
・One aspect.
Claims (1)
を与えて基板から半導体素子を取り外す装置において、
前記外力は、前記側面に一側面が対向するように基板に
搭載された三角柱状のツールを介して与えられ、且つ、
前記一側面は、基板と平行な任意の平面によるツールの
断面が形成する三角形の最長辺を含む一側面であること
を特徴とする半導体素子の取り外し装置。(1) In a device for removing a semiconductor element from a substrate by applying an external force to one side of the semiconductor element mounted on the substrate,
The external force is applied via a triangular prism-shaped tool mounted on the substrate so that one side faces the side, and
A device for removing a semiconductor device, wherein the one side surface includes the longest side of a triangle formed by a cross section of the tool taken along an arbitrary plane parallel to the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27676689A JPH03136353A (en) | 1989-10-23 | 1989-10-23 | Removing device of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27676689A JPH03136353A (en) | 1989-10-23 | 1989-10-23 | Removing device of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03136353A true JPH03136353A (en) | 1991-06-11 |
Family
ID=17574059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27676689A Pending JPH03136353A (en) | 1989-10-23 | 1989-10-23 | Removing device of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03136353A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160061557A (en) * | 2014-11-21 | 2016-06-01 | 대한민국(국립재활원장) | System and method for assisting ambulatory rehabilitation using projected image |
| JP2016119336A (en) * | 2014-12-18 | 2016-06-30 | 富士通株式会社 | Semiconductor component separation method |
-
1989
- 1989-10-23 JP JP27676689A patent/JPH03136353A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160061557A (en) * | 2014-11-21 | 2016-06-01 | 대한민국(국립재활원장) | System and method for assisting ambulatory rehabilitation using projected image |
| JP2016119336A (en) * | 2014-12-18 | 2016-06-30 | 富士通株式会社 | Semiconductor component separation method |
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