JPH03133272A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To reproduce an excellent video image without deterioration in a synchronizing signal by providing an inhibit signal output means outputting an inhibit signal relating to a synchronizing signal of a video signal and an inhibit inhibit solarization to inhibit the solarization in the synchronizing signal portion. CONSTITUTION:When a synchronizing signal is inputted from a synchronizing separator circuit 22, a timing signal being a low level during the synchronizing signal period is outputted from a timing adjustment circuit 20. Thus, an output of OR gates 188-181, that is, a data of output terminals 166-161 depends on a low level or high level of input terminals 148-141. Thus, the operation of the solarization circuit 12 is substantially inhibited during the synchronizing signal period and the 8-bit quantization video signal data inputted from input terminals 14128-141 is outputted as it is to the 8-bit output terminals 16128-161. Thus, the deterioration in the synchronizing signal is not caused even the synchronizing signal portion.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a video signal processing circuit, and in particular, quantizes the video signal from the sync tip level to the white level using N bits, and converts the quantized data into upper M (M Solarization to <N) bits.

n) relates to a video signal processing circuit.

[Prior art]

For example, a circuit that applies special effects using digital signal processing, such as solarizing video signal data quantized at 8 bits (256 gradations) to 4 bits (16 gradations), is used in digital TVs, for example. Or it is attached to a VTR, etc.

An example of such a solarization circuit is, for example:
It is disclosed in Japanese Unexamined Patent Publication No. 61-283281. Conventionally, the signal to be solarized has been a pedestal clamped video signal, as shown in FIG. Therefore, no consideration was required for the synchronization signal of the video signal.

[Problem to be solved by the invention]

However, IDT V (Improved
Definition TV), etc., the clamp level is the sync tip level, so special effects like this (
When solarization is applied, there is a problem in that the synchronization signal deteriorates or disappears.

FIG. 3 shows an example in which solarization is simply applied to a signal clamped at the sync tip level. The example in Figure 3 is 8 bits (256 gradations).
This is an example in which a quantized video signal is solarized to 2 bits (4 gradations). At this time, the relationship between the 256-gradation video signal and the slice level for reducing the gradation to 4 gradations is shown in FIG. 3(A). As can be seen from FIG. 3(A), if the pedestal level of the video signal is higher than the slice level, the pedestal level will no longer exist in the signal after solarizing, and conversely, If it is low, the width of the horizontal synchronization pulse (or vertical synchronization pulse) will increase. Furthermore, if the pedestal level and the slice level are even higher, as shown in FIG. 3(B), the horizontal or vertical synchronizing signal portion will be greatly degraded by the noise superimposed on the pedestal level. In FIG. 3(B), the portion marked with an x is a portion where the waveform resulting from the solarization is affected by noise, and the waveform cannot be predicted.

In this way, if solarization is simply applied to a signal clamped at the sync tip level, the synchronization signal will deteriorate or disappear.

Therefore, the main object of the present invention is to provide a video signal processing circuit that does not cause deterioration of the synchronization signal even when a video signal clamped at the sync chip level is quantized and the quantized data is solarized. .

[Means to solve the problem]

Simply put, the present invention is directed to a video signal processing circuit that quantizes a video signal from the sync tip level to the white level using N bits, and solarizes the quantized data of the N bits into upper M (M<N) bits. , a video signal processing device comprising: prohibition signal output means for outputting a prohibition signal in relation to a synchronization signal of a video signal; and a prohibition circuit for prohibiting solarization in response to the prohibition signal from the prohibition signal output means. It is a circuit.

[Effect]

The prohibition signal output means outputs a prohibition signal that is at a low level or a high level at least during a period of the synchronization signal, based on a horizontal synchronization signal or a vertical synchronization signal obtained from the video signal by the synchronization separation circuit, for example. The prohibition circuit responds to the prohibition signal by, for example, outputting the quantized data as is during the duration of the prohibition signal.
Prohibit solarization.

〔Effect of the invention〕

According to this invention, solarization is prohibited in the synchronization signal portion, so even if a video signal clamped at the sync chip level is quantized and solarized, a good signal with no deterioration of the synchronization signal (horizontal and vertical) can be obtained. Images can be reproduced.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

〔Example〕

Referring to FIG. 1, a video signal processing circuit 10 of this embodiment
is a solarization circuit 12 that receives 8-bit video signal data quantized by a quantization circuit (not shown).
including. This solarization circuit 12 has 8-bit input terminals 14128°1464, L4 . z, 14th,
1411, 144, 142 and 14. and 8-bit output terminals 16+ga, 16ba, 163g, 16
1&, 16a, 16416□ and 16. and has input terminals 148°144.141 and 14. and output terminal 168°16=, 16g and 16. Between them are ORGATE 1B, 1B, 18□ and 181, respectively.
is inserted. These OR gates 18a to 18 act as inhibiting means, and one input of each receives a signal from the corresponding input terminal 14a, 14a, 14□, and 14+, and the other input receives a timing signal from the timing adjustment circuit 20. A signal is output.

This timing signal adjustment circuit 20 receives a horizontal synchronization signal and a horizontal synchronization signal from a synchronization separation circuit 22 that receives a video signal, and during the period of the synchronization signal (horizontal and vertical),
For example, it outputs a timing signal that becomes low level (this acts as a prohibition signal).

The embodiment shown in FIG. 1 is an example in which the lower 4 bits of 8 bits (256 gradations) are omitted and the gradation is converted to 4 bits (16 gradations).

That is, during the video signal period, the timing signal from the timing adjustment circuit 20 is at a high level, so the output terminals 16s, 164.162, and 16+ have the following signals.
Input terminals 148, 144°14□ and 14. Regardless of whether it is a low level or a high level, all outputs are high level (“1”). Therefore, input terminal 1
4. .

The quantized video signal data inputted from the terminals 14+ to 16. It is output as 4-bit video signal data from za to 1616.

When the synchronization signal (horizontal and vertical) is input from the synchronization separation circuit 22, the timing adjustment circuit 20 outputs a timing signal that is at a low level during the period of the synchronization signal. Therefore, ORGATE 188-18. The output of , that is, the data of output terminals 168 to 161
It depends on the low level or high level of 8 to 141.

Therefore, during the synchronization signal period, the operation of the solarization circuit 12 is substantially prohibited, and the input terminals 14,
. ~14. The 8-bit quantized video signal data input from the 8-bit output terminals 161□ to 16. is output to. Therefore, according to this embodiment, the deterioration of the synchronization signal as shown in FIG. 3 does not occur even in the synchronization signal portion.

In the embodiment described above, OR gates 188 to 181 are used to prohibit solarization during the synchronization signal period. However, it will be readily understood that such inhibiting means can be appropriately designed using other types of gates and elements.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a waveform diagram showing an example of solarizing a pedestal clamped video signal. FIG. 3 is an illustrative diagram showing the case of solarizing a video signal clamped at the sync chip level.
FIG. 3(A) shows the relationship between quantized video signal data and the slice level of solarization, and FIG. 3(B) shows how the synchronization signal is degraded by noise. In the figure, 10 is a video signal processing circuit, 12 is a solarization circuit, ILza~14+ is an input terminal, 16.
21-16. 188 to 16 are OR gates, 20 is a timing adjustment circuit, and 22 is a synchronous separation circuit. Figure 1

Claims (1)

[Claims] Quantize the video signal from the sync tip level to the white level using N bits, and use the quantized data of the N bits as the upper M
In a video signal processing circuit that solarizes to (M<N) bits, a prohibition signal output means for outputting a prohibition signal in relation to a synchronization signal of the video signal, and in response to the prohibition signal from the prohibition signal output means. A video signal processing circuit comprising a prohibition circuit that prohibits the solarization.