JPH03132267A - Timing signal generating circuit - Google Patents

Abstract

PURPOSE:To prevent occurrence of malfunction by providing a decode circuit outputting a gate signal corresponding to synchronizing signal based on an output of a counter and a 1st gate circuit using a gate signal generated by the decode circuit and masking a reset signal. CONSTITUTION:Mask processing is applied to a reset signal of one clock width and 1/2 line width outputted respectively from pulse generators 10, 14 based on a horizontal synchronizing signal and a vertical synchronizing signal by using a gate signal generated by horizontal and vertical decoders 20, 28. Thus, erroneous reset by counters 114, 126 due to the effect by noise is prevented in an excellent way. Since the processing content is revised depending on the presence of a signal in the gate processing by a vertical synchronizing signal detecting signal by a D flip-flop 30, noise prevention is entered and the system is effective especially at power application.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to ghost cancellers, digital televisions,
It is used in video equipment such as image processing devices, and is particularly used to accurately define the scanning position of pixels on the screen from the input composite video signal, extract any specific signal on the screen, etc. The present invention relates to a timing signal generation circuit that defines a desired timing of a timing signal.

[Prior art 1] As a conventional timing signal generation circuit, for example, the 11th
14, and 16, respectively. Among these, the one shown in Fig. 11 detects pixel addresses in both horizontal and vertical directions, the one shown in Fig. 14 performs field detection, and the one shown in Fig. 16 detects line extraction timing. It is something to detect.

<First Conventional Example> First, the first conventional example will be described with reference to FIGS. 11 to 13. 5 in FIG. 11. In FIG. 11, the input composite video signal is input to horizontal synchronization separation circuit 100. Vertical synchronization separation circuit 102. The signals are respectively input to the clock generation circuit 104. A horizontal synchronization separation circuit 100 separates a horizontal synchronization signal from an input composite video signal, a vertical synchronization separation circuit 102 separates a vertical synchronization signal, and a clock generation circuit 104 generates a reference clock signal. This reference clock is, for example, a 4fsc (fsc) locked to a burst signal of a composite video signal.
is the color subcarrier frequency, 4fsc=14.32 MHz). Here, it is assumed that the synchronization signals output from the horizontal synchronization separation circuit 100 and the vertical synchronization separation circuit 102 are both of negative polarity.

The horizontal synchronization signal output from the horizontal synchronization separation circuit 100 is applied to the D-flip-flop 108 of the pulse generator 106. A reference clock is input from the clock generation circuit 104 to the clock input side of the D-flip-flop 108 . This D-flip-flop 10B
The inverted output of is given to the D-flip-flop 110.

A reference clock is similarly input from the clock generation circuit 104 to the clock input side of the D-flip-flop 110. This D-flip-flop 108.11
Each inverted output of 0 is provided to a NAND gate 112, respectively.

The above components constitute the pulse generator 106, and its operation timing is as shown in the time chart of FIG. 12. The same figure (the reference clock next to the leading edge or falling edge of the horizontal synchronization signal of Al (the same figure (B))
The inverted output of the D-flip-flop 108 becomes the logical value "H" at the rising timing of the signal (see figure I).
Therefore, the inverted output of the D-flip-flop 110 becomes the logical value "L" at the timing of the next rising edge of the reference clock (see the figure (see Dl),
The output of the AND gate 112 becomes a negative polarity pulse of one clock width from the rising edge of the next reference clock of the front line of the horizontal synchronization signal, as shown in FIG.

- This pulse is given to the synchronous counter 114 as a reset pulse of negative polarity. This counter 114 is given the above-mentioned reference clock as a clock input, and counts every l clock, and when a reset pulse is input, the count value is reset to "0" by the next clock input. .

The counted value is output as an appropriate number of bits as a pixel address in the horizontal direction of the screen.1For example, if the reference clock frequency is 4fsc, the l line will have 910 clocks, so 10 bits will be used to address the horizontal pixel. Address output is performed.

Next, the horizontal pixel address is input to the decoder 116, and based on this, a 1/2 line period pulse as shown in FIG. 13 is generated. This decoder 1
16 is composed of, for example, one ROM, and by storing the logical value of the decoded output in advance in the ROM according to the count value of the counter 114, a 1/2 line period pulse can be generated.

Note that at this time, there is a slight time delay (several to several tens of ns) for the count value from the rise of the reference clock until the value is determined, and glitches may occur in the ROM output during this time. Therefore, should one stage of latch circuit be placed after the RQM?

It is preferable to use a ROM with a latch, and a reference clock is used as the latch clock.

In that case, the output of the latch circuit will be delayed by one clock with respect to the address given to the ROM, so it is necessary to take this into consideration when selecting data to be stored in the ROM.

Next, the 1/2 line period pulses output from the decoder 116 are input to the pulse generator 118 together with the vertical synchronization signal output from the vertical synchronization separation circuit 102.

This pulse generator 118 is similar to the pulse generator 10 described above.
Exactly the same configuration as 6, D-flip-flop 120
, 122, and NAND gate 124 correspond to D-flip-flop 108, 110, and NAND gate 112, respectively. Also, the vertical synchronization signal corresponds to the horizontal synchronization signal, and 1/
The two-line periodic pulse corresponds to the reference clock.

The operation of the pulse generator 118 regarding this vertical synchronization is as shown in parentheses in FIG.

The pulse output from this pulse generator 118 is given to the synchronous counter 126 as a negative reset pulse. A 1/2 line period pulse is applied to this counter 126 as a clock input, and counting is performed at every rising edge of the pulse, that is, every 1/2 line. When a reset pulse is input, the count value is reset to "0" after the first rise, that is, after 1/2 lines. The counted value is 0, which is output as a vertical pixel address with an appropriate number of bits.
For example, when l vertical synchronization is 525X (1/2 line).

A count value is output using the IO bit.

As described above, the counter 114 outputs a pixel address in the horizontal direction, and the counter 126 outputs a pixel address in the vertical direction. This allows the current pixel position of the signal within one screen to be known, and by decoding this, for example, it is possible to obtain the timing to perform desired processing at any position on the screen.

Second Conventional Example> Next, a second conventional example will be described with reference to FIGS. 14 and 15. Note that the same reference numerals are used for the same components as in the first conventional example described above, and the same applies to the conventional examples below C.)

In FIG. 14, the 1/2 line period pulse of the decoder 116 described above is input to the D-flip-flop 200. A vertical synchronizing signal is input as a clock to this D-flib flop 200, and the input is latched at the timing thereof.

The vertical sync signal is the same as the horizontal sync signal.

Each field is shifted by 1/2 line. Therefore, fields can be detected by latching pulses that are inverted every 1/2 line with the vertical synchronization signal. This situation is shown in the time chart of FIG.

In the case of odd fields, (A) and (B) in the same figure
.

As shown in (C), the pulse of the vertical synchronizing signal and the line change coincide with each other. Therefore, in the vertical synchronization separation circuit 102, a 1/2 line period pulse is sent to the D-flip-flop at the rising edge of the vertical synchronization signal that is delayed (less than 1/2 line) with respect to the input composite video signal, that is, at the end tl of the synchronization signal. When latched at 200, a logical value of "H" is output.

On the other hand, in the case of an even field, the line transition is shifted by l/2 lines compared to the case of an odd field, so similarly, at tl, the D-flip-flop 2
When latched by 00, the logical value rLJ will be output. As a result, a field discrimination signal of the input composite video signal is obtained.

<Third Conventional Example> Next, a third conventional example will be described with reference to FIGS. 16 and 17. It is assumed that the horizontal synchronization signal separated from the input composite video signal by the horizontal synchronization separation circuit 300 in this example has positive polarity.

A horizontal synchronization signal is applied to the pulse generator 118 as a clock. FIG. 17 shows such a pulse generator 11
A time chart of the operation of B is shown. In the same figure, (
A) to (0) are the first field of the NTSC signal,
(E) to (Hl are for the second field. As shown in this figure, the pulse generator 118 generates the rising edge (falling edge) of the horizontal synchronizing signal following the leading edge (falling edge) of the vertical synchronizing signal.
A negative polarity pulse of one horizontal opening signal width, that is, one line width, is generated and output as a reset pulse from the beginning of the line.

In the same figure, the vertical synchronization signal includes a vertical synchronization separation circuit 1
There is a delay due to 02. For the first field,
A reset pulse appears on the fifth line. However, in the case of the second field, since the vertical synchronizing signal is shifted by 1/2 line with respect to the first field, when a reset pulse is generated in the same way as in the first field, it appears on the fourth line.

These pulses are applied to the synchronous counter 126 as negative reset pulses. This counter 126
A horizontal synchronization signal is provided as a clock input. Counting is performed every l line, and when a reset pulse is input, the count value is reset to "0" on the next horizontal synchronizing signal input line (first line).

On the other hand, a horizontal synchronization signal is input to the monostable multi-by-break 302. Monostable multivi break 30
The time constant of 2 is set to, for example, about 32 uS, and a pulse that is inverted every about every 172 lines is generated with respect to the manually inputted horizontal synchronization signal. This pulse is input to the D-flip-flop 200, and is latched by the vertical synchronization signal input from the vertical synchronization separation circuit 102.

As mentioned above, the vertical synchronization signal is shifted by 1/2 line for each field with respect to the horizontal synchronization signal, so the D-flip-flop latches the pulse that is inverted every 1/2 line in the vertical synchronization signal. In particular, fields can be detected (see FIG. 15).

Next, the count value of the counter 126 is calculated by the comparator 30.
It is input to the B input side of 4. A of this comparator 304
A preset sampling line number is input to the input side, and this is compared with the count value. Here, to explain the set of sampling line numbers, as shown in Fig. 17, in the first field, 6
The counter 126 is reset at the line, and the count value becomes "0". Therefore, the subtraction value of "line number to be extracted - 7" can be set as the A input of the comparator 304. In the comparator 304, When the set sampling line number and count value match, that is, A=B
When this occurs, the logic value "H" (in case of positive logic) is output as a sampling line detection signal.

On the other hand, in the case of the second field, as shown in FIG. 17, the counter 126° is reset on the fifth line and the count value becomes rQJ. That is, the sampling line detection signal is l compared to the case of the first field.
Appears in front of the line.

Then, the output of comparator 304 is output to selector 3 on the one hand.
On the other hand, it is input to the B side of the selector 306 via the D-flip-flop 308. The D-flip-flop 308 outputs the input signal with a delay of 1942 minutes using the horizontal synchronizing signal as a clock. A field detection signal from the D-flip-flop 200 is input to a select input of the selector 306 . As a result, in the selector 306, the field detection signal is set to the logical value rHJ.
When the first field is such that the A-side signal is output, and when the second field is where the field detection signal has a logical value of "L", the B-side signal is output.

As described above, in the case of the second field, the sampling line detection signal appears one line earlier than in the case of the first field. This time difference is.

Adjustment is made by the D-flip-flop 308, and as a result, even if the outputs of the selector 306 are fields, the extraction line detection signal is output to the same line.

Next, the sampling line detection signal output from the selector 306 is input to the D-flip-flop 310, and
It is latched at the timing of the horizontal synchronization signal. This prevents glitches from occurring when the selector 306 and counter 126 are switched.

Next, the sampling line detection signal output from the D-flip-flop 310 is transmitted to the monostable multivibrator 31.
Here, a line extraction pulse of a predetermined length, for example, 63.5 μs for 1 line, is generated and output.

[Problems to be Solved by the Invention] However, the above conventional techniques have the following disadvantages. First, in the first conventional example, the horizontal and vertical counters 114 and 126 are reset at the timing of the horizontal and vertical synchronization signals separated from the composite video signal, and the reference clock and 1/2 line period pulse are , only determines the width of the reset pulse. That is, horizontal and vertical synchronization signals separated from the composite video signal are input to pulse generators 106 and 118, respectively, and the reset signals generated there are directly applied to the reset inputs of counters 114 and 126.

Therefore, due to the influence of noise, etc., a pulse at a position different from the original synchronization signal may be generated at the D-flip-flop 108.120.
Even if only a small amount is given to counter 114.
126 will be reset unconditionally, resulting in the inconvenience that a normal pixel address cannot be obtained.

Next, in the second conventional example, when a noise pulse is applied to the D-flip-flop 108, etc., the counter 1
14 is reset unconditionally, making it impossible to perform normal field discrimination.

Furthermore, in the third conventional example, in addition to the reset due to noise on the counter 126 and the influence of noise on the field discrimination in the D-flip-flop 200, the same influence of noise is also considered in the monostable multivibrator 302, 312, etc. .

The present invention has been made in view of these points, and an object thereof is to provide a timing signal generation circuit that can satisfactorily reduce the occurrence of malfunctions.

[Means for Solving the Problems] One of the aspects of the present invention is that resetting a counter that counts a predetermined clock signal and outputs a timing signal,
In a timing signal generation circuit that is operated by a reset signal generated based on a synchronization signal separated from an input composite video signal, a decoding circuit outputs a gate signal corresponding to the synchronization signal based on the output of the counter; The present invention is characterized by comprising a first gate circuit that masks the reset signal using the gate signal generated thereby.

A second invention provides a timing signal generation circuit in which a counter that counts a predetermined clock signal and outputs a timing signal is reset by a reset signal generated based on a synchronization signal separated from an input composite video signal. a decoding circuit that outputs a forced reset signal corresponding to the contents of the count value based on the output of the counter; and a decoding circuit that outputs a forced reset signal generated by the decoding circuit to the counter regardless of the presence or absence of the reset signal. the second for applying
The present invention is characterized by comprising a gate circuit.

A third aspect of the invention is the timing signal generation circuit according to claim 1, further comprising: a signal detection circuit for detecting the presence or absence of the synchronization signal;
The present invention is characterized in that it includes a third gate circuit that stops masking by the gate circuit.

According to one of the main aspects, a decoding circuit outputs a field detection signal corresponding to the synchronization signal based on the output of the counter, and the field detection signal generated by the decoding circuit is used to perform field detection. and a counting circuit that uses the output of the field detection circuit to count the desired sequence.

According to still another aspect, a decoding circuit that outputs a field detection signal corresponding to the synchronization signal based on the output of the counter, and a field detection circuit that performs field detection using the field detection signal generated thereby. with detection circuit.

A line detection circuit that uses the output of the field detection circuit to generate a sampling line detection signal indicating a desired sampling line, and a line sampling pulse of a desired length using the sampling line detection signal of this line detection circuit. A pulse output circuit is provided.

[Operation 1] According to the present invention, the counter is reset by masking the reset signal generated based on the synchronization signal with the gate signal generated in response to the synchronization signal. Further, the counter is forcibly reset by a forced reset signal depending on the contents of the count value.

Further, when the synchronization signal is not present, the counter is reset over a wide range without masking, thereby stabilizing the operation. After stabilization, the state shifts to a state where malfunctions are prevented by masking.

According to the main aspect, field detection is performed using good counting results of the counter operating as described above, and counting of a desired field sequence is also performed. According to yet another aspect, sampling line detection is performed and a line sampling pulse of a desired width is also generated.

(Example J) Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. Note that the same reference numerals are used for the same components as those of the conventional device described above.

<First Embodiment> First, a first embodiment of the present invention will be described with reference to FIGS. 1 to 5.

a. Configuration of the first embodiment Next, the configuration of the first embodiment will be explained with reference to FIG. In the figure, a horizontal pulse generator 1
0, the inverting outputs of the D-flip-flops 108, 110 are each connected to the input of the NAND gate 12. Further, in the vertical pulse generator 14, the inverted output sides of the D-flip-flops 120 and 122 are respectively connected to the input side of the NAND gate 16.

+ The output side of the NAND gate 12 is the AND gate 18
is connected to one input side of the AND gate 1.
8 or the set side of the counter 114. Further, on the output side of the counter 114, a decoder 2
0 is connected. The horizontal forced reset signal output side of this decoder 20 is connected to the other input side of the AND gate 18, and the horizontal horizontal synchronization gate signal output side is connected to one input side of the AND gate 22. The output side of this AND gate 22 is OR
It is connected to one input side of gate 24. Furthermore, O
The output side of the R gate 24 is connected to the remaining input side of the NAND gate 12.

On the other hand, the output side of the NAND gate 16 is connected to the AND gate 2.
6, and the output side of this AND gate 26 or the reset side of the counter 126. Further, a decoder 28 is connected to the output side of the counter 126. The vertical forced reset signal output side of this decoder 28 is connected to the other input side of the AND gate 26, and the vertical synchronization gate signal output side is connected to the remaining input side of the NAND gate 16. . Furthermore, the vertical horizontal synchronization gate signal output side of the decoder 28 is connected to the other input side of the AND gate 22.

The output side of the AND gate 26 is then connected to the clock side of the D-flip-flop 30. The output side of the vertical synchronization separation circuit 102 is connected to the input side of the D-flip-flop 30, the non-inverting output side is connected to the other input side of the OR gate 24, and the vertical A synchronization signal detection signal is output.

Next, among the above parts, the AND gate 22 receives horizontal synchronization gate signals in each of the horizontal and vertical directions from the decoder 20 .
28, respectively. These gate signals are shown in FIG. This figure corresponds to a television screen, with horizontal lines representing the horizontal direction and vertical lines representing the vertical direction.

The horizontal synchronization gate signal in the horizontal direction (see (B) in the same figure) is
It is a signal (positive logic) that selects only the periphery of the horizontal synchronization signal (same figure + AI !) of each horizontal line, and the horizontal horizontal synchronization gate signal (same figure (CI !)) in the vertical direction selects only the area around it. This is a signal to select only the lines of (
positive logic).

When the AND gate 22 performs a logical product of both, in a steady state, a signal is obtained that selects only the leading edge (falling edge) of the horizontal synchronizing signal of a specific line (see the shaded area in the same figure).
.

Next, a vertical synchronization signal detection signal is applied from a D-flip-flop 30 to an OR gate 24 to which the outputs of one or more AND gates 22 are input. In the D-flip-flop 30, as shown in FIG. 3, the input vertical synchronization signal is latched by the vertical reset signal input to the counter 126.

During normal operation, as shown in (B) in the same figure, the vertical synchronization signal is at the logic "L" level at the rising timing of the vertical reset signal, so the vertical synchronization signal detection signal, which is the latch output, is "L". However, if it is not normal, as shown in (C1, (Dl) in the same figure, the vertical synchronization signal is at the rHJ level of the logic value at the rising timing of the vertical reset signal, so the vertical The synchronization signal detection signal is rHJ, therefore,
The output of the OR gate 24 is the output of the AND gate 2 during normal operation.
The output of 2 is output as is, and when it is not normal, the logical value rHJ is always output.

Next, the new input of the NAND gate 12 includes this OR
The output of gate 24 is applied. Therefore, only when the output of the OR gate 24 is a logical value rHJ, the output pulse of the pulse generator IO, that is, the reset signal with a width of one clock from the front part of the horizontal synchronization signal is N
It is output from the AND gate 12.

Next, the AND gate 18 performs an AND operation on the output of the NAND gate 12 and the horizontal forced reset signal output from the horizontal decoder 20. This horizontal forced reset signal (negative logic) matches the reset signal output from the NAND gate 12 during normal operation. Also, when the decoder 20 is given an address that should not originally exist from the counter 114 (910 or more in the 4fsc),
A reset signal is output from the decoder 20. The output pulse of the AND gate 18 is applied to the counter 114 as a negative reset pulse.

Next, the decoder 20 generates and outputs a 1/2 line period pulse, a horizontal synchronization gate signal, and a horizontal forced reset signal, respectively, based on the horizontal address. This decoder 20, as mentioned above,
For example, it is composed of one ROM, and its pulse generation timing is set, for example, as shown in FIG. ), (C1, as shown in (D), horizontal forced reset signal, horizontal horizontal synchronization gate signal.

RO so that 1/2 line period pulses are output respectively.
Data storage for M is being performed.

Next, a vertical synchronization gate signal is newly inputted from the decoder 28 to the NAND gate 16 of the pulse generator 14, which is similar to the first conventional example described above. Further, a vertical forced reset signal (negative logic) is inputted to the AND get 26 from the decoder 28 . The generation timings of the output signals of these decoders 28 are set as shown in FIG. 5 (Al-(C1). That is, depending on the input count value shown in FIG. As shown in (C), data is stored in the ROM so that a vertical forced reset signal and a vertical synchronization gate signal are respectively output.

Among these, the vertical forced reset signal is
6 to the decoder 28 when a count value that should not exist (for example, 525 or more) is given, and is not output when the counter 126 is reset normally. In addition to the normal operation timing, the vertical synchronization gate signal is a signal that becomes the logical value rHJ at an appropriate position, and a gate is placed at that position.1 In the example shown, the last digit of the count value A gate is applied when the value is "4".

These signals are respectively input to gates 16.26. Therefore, during normal operation, the reset signal output from the pulse generator 14 and the vertical synchronization gate signal match, and the counter 126 is reset at that timing. However, if the timings of these signals deviate, the counter 126 is activated at the timing when the gate placed on the vertical synchronization gate signal and the output reset signal of the pulse generator 14 match, or at the timing of the vertical forced reset signal. A reset will be performed.

In this way, the locking of the counter reset with respect to the vertical synchronization signal is performed by the vertical synchronization gate signal rather than the vertical forced reset signal, and the locking of the counter reset by the vertical forced reset signal is performed from a transient state such as when the power is turned on. This is done when transitioning to a steady state.

In this respect, it is somewhat different from the horizontal counter reset operation. This is because the horizontal synchronization gate signal can be set relatively wide compared to the horizontal synchronization signal, whereas the vertical synchronization gate signal can only be set in line units.Therefore, when trying to lock the vertical forced reset signal to the vertical synchronization signal Then, the vertical sync gate signal cannot catch the vertical sync signal,
This is because there is a risk that the reset may be repeated using only the vertical forced reset signal.

b. Operation of the first embodiment Next, the operation of the first embodiment configured as above will be explained. First, the horizontal direction will be explained. The one-clock width reset signal output from the pulse generator IO is gated or masked by an AND gate 22 and an OR gate 24, respectively. In the AND gate 22, a mask is applied by a horizontal synchronization gate signal in the horizontal direction and a horizontal synchronization gate signal in the vertical direction (see FIG. 2).

Next, for the reset signal that has passed through the above gates, O
A mask is applied by the vertical synchronization signal detection signal by the R gate 24 (see FIG. 3), so that the output of the AND gate 22 is directly outputted from the OR gate 24 during normal operation.

When it is not normal, a logical value of "H" is always output. That is, in the normal case, the reset signal of the pulse generator 10 is output to the counter 114 according to the output of the AND gate 22.
However, if it is not normal, the reset signal of the pulse generator 10 is input to the counter 114 regardless of the output of the AND gate 22.

After the output of the pulse generator IO is subjected to the above mask,
It is input to AND gate 18. The counter 114 is reset using either the reset signal obtained as described above or the horizontal forced reset signal. counter 11
The count output of 4 becomes a pixel address in the horizontal direction.

Next, the operation in the vertical direction will be explained. The reset signal output from the pulse generator 14 is masked by the vertical synchronization gate signal by the NAND gate 16 (see FIG. 5).The counter 12B is reset by the action of the AND gate 26 as described above. Either the reset signal obtained in the above manner or the vertical forced reset signal is used. The count output of the counter 126 becomes a pixel address in the vertical direction.

Furthermore, in the D-flip-flop 30, the counter 126
The vertical synchronizing signal is latched by the final reset signal input to the gate 24, the presence or absence of the vertical synchronizing signal is determined, and a vertical synchronizing signal detection signal is output to the OR gate 24. This signal is also output to the outside.

These operations can be summarized as follows.

(11 Pulse generator 1 based on each horizontal and vertical synchronization signal
1 clock width each output from 0.14.

1) Mask processing is performed on the 2-line width reset signal using gate signals generated by the horizontal and vertical decoders 20 and 28. This effectively prevents erroneous reset operations of the counters 114 and 126 due to noise or the like.

(2) Next, gate processing by the vertical synchronization signal detection signal by the D-flip-flop 30 operates to change the processing content depending on the presence or absence of the signal.

For example, the output reset signal of the pulse generator 1O is directly accepted by the counter 114 over a wide range until the state changes from a state with no signal to a state with a signal. It acts to enter noise prevention operation using a gate signal.This is especially useful when power is turned on.

(3) Counter 1 by horizontal and vertical forced reset signals
In a steady state, the reset of 14.126 is locked with the reset based on each horizontal and vertical synchronization signal, and has the effect of stabilizing the operation of the circuit.

d. Effects of the first embodiment As described above, the first embodiment has the following effects.

(As a reset signal for the 11-pixel address counter, various horizontal and vertical synchronization gate signals and vertical synchronization signal detection can be performed without directly using the reset signal generated by a pulse generator based on the synchronization signal separated from the input composite video signal.) Since masking is performed using the signal and the counter is reset in combination with a predetermined forced reset signal, malfunctions can be effectively prevented.

(2) Furthermore, since the counter is reset by accepting a wide range of reset signals when there is no signal, stable operation can be performed quickly and stably when the power is turned on.

(3) Compared to the conventional example, the circuit size can be configured by simply adding one ROM and several gate elements, and the entire circuit has several hundred gates excluding analog parts such as the synchronous separation section. This is a small-scale project. It is easy to implement with general-purpose TTL.

It is also possible to make it into an LSI.

14) There is a time delay due to circuit processing, but if the circuit is determined in clock units for both Nohira and Vertical, the delay l is determined, so the counter output can be used with that delay amount in mind. There is no major change, and there is no effect on the human-powered combo signal itself.

(5) Horizontal/vertical counters can be easily applied to timing signal generation circuits for not only the NTSC system but also other television systems such as the PAL system if it is a 10 bit counter.

Second Example> Next, referring to FIGS. 4 to 7, the second example of one
An example will be explained. This second example corresponds to the second conventional example described above, and performs field detection. Further, in this Q embodiment, by counting the detected fields, a field sequence d suitable for 4-field sequence processing of a single signal signal or 8-field 1-sequence processing of a reference signal for ghost removal is performed. Note that the same reference numerals are used for the same components as in the conventional example and the first embodiment described above.

a. Configuration of the second embodiment First, the configuration of the second embodiment will be explained with reference to FIG. In the figure, a horizontal counter 11
4 is connected to the input side of the decoder 32, and the output side of the vertical counter 126 is connected to the input side of the decoder 32.
connected to the input side of the These decoders 32.3
4, a horizontal signal for field detection and a vertical signal for field detection are respectively output.

And these field detection signals.

field detection horizontal signals outputted from decoders 32 and 34, each input to a D-flip-flop 36 such that the field detection horizontal signal is latched with the field detection vertical signal;
The vertical signal for field detection is a signal as shown in FIG. 4 (E) and FIG. 5 (ID), respectively. The non-inverted output of the D-flip-flop 36 is output as the field detection result, and its inverted output is connected to the clock input of the counter 38. The counter 3B is configured to divide the input signal by 1, for example, and output the divided signal in 2 bits.

b. Operation of the second embodiment Next, the operation of the second embodiment configured as above will be explained. First, the D-flip-flop 36 will be explained. When the counter 126 is reset by a reset signal from the pulse generator 14 based on the vertical synchronization signal, the count value r517J becomes the start of the first line in the case of an odd field. When the field detection horizontal signal shown in FIG. 4(E) is latched at this timing, a logical value of "L" is output from the non-inverted output side. Further, in the case of an even field, the count value r517J of the counter 126 is at the center of the 263rd line, so the similar latch output becomes the logical value rH.

In this way, the non-inverting output side of the D-flip-flop 36 outputs a field detection signal that has a logical value of "L" in odd fields and a logical value of "H" in even fields.

Next, in the counter 38, the field detection result is frequency-divided and counted repeatedly using 2 bits.

A field sequence counter is configured to repeatedly count from "0" to "7" using this count output as the upper bit and the field detection result output from the D-flip-flop 36 as the least significant bit.

This situation is shown in FIG. The output field determination result of the D-flip-flop 36 is as shown in (b) of the same figure with respect to the rising timing of the field detection vertical signal (see IEI in the figure) which is latched by the D-flip-flop 36. On the other hand, the counting operation of the counter 38 is as shown in FIGS. 3B and 3C, and the output as a field sequence counter is as shown in FIG.

Such a count value is used, for example, for processing according to a 4-field sequence for color signals or an 8-field sequence for ghost removal. In this embodiment, it is not possible to specify the absolute color or the field number for ghost removal.
However, in the case of field processing for color or ghost removal, it is often sufficient to know the relative relationships of fields other than odd and even numbers, so it can be used satisfactorily.

C0 Effects of Second Embodiment As described above, according to this second embodiment, the field detector detects even and odd fields, and the field sequence counter detects 4 fields and 8 fields. Since we obtained field sequence signals of , horizontal and vertical pixel addresses as well as
This has the effect that the current position of the signal in the horizontal, vertical, and time axis directions of the image can be displayed satisfactorily.

Note that the other configurations, operations, and effects are the same as those of the first embodiment.

<Third Embodiment> Next, a third embodiment of the present invention will be described with reference to FIGS. 8 to 10. This embodiment corresponds to the third conventional example described above.

Similarly, in the conventional example, No. 1. The same reference numerals are used for the same components as in the second embodiment.

a. Configuration of the third embodiment First, the configuration of the third embodiment will be explained with reference to FIG. In the figure, the non-inverting output side of the D-flip-flop 36 for field discrimination is connected to the select terminal side of the selector 306. The output side of this selector 306 is connected to the input side of the shift register 40. The clock input side of the counter 126 is connected to the shift register 40, and the 1/2 line period pulse is input to the shift register 40 as a clock.

Next, the one-clock delayed output terminal IT of the shift register 40 is connected to the reset terminal side of the RS-flip-flop 42, and the two- to five-clock delayed output terminal 2T is connected to the reset terminal side of the RS-flip-flop 42.
~5T is switched by a switch 44 and connected to the set terminal side of the R3-flip-flop 42.

Next, the output side of the R3 flip-flop 42 is connected to the input side of a D-flip-flop 310 for glitch prevention, and the output side of this flip-flop is the output side of the line extraction pulse. A 1/2 line period pulse is input as a clock to the clock terminal of the D-flip-flop 310.

b. Operation of the third embodiment Next, the operation of the third embodiment will be explained. Comparator 30
4. Selector 306. The basic operation of the D-flip-flop 308 is the same as that of the third conventional example described above. The relationship between the input composite video signal and the count value of the vertical counter 126 in this embodiment is different from that in FIG. 17, and is as shown in FIG. 9.

First, in the case of the first field, for the input composite video signal shown in the same figure (Al), the vertical synchronization signal, 1/
The two-period pulse (rising), the reset signal, and the vertical count value are as shown in (B) to (E) of the same figure, respectively.

As is clear from these figures, the counter 126 is
It is reset at the beginning of line (5H).

Next, in the case of the second field, the vertical synchronization signal, 17
The two-period pulse (rising), reset signal, and vertical count value are as shown in (G) to IJ), respectively.

In this case, the vertical synchronization signal is 1/1 with respect to the horizontal synchronization signal.
/2 lines shifted. Therefore, the counter 12B is also 1/2
4th line with the fastest line (2nd line in total from the 1st field)
It will be reset in the latter half of line 67).

In addition, in the case of normal operation, -r Q
Counting is done from J to r524J. In addition%
The l field is 525Xl/2 lines.

Therefore, the sampling line detection signal output from the comparator 304 appears 1/2 lines earlier in the second field. Therefore, similarly to the third conventional example, selector 306.0 and flip-flop 308 are used, respectively.
As a result, the selector 306 outputs the extraction line detection signal on the same line even if the fields are all fields. Note that the sampling line number on the input side of the comparator 304 is the subtracted value of "line number to be sampled x 2 - 12", considering that the vertical counting operation is performed every 1/2 line. Set.

Next, the sampling line detection signal obtained as described above is input to the shift register 40. In this shift register 40, as shown in FIG.
Shifting of the input pulses is performed. Of these, the same figure (
C) IT delay pulse is R3-flip-flop 42
is input to the reset terminal side of the flip-flop, thereby resetting the flip-flop.

Note that by not performing a direct reset operation using the output of the selector 306 in this manner, malfunction of the R5 flip-flop 42 due to glitches that may occur at the output of the selector 306 is prevented.

The set of R3-flip-flop 42 is shown in FIG.
This is performed using pulses delayed by 2T to 5T, respectively, as shown in (G). The outputs of the RS-flip-flop 42 at this time are as shown in Kl in the same figure.

In this way, in the RS-flip-flop 42, by switching the output from the shift register 40 with the switch 44, a line extraction pulse of negative polarity whose pulse width changes in units of 1/2 lines is generated and output. This line extraction pulse is again subjected to glitch prevention in the D-flip-flop 310 and finally output.

Effects of C0 Third Embodiment As described above, according to this third embodiment, a plurality of delayed outputs of the shift register are selected to reset and set the R3-flip-flop. Line extraction pulses of arbitrary length can be easily obtained in units of lines.

Note that the other configurations, operations, and effects are the same as those of the first and second embodiments.

Other Examples〉 It should be noted that the present invention is not limited to the above-mentioned Examples.
For example, the design of the circuit can be changed to achieve the same effect, and these are also included in the present invention.

Further, the value is not limited to the values shown in the above description, and may be set as appropriate as necessary.

[Effects of the Invention] As explained above, the present invention has the following effects.

+1) For the pixel address counter reset signal,
Along with performing masking using a predetermined gate signal,
Since the count is forcibly reset as necessary, malfunctions are effectively prevented from occurring.

(2) Furthermore, since the counter is reset by accepting a wide range of reset signals when there is no signal, stable operation can be performed quickly and stably when the power is turned on.

(3) Since field discrimination is performed based on the operation of the pixel address counter, even and odd fields can be detected without error. Furthermore, since a field sequence counter is provided, field sequence signals in units of 4 fields and 8 fields can be obtained.

(4) Since the line extraction pulse is generated by selecting a plurality of delayed outputs of the shift register, the line extraction pulse can be made to have an arbitrary length in a predetermined unit.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention, FIGS. 2 to 5 are time charts showing the operation of the first embodiment,
FIG. 6 is a block diagram showing the second embodiment, FIG. 7 is a time chart showing the operation of the second embodiment, FIG. 8 is a block diagram showing the third embodiment, and FIGS. 9 to 10 are FIG. 11 is a configuration diagram showing the first conventional example. FIGS. 12 to 13 are time charts showing the operation of the first conventional example. FIG. 14 is a time chart showing the operation of the first conventional example. FIG. 15 is a time chart showing the operation of the second conventional example, FIG. 16 is a configuration diagram showing the third conventional example, and FIG.
The figure is a time chart showing the operation of the third conventional example. 10.14--Pulse generator, 12.16--NA
ND gate% 18.26-...AND gate. 20.28.32.34...decoder, 22...A
ND gate, 24...OR gate, 30.36-...
D-Flip-flop, 38... Counter, 40...
・Shift register, 42...RS-flip-flop, 114.126...Counter.

Claims (5)

[Claims] (1) A timing signal generation circuit in which a counter that counts a predetermined clock signal and outputs a timing signal is reset by a reset signal generated based on a synchronization signal separated from an input composite video signal, Based on the output of said counter,
A timing signal generation circuit comprising: a decoding circuit that outputs a gate signal corresponding to the synchronization signal; and a first gate circuit that masks the reset signal using the gate signal generated thereby. . (2) In a timing signal generation circuit in which a counter that counts a predetermined clock signal and outputs a timing signal is reset by a reset signal generated based on a synchronization signal separated from an input composite video signal. , based on the output of said counter,
a decoding circuit that outputs a forced reset signal corresponding to the contents of the count value; and a second gate circuit that applies the forced reset signal generated by the decoding circuit to the counter regardless of the presence or absence of the reset signal. A timing signal generation circuit comprising: (3) The timing signal generation circuit according to claim 1, further comprising: a signal detection circuit that detects the presence or absence of the synchronization signal; and a third gate circuit that stops masking by the first gate circuit when no signal is detected. A timing signal generation circuit comprising: (4) The timing signal generation circuit according to any one of claims 1 to 3, further comprising: a decoding circuit that outputs a field detection signal corresponding to the synchronization signal based on the output of the counter; 1. A timing signal generation circuit comprising: a field detection circuit that performs field detection using a field detection signal; and a count circuit that performs counting of a desired sequence using an output of the field detection circuit. (5) The timing signal generation circuit according to any one of claims 1 to 3, further comprising: a decoding circuit that outputs a field detection signal corresponding to the synchronization signal based on the output of the counter; A field detection circuit that performs field detection using a field detection signal, a line detection circuit that uses the output of this field detection circuit to generate a sampling line detection signal indicating a desired extraction line, and extraction of this line detection circuit. 1. A timing signal generation circuit comprising: a pulse output circuit that generates a line extraction pulse of a desired length using a line detection signal.