JPH03132052A - Mis boundary evaluation method and device - Google Patents

Abstract

PURPOSE:To enable the evaluation of the interface between two kinds of different insulating films, i.e., polycrystalline Si and SiO2 films so as to optimize the condition of a film formation process by evaluating the semiconductor of a sample, which is manufactured through an actual semiconductor process, and the interface of the insulating films, using an FET cell which has minute stray capacitance with extremely minute area. CONSTITUTION:An FET cell, which has a floating electrode being insulated from the circumstance and consisting of semiconductor material, is used for evaluation within the gate insulating film between a MOS FET being the constituent unit element of an LSI and a semiconductor having a gate electrode and source and drain electrodes with the same area. A trap generated at the interface between the floating electrode and the insulating film captures carriers this way, and trap level and lavel density are evaluated from the difference of the threshold of the cell viewed from the gate electrode before and after the capture. Or the unit beam in the region of visible radiation to ultraviolet ray is applied to the vicinities of the floating electrode and the insulating film so as to excite the carriers captured in a trap, and by measuring the threshold of the cell the time constant of attenuation properties is sought and the density and distribution can be known.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for evaluating an interface between a semiconductor and an insulating film, particularly an interface between silicon and a silicon oxide film;

9 Regarding evaluation equipment [Prior art] As a method for evaluating the silicon-silicon oxide film interface, C-■ ((Capacit, a
nce -V oltage) ) method, Solid State Electronics 13 (1970) No. 8
Pages 73 to 885 (Solid State
E 1ectron.

13 (1970) pp. 873-885). In addition, D L T S ((Deep
Level Transient Spectro
An example of applying this method to the analysis of the interfacial state of an MO5 structure is given in Applied Physics, 18 (1979), pp. 169 to 175 (Appl, Phys, l 8 (1979) P.
r2O3-175).

[Problem to be solved by the invention]

The C-v method described above is a method of determining the interface state density of a silicon-silicon oxide film from the change in the depletion layer capacitance of the semiconductor junction when the bias voltage is changed using the MO3O3 capacitance. In the photo-excited DLTS method, the time constant of transient capacitance change at the junction, which occurs during the thermal dissociation process of carriers trapped in the interface state when a MO3O3 capacitance pulse voltage is applied or pulsed light is irradiated, is calculated over a wide temperature range. This method determines the interface state and interface state density by measuring within a range. Both methods measure minute changes in capacitance, so a capacitance of several tens of P F or more is required, and a large-area MOS device is required. However, there were drawbacks such as low accuracy and low accuracy.

The purpose of the present invention is to eliminate trap levels and traps formed at the interface between silicon and silicon oxide films, as well as at the interface between semiconductor and insulating films, in an area comparable to that of a MOSFET, which is a basic element constituting an actual LSI. An object of the present invention is to provide a method and apparatus for accurately and simply determining the level density.

[Means to solve the problem]

In order to achieve the above objective, a gate insulating film, which has the same area as a MOS-FET, which is a constituent element of an LSI, and is insulated from the surroundings, is placed between a gate electrode and a semiconductor substrate having source and drain electrodes. An FET cell having a structure having a floating electrode made of a semiconductor material is used. Carriers are captured in a trap formed at the interface between the floating electrode and the insulating film.

V is the threshold voltage of the FET cell seen from the gate electrode before and after carriers are captured in this trap. . .

and VGL, then the difference between these two considerations V a t −V
ao is.

It is proportional to the amount of charge of carriers captured in the trap. Monochromatic light in the visible to ultraviolet region is irradiated near the interface between the floating electrode and the insulating film to excite the carriers captured in the traps, and the threshold voltage V a (t) of the FET cell is measured, and its attenuation is measured. Find the time constant τ of the characteristic. Next, the time constant τ(E) is determined in the same manner by changing the wavelength of the monochromatic light (photon energy E).

The reciprocal of this time constant τ(E) corresponds to the ratio of the number of excited carriers to the number of incident photons of monochromatic light, that is, the quantum efficiency. By determining the reciprocal l/τ(E) of this time constant as a function of the incident photon energy E, the interface state density formed at the interface between the floating electrode and the insulating film and its distribution function can be determined.

In order to embody the above method, the above test sample FET
means for measuring the cell threshold voltage and injecting carriers;
A means of irradiating a sample with monochromatic light for a certain period of time by having a variable wavelength light source with a constant amount of light, and calculating the time constant of threshold voltage attenuation from the above irradiation time and the measured threshold voltage, and converting this time constant into the time constant of the monochromatic light. An apparatus is used that is equipped with a means for calculating the energy distribution of the interface state and the density of the interface state from this by determining the energy distribution as a function of the photon energy E. In addition, by setting measurement FET cells to evaluate this interface at multiple locations within the wafer, the distribution of the interface state between the semiconductor and the insulating film within the wafer can be monitored, making it possible to evaluate processes, evaluate wafers between lots, Furthermore, it becomes possible to evaluate the quality of new semiconductors and insulating film materials, as well as their combinations.

[Effect]

The principle of the method for measuring the interface state density between a semiconductor and an insulating film according to the present invention will be explained below.

The threshold voltage of the FET cell as seen from the gate electrode in a state where carriers are not captured and a state where carriers are captured in the traps existing at the interface between the semiconductor and the insulating film are respectively V a o + V a Let it be t. To inject carriers into the trap, a saturation current is passed between the source and drain of the semiconductor substrate, and the hot carriers generated in the high electric field area near the drain are transferred to the hot carriers generated in the insulating film by the voltage applied to the gate electrode. Tunnel current or Fowler-Nordheim (Fowler-Nordheim)
ovler Nordheim) There is a method of injecting it as a tunnel current. If the capacitance between the floating electrode and the gate electrode is C3, carriers Q are captured in the trap.

The number No and the charge Qo are N o = = Cz (V
OI V a o ). Next, monochromatic light of wavelength λ (photon energy E) and light intensity P is irradiated near the interface between the floating electrode and the insulator for a time t to excite the carriers captured in the traps and cause them to disappear. In this case, the threshold voltage of the FET cell viewed from the gate electrode is ■. (1), the number N (t) of carriers remaining in the trap and the charge Q (t) can be expressed by the following equations.

Photocurrent I (
t) is the electric field F in the insulating film caused by the charge Q (t) remaining in the trap. Since X is proportional to the amount of light P, the following differential equation holds true.

However, ε1 is the dielectric constant of the insulating film, and b is a constant.

When the above differential equation is solved for Q (t), the following equation holds true.

(VG(t) −Vao)/(Vat−V(1
0) can be expressed as an exponential relationship between time t and light amount P, and τ=T
v is the time constant of its decay. Here, the number of incident photons per second when the FET cell is irradiated with monochromatic light of light amount P is n
P can be expressed by E 1nstein's relational expression, nP=number,
C is the speed of light.

The cumulative number of photons np・τ that entered during the time τ until N(t)/No decays to 1/e valve 0.37 (e is the base of the natural logarithm) and the carriers captured in the trap are The ratio of the number of excited and extinguished carriers No−N(τ) is
It is the carrier excitation probability η of a photon, and η can be expressed by the following equation.

Therefore, the reciprocal of the time constant τ is proportional to the photon carrier excitation probability. In the energy level diagram of an interface trap caused by impurities or defects at the interface between a semiconductor and an insulating film, carriers trapped in a level lower than photon energy E are excited, but carriers are trapped in a level higher than E. Carriers are not excited. Even if the carriers are excited, the carriers trapped in the lower level will be excited and the carriers will be excited after the level is empty, so the probability of excitation of the carriers trapped above E is extremely low. It is considered small. Therefore, when the energy distribution function of the trap density existing at this interface is n+t(c), when monochromatic light of photon energy E is irradiated, the density of carriers remaining trapped in the traps is determined. On the other hand, the number of carriers remaining in the trap is
From both equations, N (t) = No cxp(--) =
By differentiating with No expτ −E and finding the value when t=τ, the energy distribution function of the trap density can be found by performing numerical analysis as a function of the photon energy E. Furthermore, the trap density NL existing at the interface between the insulating film and the semiconductor having a narrower energy band gap
T is the valence band and conduction band of the semiconductor, respectively, Ev
, Ec, N IT: f vnIT d E=0
．． 37No f:cゞ-'L! ' = 0.37N
.

ni ηo
It is determined by n (n (Ev)/η(EC)).

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 11. Figures 1 to 3 are FE for evaluation.
Figure 1 shows the cross-sectional structure of the T cell.
A source 3 and a drain trench formed by doping impurities of different polarities are provided in the buried layer 2 deeply doped with impurities of a different polarity from those of the i&plate, and on the channel part 5 between the source and the drain, An insulating film 6 to be evaluated and a floating i-electrode 7 made of polycrystalline silicon are formed, and an insulating film 8 and a metal or
The figure shows an FET cell having a structure in which a gate electrode 9 made of polycrystalline silicon or the like is provided.
dProgrammable Read 0nly M
(emory) can be created through the manufacturing process.

In FIG. 2, amorphous silicon 11 is deposited on an insulating film 10, selectively made into a single crystal, this portion is doped with a desired impurity, and a source 3. A drain 4 and a channel region 5 are formed, and Il! to be evaluated is formed on the channel region 5. A burlap film 6 and a floating Ti electrode 7 made of a semiconductor thin film are formed, and an insulating film 8 is formed thereon. and an FE with a structure provided with a gate electrode 9 made of metal, polycrystalline silicon, etc.
T cell is shown and So I (Silicon On
It can be manufactured using the In5lator process.

FIG. 3 shows a semiconductor substrate 1 and a buried layer 2 deeply doped with impurities of a polarity different from that of the substrate, provided with a source 3 and a drain 4 each doped with impurities of different polarity, and between the source and drain. A thin film Ga, 6b made of a different type of extinct wood to be evaluated is formed on the channel portion 5 of the board, a floating electrode 7 is formed near and at the interface of this thin film, and an insulating film 8 and a metal 8 or An FET cell having a structure provided with a gate electrode 9 made of polycrystalline silicon or the like, in which silicon is used for the semiconductor substrate 1 and silicon dioxide and silicon nitride are used for the insulating films 60 and 61, respectively, is an ordinary M N OS (MetalNitride) cell.
It can be manufactured using a manufacturing process for non-volatile memory (Oxide Sem1 conductor) type non-volatile memory.

The following FET cells for evaluation are i! In order to obtain electrical continuity with the probe for measuring temporal characteristics, a substrate or embedded layer 2, an electrode 1,
A source 3, a drain 4, and a gate electrode 9 are interconnected using a metal thin film, and an electrode pad is provided at the tip of the interconnect.

FIG. 4 is a block diagram showing electric circuit means for measuring the threshold voltage of the evaluation FET cell and for injecting carriers into the floating Ti electrode or the insulating film interface and its vicinity. In order to bring the probe into contact with the electrode pad 21, source electrode pad 22, drain electrode pad 23, and gate electrode pad 24 of the substrate of the FET cell 20 or the buried layer, and apply a voltage with a predetermined waveform to these electrodes. variable power supplies 31, 32. and a square wave generator 33, a step wave or triangular wave generator 34 for measuring the threshold voltage of the FET cell, a comparator 35, a reference voltage generator 36, for measuring the threshold voltage and injecting carriers into the floating electrode. Changeover switch 37, microcomputer 38 that controls these
, and a light shielding box 40. To measure the threshold voltage, connect the changeover switch 37 to the R side, apply a predetermined voltage to the substrate and drain electrode of the FET cell, and
A step wave or a triangular wave is applied to the gate electrode until the source current of the T cell flows to a specified current value. When the source current reaches a specified value, the gate voltage vcl is measured based on the output from the comparator 35, and the voltage applied to each electrode is set to 0 volts. These controls are performed via the microcomputer 38.

To inject carriers into the floating electrode, turn the changeover switch 37 to W.
This is done by connecting the FET cell to the same side and applying a predetermined voltage waveform to the substrate, source, drain, and gate of the FET cell. Setting and application of these predetermined voltage waveforms are performed via the microcomputer 38.

FIG. 5 shows the evaluation FET cell 20 on the wafer 30
, Y, Z, attached to a 3-axis movable base 41, and converts the broad wavelength light from light @42 into monochromatic light using a spectrometer 43.
This monochromatic light is irradiated onto the sample surface. Cell 20 on wafer
an optical microscope 44 necessary for positioning, a shutter 45 for irradiating monochromatic light for a certain period of time, a filter 46 for attenuating high-order waves from the spectrometer, and a monitor for keeping the amount of light irradiated onto the sample constant. Increased feedback of photosensor output to photosensor 47 and light source power source 48 l11g
It is enlightened from vessel 49.

As an example of the present invention, the results of an experiment conducted using an n-channel FET cell formed of polycrystalline silicon and a silicon oxide film as a sample and having the structure shown in FIG. 1 are shown in FIGS. 6 to 9.
As shown in the figure.

Figure 6 shows the threshold voltage ■ as seen from the gate electrode when carriers are not injected into the floating electrode of the FET cell. The carrier injection, which shows the relationship between the source current I and the substrate current I, is the substrate and source current I? ! ! The electrode is grounded, and a predetermined voltage waveform that causes the FET to operate in saturation is applied to the gate and drain electrodes. At this time, hot carriers that are accelerated by the high electric field in the depletion layer near the drain and have gained energy that exceeds the barrier energy between silicon and silicon oxide film are injected into the silicon oxide film by the electric field that exists in the oxide film. It is captured in traps formed at and near the interface between polycrystalline silicon and silicon oxide film. The relationship between the threshold voltage 6 of the FET cell and the source current as seen from the gate electrode 1 at this time is shown by the broken line in the figure.
In this case, the captured carriers are electrons. FE when no electron is captured in the interface trap and when it is captured
The threshold voltage of the T cell is V. . +VGL. In the captured state, the threshold voltage when monochromatic light is irradiated near the floating electrode of the cell for t hours is (■). (1).

Figure 7 shows the initial value of the threshold voltage change (V o
□V. o), i.e. (VG(t)-VG0)
/(V a 1V,,a) represents the relationship between monochromatic light irradiation time. (VG(t)-VG0)/(Vut-
VuJ is attenuated by an exponential function of L. From this relationship, find the time constant τ until (Va(t)-VG0) / (Vat-Vao) decays to 1 / e 40.37 (e is the base of the natural logarithm), and calculate the photon carrier excitation probability η seek. Next, the wavelength of the monochromatic light, that is, the photon energy E is changed, the decay time constant τ(E) of the threshold voltage is measured, and the carrier excitation probability η(E) of the photon is determined.

FIG. 8 shows the photon-energy E dependence of the photon carrier excitation probability η(E). At this time, consider the photon energy E with reference to the conduction band of the silicon oxide film. An approximate expression is obtained as a function of η(E), and the energy distribution of degrees n+t(E) is obtained.

FIG. 9 shows the distribution of electron trap level density formed at the interface between polycrystalline silicon and silicon oxide film. The broken line in the figure shows the distribution of electron trap level density when the same sample was subjected to a high temperature storage test and deteriorated. It can be seen that due to thermal stress, the trap level density in the band gap of silicon decreases slightly on the conduction band side, and increases from the center to the valence band. Also, the trap density at this time is also 10”
/(1m" order, which is close to the value of the interface state density between the silicon substrate and the silicon oxide film. Furthermore, P-channel FE
By using a T cell and trapping holes at the interface between polycrystalline silicon and silicon oxide film,
Needless to say, the hole trap level density is required.

Evaluation F with the structure shown in Figures 1 to 3 above.
Examples in which the ET cell is installed on a wafer or a chip are shown in FIGS. 10 and 11.

FIG. 10 shows an example in which the evaluation FET cell 20 is installed in the scribe area 51 of the wafer 30 or in the uncollected chip portion 52 on the periphery of the wafer.

FIG. 11 shows a portion 53 (for mask alignment) on an integrated circuit chip 50, 4J! MO of DRAM, SRAM, etc., which shows an example in which the evaluation FET cell 20 is installed in a blank area without elements, electrodes, or wiring that would dry up the product circuit.
In LSIs such as S memory, by installing the above evaluation FET cell on an LSI wafer or chip and using the evaluation method of the present invention, it is possible to
It is possible to evaluate the interface between films and the interface between insulating films made of different insulating materials.

〔Effect of the invention〕

According to the present invention, the ? ? J
Actual semiconductor y5 using FET cell with t electrode
It is possible to accurately evaluate the interface between the semiconductor and the insulating film of the sample manufactured through the manufacturing process. It is possible to evaluate the interface between two different types of insulating films, polycrystalline silicon and silicon oxide films, in current MOS memories and other LSI products, and to optimize process conditions for forming silicon oxide films, polycrystalline silicon thin films, and insulating films. It is possible to improve the performance of elements. Furthermore, it can be used as an evaluation method for future SOI technology, new conductor materials, insulation material selection, and manufacturing process conditions. Furthermore, the FE of this structure
By distributing T cells on a wafer, it is possible to evaluate processes, evaluate variations within a wafer, and monitor variations between lots, contributing to quality improvement.

[Brief explanation of the drawing]

1 to 3 are longitudinal cross-sectional views of an FET cell having a floating electrode according to an embodiment of the present invention, and FIG. 4 shows an electric circuit for measuring the threshold voltage of the FET cell and injecting carriers into the floating yIi electrode. Figure 5 is a block diagram of an optical system for irradiating monochromatic light with a fixed view for a fixed period of time near the floating electrode of the cell, and Figure 6 shows the FET source current and goo depending on the presence or absence of carriers in the floating electrode. 1 - A diagram showing the change in voltage, Figure 7 is a diagram showing the attenuation characteristic of the threshold voltage of the FET cell during monochromatic light irradiation, and Figure 8 is a diagram showing the dependence of photon carrier excitation probability η on photon energy E. , FIG. 9 is a diagram showing the energy distribution of electron trap level density, FIG. 10 is a diagram showing an example of installing an evaluation FET cell on a wafer, and FIG.
FIG. 1 is a diagram showing an example of 12E1 on a chip of an evaluation FET cell. 1... Silicon substrate, 2... Buried layer, 3... Source, 4. Drain, 5... Channel region, G-#A
Edge layer, 7・M electrode, 8... Insulating film, 9... Gate electrode 9th] Plan? Fig. Fig. Fig. 5 Gate mill 1 vr, - Fig. g Fig. Mazu Kameko 1 half rube EIeVE- 1 half ruki - Drop [eVl Fig. 1 O Fig. 11 zo---FETILl 4 - Claw) Te A〉7゛Ha0・Soto

Claims (1)

[Claims] 1. Having a source and a drain of a semiconductor substrate, or
A thin film made by crystallizing amorphous silicon deposited on an insulating film has a source and a drain, and an interface between the insulating film and semiconductor to be evaluated is placed on the substrate or thin film between the source and drain. MISFET (Metal I
nsulatorSemiconductorFiel
dEffectTransistor), the FE observed from the gate electrode before and after carrier injection is applied to the interface between the insulating film and the semiconductor to be evaluated, or the interface between two different insulating films, and the trap formed in the vicinity thereof.
When the threshold voltages of T are V_G_0 and V_G_1, after capturing carriers in the trap, monochromatic light with photon energy E is irradiated on this interface and the vicinity for a time t to excite and extinguish the carriers. Threshold voltage V
From the change in _G(t), (V_G(t)-V_G_0)/
Find the decay time constant of (V_G_1-V_G_0), and from this time constant find the carrier excitation probability η of photons of monochromatic light,
An MIS interface evaluation method characterized in that an approximate expression is obtained using η as a function of E, and from this, an energy distribution of a trap level density and a trap level density are obtained. 2. Means for measuring the threshold voltage of the MISFET that is the evaluation sample, means for injecting carriers into traps formed at and near the interface between the semiconductor and insulating film to be evaluated, or at and near the interface of different insulating films, Calculating the photon carrier excitation probability η from the means for irradiating the sample surface with monochromatic light for a certain period of time and the time constant of the threshold voltage decay of the FET,
A MIS interface evaluation device comprising a calculation means for determining the trap level density formed at and near the interface and its energy distribution. 3. The evaluation MISFETs having the structure described in claim 1 are distributed and arranged in an area on the wafer that does not reduce the chip yield, for example, the circumference of the wafer or the scribe area, and the semiconductor and insulating film,
Alternatively, a semiconductor manufacturing method characterized by obtaining information regarding the density of traps formed at and near the interface of different insulating films.