JPH03132052A - Mis boundary evaluation method and device - Google Patents

Mis boundary evaluation method and device

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Publication number
JPH03132052A
JPH03132052A JP26890089A JP26890089A JPH03132052A JP H03132052 A JPH03132052 A JP H03132052A JP 26890089 A JP26890089 A JP 26890089A JP 26890089 A JP26890089 A JP 26890089A JP H03132052 A JPH03132052 A JP H03132052A
Authority
JP
Japan
Prior art keywords
interface
semiconductor
insulating film
carriers
trap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26890089A
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Japanese (ja)
Other versions
JP2609728B2 (en
Inventor
Riichi Uetsuki
植月 利一
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Hitachi Ltd
Original Assignee
Hitachi Ltd
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Priority to JP26890089A priority Critical patent/JP2609728B2/en
Publication of JPH03132052A publication Critical patent/JPH03132052A/en
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Publication of JP2609728B2 publication Critical patent/JP2609728B2/en
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Expired - Lifetime legal-status Critical Current

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To enable the evaluation of the interface between two kinds of different insulating films, i.e., polycrystalline Si and SiO2 films so as to optimize the condition of a film formation process by evaluating the semiconductor of a sample, which is manufactured through an actual semiconductor process, and the interface of the insulating films, using an FET cell which has minute stray capacitance with extremely minute area. CONSTITUTION:An FET cell, which has a floating electrode being insulated from the circumstance and consisting of semiconductor material, is used for evaluation within the gate insulating film between a MOS FET being the constituent unit element of an LSI and a semiconductor having a gate electrode and source and drain electrodes with the same area. A trap generated at the interface between the floating electrode and the insulating film captures carriers this way, and trap level and lavel density are evaluated from the difference of the threshold of the cell viewed from the gate electrode before and after the capture. Or the unit beam in the region of visible radiation to ultraviolet ray is applied to the vicinities of the floating electrode and the insulating film so as to excite the carriers captured in a trap, and by measuring the threshold of the cell the time constant of attenuation properties is sought and the density and distribution can be known.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体と絶縁膜の界面、中でも、シリコンと
シリコン酸化膜の界面の評価方法、及び。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for evaluating an interface between a semiconductor and an insulating film, particularly an interface between silicon and a silicon oxide film;

評価装置に関する9 〔従来の技術〕 シリコン−シリコン酸化膜界面の評価法として、従来か
ら、MO8容量を用いたC−■((Capacit、a
nce −V oltage) )法があり、ソリッド
・ステート・エレクトロニクス13 (1970)第8
73頁から第885頁(S olid S tate 
E 1ectron。
9 Regarding evaluation equipment [Prior art] As a method for evaluating the silicon-silicon oxide film interface, C-■ ((Capacit, a
nce -V oltage) ) method, Solid State Electronics 13 (1970) No. 8
Pages 73 to 885 (Solid State
E 1ectron.

13 (1970) pp873〜885)において論
じられている。また、半導体中の不純物や欠陥の準位や
密度を求める方法としてD L T S ((Deep
 LevelT ransient S pectro
scopy))法があり、この方法をMO5構造の界面
状態の解析に適用した例として、アプライド フィジッ
クス、 18 (1979)第169頁から第175頁
(Appl 、 Phys、  l 8(1979)P
r2O3−175)に記載されている。
13 (1970) pp. 873-885). In addition, D L T S ((Deep
Level Transient Spectro
An example of applying this method to the analysis of the interfacial state of an MO5 structure is given in Applied Physics, 18 (1979), pp. 169 to 175 (Appl, Phys, l 8 (1979) P.
r2O3-175).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記、C−v法では、MO3O3容量いて、バイアス電
圧を変化させたときの半導体接合部の空乏層容量の変化
から、シリコン−シリコン酸化膜の界面準位密度を求め
る方法であり、DLTS法、及び光励起DLTS法では
、MO3O3容量パルス電圧を印加、又は、パルス光を
照射した時の、界面準位にトラップされたキャリアの熱
解離過程で生じる接合部の過度容量変化の時定数を、広
い温度範囲で測定することにより、界面準位、及び界面
準位密度を求める方法で、いずれも、微小容量の変化を
測定するため、数10 P F以上の容量が必要で、大
面積のMOS素子が必要であり、精度も低い等の欠点が
あった。
The C-v method described above is a method of determining the interface state density of a silicon-silicon oxide film from the change in the depletion layer capacitance of the semiconductor junction when the bias voltage is changed using the MO3O3 capacitance. In the photo-excited DLTS method, the time constant of transient capacitance change at the junction, which occurs during the thermal dissociation process of carriers trapped in the interface state when a MO3O3 capacitance pulse voltage is applied or pulsed light is irradiated, is calculated over a wide temperature range. This method determines the interface state and interface state density by measuring within a range. Both methods measure minute changes in capacitance, so a capacitance of several tens of P F or more is required, and a large-area MOS device is required. However, there were drawbacks such as low accuracy and low accuracy.

本発明の目的は、実際のLSIを構成する基本素子であ
るMOSFETと同じ程度の面積で、シリコンとシリコ
ン酸化膜の界面、さらに半導体と絶縁膜との界面に形成
されたトラップ準位、及びトラップ準位密度を、正確に
、簡mに求める方法及び、装置を提供するにある。
The purpose of the present invention is to eliminate trap levels and traps formed at the interface between silicon and silicon oxide films, as well as at the interface between semiconductor and insulating films, in an area comparable to that of a MOSFET, which is a basic element constituting an actual LSI. An object of the present invention is to provide a method and apparatus for accurately and simply determining the level density.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するために、LSIの構成単位素子であ
るMOS −FETと同じ面積で、ゲート電極と、ソー
ス及びドレイン電極をもつ半導体基板との間のゲート絶
縁膜中に、周囲から絶縁された半導体材料からなる浮遊
電極を有する構造のFETセルを用いる。この浮遊電極
と絶縁膜との界面に形成されたトラップにキャリアを捕
獲させる。
In order to achieve the above objective, a gate insulating film, which has the same area as a MOS-FET, which is a constituent element of an LSI, and is insulated from the surroundings, is placed between a gate electrode and a semiconductor substrate having source and drain electrodes. An FET cell having a structure having a floating electrode made of a semiconductor material is used. Carriers are captured in a trap formed at the interface between the floating electrode and the insulating film.

このトラップにキャリアが捕獲される前後のゲート電極
からみたFETセルのしきい電圧をV。。。
V is the threshold voltage of the FET cell seen from the gate electrode before and after carriers are captured in this trap. . .

及びVGLとすると、この両考の差V a t −V 
a oは。
and VGL, then the difference between these two considerations V a t −V
ao is.

トラップに捕獲されたキャリアの電荷量に比例する。浮
遊電極と絶縁膜界面近傍に、可視光〜紫外光領域の単色
光を照射して、トラップに捕獲されたキャリアを励起さ
せ、FETセルのしきい電圧V a (t )を測定し
、その減衰特性の時定数τを求める。次に、単色光の波
長(光子エネルギーE)を変えて、同様にして、時定数
τ(E)を求める。
It is proportional to the amount of charge of carriers captured in the trap. Monochromatic light in the visible to ultraviolet region is irradiated near the interface between the floating electrode and the insulating film to excite the carriers captured in the traps, and the threshold voltage V a (t) of the FET cell is measured, and its attenuation is measured. Find the time constant τ of the characteristic. Next, the time constant τ(E) is determined in the same manner by changing the wavelength of the monochromatic light (photon energy E).

この時定数τ(E)の逆数は、単色光の入射光子数に対
し、励起されるキャリア数との比、即ち、量子効率に対
応している。この時定数の逆数l/τ(E)を入射光子
エネルギーEの関数として求めることにより、浮遊電極
と絶縁膜の界面に形成された界面準位密度、及び、その
分布関数が求められる。
The reciprocal of this time constant τ(E) corresponds to the ratio of the number of excited carriers to the number of incident photons of monochromatic light, that is, the quantum efficiency. By determining the reciprocal l/τ(E) of this time constant as a function of the incident photon energy E, the interface state density formed at the interface between the floating electrode and the insulating film and its distribution function can be determined.

上記方法を具現化するには、上記供試試料であるFET
セルのしきい電圧を測定し、キャリアを注入する手段、
光量一定の波長可変の光源を有し試料に単色光を一定時
間照射する手段、上記照射時間と測定したしきい電圧か
ら、しきい電圧減衰の時定数を算出し、この時定数を単
色光の光子エネルギーEの関数として求め、これより界
面準位のエネルギー分布、及び界面準位密度を算出する
手段を具備した装置を用いる。又この界面を評価するた
めの測定用FETセルを、ウェハ内の複数箇所に設定し
ておけば、ウェハ内の半導体と絶縁膜の界面状態の分布
がモニタできプロセス評価、ウェハのロット間評価、さ
らには新しい半導体、及び絶縁膜材料の良否、及び、そ
の組合せの評価が可能となる。
In order to embody the above method, the above test sample FET
means for measuring the cell threshold voltage and injecting carriers;
A means of irradiating a sample with monochromatic light for a certain period of time by having a variable wavelength light source with a constant amount of light, and calculating the time constant of threshold voltage attenuation from the above irradiation time and the measured threshold voltage, and converting this time constant into the time constant of the monochromatic light. An apparatus is used that is equipped with a means for calculating the energy distribution of the interface state and the density of the interface state from this by determining the energy distribution as a function of the photon energy E. In addition, by setting measurement FET cells to evaluate this interface at multiple locations within the wafer, the distribution of the interface state between the semiconductor and the insulating film within the wafer can be monitored, making it possible to evaluate processes, evaluate wafers between lots, Furthermore, it becomes possible to evaluate the quality of new semiconductors and insulating film materials, as well as their combinations.

〔作用〕[Effect]

以下、本発明に係わる半導体と絶縁膜との界面準位密度
の測定法の原理について説明する。
The principle of the method for measuring the interface state density between a semiconductor and an insulating film according to the present invention will be explained below.

半導体と絶縁膜の界面に存在するトラップに、キャリア
が捕獲されてない状態と、キャリアが捕獲されている状
態での、ゲート電極からみたFETセルのしきい電圧を
、それぞれV a o + V a tとする。尚、ト
ラップにキャリアを注入するには、半導体基板のソース
とドレイン間に飽和電流を流し、ドレイン近傍の高電界
部分で発生するホットキャリアを、ゲート電極に印加し
た電圧で発生する絶縁膜中の電界で引き込む方法や、ゲ
ート電極と基板間の絶縁膜中に存在する電界により、ト
ンネル電流、あるいは、ファウラーノルドハイム(F 
ovler Nordheim)  トンネル電流とし
て注入する方法がある。浮遊電極とゲート電極の間の容
量をC3とすると、トラップに捕獲されたキャリアQ。
The threshold voltage of the FET cell as seen from the gate electrode in a state where carriers are not captured and a state where carriers are captured in the traps existing at the interface between the semiconductor and the insulating film are respectively V a o + V a Let it be t. To inject carriers into the trap, a saturation current is passed between the source and drain of the semiconductor substrate, and the hot carriers generated in the high electric field area near the drain are transferred to the hot carriers generated in the insulating film by the voltage applied to the gate electrode. Tunnel current or Fowler-Nordheim (Fowler-Nordheim)
ovler Nordheim) There is a method of injecting it as a tunnel current. If the capacitance between the floating electrode and the gate electrode is C3, carriers Q are captured in the trap.

の数No、電荷Qoは、N o =  = Cz (V
 OI  V a o )である。次に、波長λ(光子
エネルギーE)、光量Pの単色光を、浮遊電極と絶縁体
界面近傍に、時間tだけ照射し、トラップに捕獲されて
いるキャリアを励起し、消失させる。こと時、ゲート電
極からみたFETセルのしきい電圧を■。(1)とする
と、トラップに残存するキャリアの数N (t)、電荷
Q (t)は、次式で表わせる。
The number No and the charge Qo are N o = = Cz (V
OI V a o ). Next, monochromatic light of wavelength λ (photon energy E) and light intensity P is irradiated near the interface between the floating electrode and the insulator for a time t to excite the carriers captured in the traps and cause them to disappear. In this case, the threshold voltage of the FET cell viewed from the gate electrode is ■. (1), the number N (t) of carriers remaining in the trap and the charge Q (t) can be expressed by the following equations.

光照射時にトラップから励起されて流れる光電流I (
t)は、トラップに残存する電荷Q (t)により生じ
る絶縁膜中の電界F。Xと、光量Pに比例するので、次
の微分方程式が成立する。
Photocurrent I (
t) is the electric field F in the insulating film caused by the charge Q (t) remaining in the trap. Since X is proportional to the amount of light P, the following differential equation holds true.

但し、ε1は絶縁膜の誘電率、bは定数である。However, ε1 is the dielectric constant of the insulating film, and b is a constant.

上記、微分方程式をQ (t)について解くと、次式が
成立する。
When the above differential equation is solved for Q (t), the following equation holds true.

なり、(VG(t) −Vao)/ (Vat−V(1
0)は、時間tと、光量Pの指数関係で表わせ、τ=T
vは、その減衰の時定数である。ここでFETセルに光
量Pの単色光を照射したときの毎秒当りの入射光子数n
PはE 1nsteinの関係式で表わせ、nP=数、
Cは光速である。
(VG(t) −Vao)/(Vat−V(1
0) can be expressed as an exponential relationship between time t and light amount P, and τ=T
v is the time constant of its decay. Here, the number of incident photons per second when the FET cell is irradiated with monochromatic light of light amount P is n
P can be expressed by E 1nstein's relational expression, nP=number,
C is the speed of light.

N(t)/Noが1 / e 弁0.37 (eは自然
対数の底)に減衰する迄の時間τの間に入射した累積光
子数np・τと、トラップに捕獲されていたキャリアが
励起され消失したキャリア数No−N(τ)との比が、
光子のキャリア励起確率ηであり、ηは次式で表わせる
The cumulative number of photons np・τ that entered during the time τ until N(t)/No decays to 1/e valve 0.37 (e is the base of the natural logarithm) and the carriers captured in the trap are The ratio of the number of excited and extinguished carriers No−N(τ) is
It is the carrier excitation probability η of a photon, and η can be expressed by the following equation.

従って1時定数τの逆数は、光子のキャリア励起確率に
比例する。半導体と絶縁膜界面の不純物や欠陥に起因す
る界面トラップのエネルギー準位図において、光子エネ
ルギーEより低い準位に捕獲されているキャリアは励起
されるが、Eより高い準位に捕獲されているキャリアは
励起されない。仮りに励起されたとしても、準位の低い
所に捕獲されていたキャリアが励起され、その準位が空
になってから励起されるので、E以上に捕獲されている
キャリアの励起確率は極めて小さいと考えられる。そこ
で、この界面に存在するトラップ密度のエネルギー分布
関数をn+t(c)として、光子エネルギーEの単色光
を照射した時、トラップに捕獲されたままのキャリアの
密である。一方、トラップに残存するキャリアの数は、
両式からN (t) = No cxp(−−) = 
No expτ −Eで微分し、 t=τの時の値を求めると、 を光子エネルギーEの関数として、数値解析することに
より、トラップ密度のエネルギー分布関数が求められる
。更に、絶縁膜とそれより狭いエネルギーバンドギャッ
プを有する半導体との界面に存在するトラップ密度NL
Tは、半導体の価電子帯、及び導電帯を、それぞれEv
、EcとするとN IT: f vnIT d E=0
.37No f:cゞ−’L!’ = 0.37 N 
Therefore, the reciprocal of the time constant τ is proportional to the photon carrier excitation probability. In the energy level diagram of an interface trap caused by impurities or defects at the interface between a semiconductor and an insulating film, carriers trapped in a level lower than photon energy E are excited, but carriers are trapped in a level higher than E. Carriers are not excited. Even if the carriers are excited, the carriers trapped in the lower level will be excited and the carriers will be excited after the level is empty, so the probability of excitation of the carriers trapped above E is extremely low. It is considered small. Therefore, when the energy distribution function of the trap density existing at this interface is n+t(c), when monochromatic light of photon energy E is irradiated, the density of carriers remaining trapped in the traps is determined. On the other hand, the number of carriers remaining in the trap is
From both equations, N (t) = No cxp(--) =
By differentiating with No expτ −E and finding the value when t=τ, the energy distribution function of the trap density can be found by performing numerical analysis as a function of the photon energy E. Furthermore, the trap density NL existing at the interface between the insulating film and the semiconductor having a narrower energy band gap
T is the valence band and conduction band of the semiconductor, respectively, Ev
, Ec, N IT: f vnIT d E=0
.. 37No f:cゞ-'L! ' = 0.37N
.

に                     ηo 
n (n (Ev)/η(EC))で求められる。
ni ηo
It is determined by n (n (Ev)/η(EC)).

〔実施例〕〔Example〕

以下、本発明の一実施例について、第1図から第11図
を用いて説明する。第1図から第3図は、評価用のFE
Tセルの断面構造を示す、第1図は゛10導体基板1、
及び、i&板とは異なる極性の不純物を深くドープした
埋込み層2に、それぞれ異なる極性の不純物をドープし
て形成した、ソース3、及びドレインチを設け、ソース
及びドレイン間のチャネル部5上に、評価対象とする絶
縁膜6、及び、多結晶シリコンから成る浮i電極7を形
成し、更に、この上に、絶縁膜8、及び金属あるいは、
多結晶シリコン等からなるゲート電極9を設けた構造の
FETセルを示し1通常の紫外線消去形不揮発性メモリ
E P ROM (E 1ectrically an
dProgrammable Read 0nly M
emory)製造プロセスで作成できる。
An embodiment of the present invention will be described below with reference to FIGS. 1 to 11. Figures 1 to 3 are FE for evaluation.
Figure 1 shows the cross-sectional structure of the T cell.
A source 3 and a drain trench formed by doping impurities of different polarities are provided in the buried layer 2 deeply doped with impurities of a different polarity from those of the i&plate, and on the channel part 5 between the source and the drain, An insulating film 6 to be evaluated and a floating i-electrode 7 made of polycrystalline silicon are formed, and an insulating film 8 and a metal or
The figure shows an FET cell having a structure in which a gate electrode 9 made of polycrystalline silicon or the like is provided.
dProgrammable Read 0nly M
(emory) can be created through the manufacturing process.

第2図は、絶縁膜10上に非晶質シリコン11を堆積さ
せ、これを選択的に単結晶化し、この部分に所望の不純
物をドープして、ソース3.ドレイン4、及び、チャネ
ル領域5を形成し、チャネル領域5上に評価対象とする
Il!蒜膜6、及び半導体薄膜からなる浮ti電極7を
形成し、この上に絶縁膜8.及び、金属あるいは、多結
晶シリコン等から成るゲート電極9を設けた構造のFE
Tセルを示し、So I  (Silicon On 
 In5ulator)プロセスを用いて作製できる。
In FIG. 2, amorphous silicon 11 is deposited on an insulating film 10, selectively made into a single crystal, this portion is doped with a desired impurity, and a source 3. A drain 4 and a channel region 5 are formed, and Il! to be evaluated is formed on the channel region 5. A burlap film 6 and a floating Ti electrode 7 made of a semiconductor thin film are formed, and an insulating film 8 is formed thereon. and an FE with a structure provided with a gate electrode 9 made of metal, polycrystalline silicon, etc.
T cell is shown and So I (Silicon On
It can be manufactured using the In5lator process.

第3図は、半導体基板1、及び基板とは異なる極性の不
純物を深くドープした埋込み層2に、それぞれ異なる極
性の不純物をドープして形成したソース3、及びドレイ
ン4を設け、ソース及びドレイン間のチャネル部5上に
、評価対象とする異種絶林材からなる薄膜Ga、6bを
形成し、この薄膜の界面近傍及び界面を浮遊電極7とし
、この上に絶縁膜8、及び、金属8あるいは多結晶シリ
コン等から成るゲート電極9を設けた構造のFETセル
を示し、半導体基板1にシリコン、絶縁膜60.61に
それぞれ二酸化シリコン、窒化シリコンを用いたものは
、通常のM N OS (MetalNitride 
0xide Sem1conductor)型不揮発性
メモリの製造プロセスで作製できる。
FIG. 3 shows a semiconductor substrate 1 and a buried layer 2 deeply doped with impurities of a polarity different from that of the substrate, provided with a source 3 and a drain 4 each doped with impurities of different polarity, and between the source and drain. A thin film Ga, 6b made of a different type of extinct wood to be evaluated is formed on the channel portion 5 of the board, a floating electrode 7 is formed near and at the interface of this thin film, and an insulating film 8 and a metal 8 or An FET cell having a structure provided with a gate electrode 9 made of polycrystalline silicon or the like, in which silicon is used for the semiconductor substrate 1 and silicon dioxide and silicon nitride are used for the insulating films 60 and 61, respectively, is an ordinary M N OS (MetalNitride) cell.
It can be manufactured using a manufacturing process for non-volatile memory (Oxide Sem1 conductor) type non-volatile memory.

以下の評価用FETセルは、i!気時特性測定用探針と
電気的導通を得るために、基板又は埋込層2、電極1、
ソース3、ドレイン4、ゲート電極9から金属薄膜で配
線され、その先端に電極パッドが設けられている。
The following FET cells for evaluation are i! In order to obtain electrical continuity with the probe for measuring temporal characteristics, a substrate or embedded layer 2, an electrode 1,
A source 3, a drain 4, and a gate electrode 9 are interconnected using a metal thin film, and an electrode pad is provided at the tip of the interconnect.

第4図は、評価用FETセルのしきい電圧の測定、及び
、浮Ti電極あるいは絶縁膜界面、及びその近傍に、キ
ャリアを注入するための電気回路手段を示したブロック
ダイヤ図である。FETセル20の基板、又は埋込層の
電極パッド21、ソース電極パッド22、ドレイン電極
パッド23、ゲート電極パッド24に、探針を接触させ
、これらの電極に所定の波形の電圧を印加するための可
変電源31,32.及び矩形波発生器33と、FETセ
ルのしきい電圧を測定するための段階波あるいは三角波
発生器34、比較器35、基準電圧発生器36、しきい
電圧測定と浮遊電極にキャリア注入のための切替えスイ
ッチ37、これらを制御するマイクロコンピュータ38
、及び、遮光箱40から構成されている。しきい電圧の
測定は、切換えスイッチ37をR側に接続し、FETセ
ルの基板、及びドレイン電極に所定の電圧を加え、FE
Tセルのソース電流が規定の電流値に流れるまでゲート
電極に、段階波あるいは三角波を加える。ソース電流が
規定値に達した時、比較器35からの出力により、ゲー
ト電圧vclを測定し、各電極への印加電圧を0ボルト
とする。これらの制御は、マイクロコンピュータ38を
介して行う。
FIG. 4 is a block diagram showing electric circuit means for measuring the threshold voltage of the evaluation FET cell and for injecting carriers into the floating Ti electrode or the insulating film interface and its vicinity. In order to bring the probe into contact with the electrode pad 21, source electrode pad 22, drain electrode pad 23, and gate electrode pad 24 of the substrate of the FET cell 20 or the buried layer, and apply a voltage with a predetermined waveform to these electrodes. variable power supplies 31, 32. and a square wave generator 33, a step wave or triangular wave generator 34 for measuring the threshold voltage of the FET cell, a comparator 35, a reference voltage generator 36, for measuring the threshold voltage and injecting carriers into the floating electrode. Changeover switch 37, microcomputer 38 that controls these
, and a light shielding box 40. To measure the threshold voltage, connect the changeover switch 37 to the R side, apply a predetermined voltage to the substrate and drain electrode of the FET cell, and
A step wave or a triangular wave is applied to the gate electrode until the source current of the T cell flows to a specified current value. When the source current reaches a specified value, the gate voltage vcl is measured based on the output from the comparator 35, and the voltage applied to each electrode is set to 0 volts. These controls are performed via the microcomputer 38.

キャリア浮遊電極への注入は、切替えスイッチ37をW
側に接続し、FETセルの基板、ソース、ドレイン、及
びゲートに所定の電圧波形を印加して行う。これらの所
定の電圧波形の設定、及び、印加は、マイクロコンピュ
ータ38を介して行う。
To inject carriers into the floating electrode, turn the changeover switch 37 to W.
This is done by connecting the FET cell to the same side and applying a predetermined voltage waveform to the substrate, source, drain, and gate of the FET cell. Setting and application of these predetermined voltage waveforms are performed via the microcomputer 38.

第5図は、ウェハ30上の評価用FETセル20を、X
、Y、Z、3軸可動台41に取付け、光@42からのブ
ロードな波長の光を、分光器43により単色光に変え、
この単色光を試料表面に照射する。ウェハ上のセル20
の位置決めに必要な光学顕微鏡44と、単色光を一定時
間照射するためのシャッター45と、分光器からの高次
波を減衰させるフィルター46、及び、試料への照射光
量を一定にするためのモニタ用フォトセンサー47、光
源の電源48へのフォトセンサー出力の帰還増l11g
器49から情成されている。
FIG. 5 shows the evaluation FET cell 20 on the wafer 30
, Y, Z, attached to a 3-axis movable base 41, and converts the broad wavelength light from light @42 into monochromatic light using a spectrometer 43.
This monochromatic light is irradiated onto the sample surface. Cell 20 on wafer
an optical microscope 44 necessary for positioning, a shutter 45 for irradiating monochromatic light for a certain period of time, a filter 46 for attenuating high-order waves from the spectrometer, and a monitor for keeping the amount of light irradiated onto the sample constant. Increased feedback of photosensor output to photosensor 47 and light source power source 48 l11g
It is enlightened from vessel 49.

本発明の実施例として、試料に多結晶シリコンとシリコ
ン酸化膜で形成された、第1図に示す構造のnチャネル
型FETセルを用いて行った実験結果を、第6図〜第9
図に示す。
As an example of the present invention, the results of an experiment conducted using an n-channel FET cell formed of polycrystalline silicon and a silicon oxide film as a sample and having the structure shown in FIG. 1 are shown in FIGS. 6 to 9.
As shown in the figure.

第6図は、FETセルの浮遊電極にキャリアが注入され
てない場合のゲート電極からみた、しきい電圧■。とソ
ース電流I、の関係を示す、キャリアの注入は、基板及
びソース?!!極を接地し、ゲート及びドレイン電極に
FETを飽和動作させる所定の電圧波形を加える。この
時、ドレイン近傍の空乏層中の高電界で加速され、シリ
コンとシリコン酸化膜の障壁エネルギー以上のエネルギ
ーを得たホットキャリアが、酸化膜中に存在する電界で
、シリコン酸化膜中に注入され多結晶シリコンとシリコ
ン酸化膜界面及び近傍に形成されたトラップに捕獲され
る。この時のゲー1へ電極からみた、FETセルのしき
い電圧■6と、ソース電流の関係を図中の破線で示す、
この場合、捕獲されたキャリアは電子である。界面トラ
ップに電子が捕獲されてない時と、捕獲された時のFE
Tセルのしきい電圧をV。。+VGLとする。捕獲され
た状態で、セルの浮遊電極近傍に単色光をt時間照射し
た時のしきい電圧を■。(1)とする。
Figure 6 shows the threshold voltage ■ as seen from the gate electrode when carriers are not injected into the floating electrode of the FET cell. The carrier injection, which shows the relationship between the source current I and the substrate current I, is the substrate and source current I? ! ! The electrode is grounded, and a predetermined voltage waveform that causes the FET to operate in saturation is applied to the gate and drain electrodes. At this time, hot carriers that are accelerated by the high electric field in the depletion layer near the drain and have gained energy that exceeds the barrier energy between silicon and silicon oxide film are injected into the silicon oxide film by the electric field that exists in the oxide film. It is captured in traps formed at and near the interface between polycrystalline silicon and silicon oxide film. The relationship between the threshold voltage 6 of the FET cell and the source current as seen from the gate electrode 1 at this time is shown by the broken line in the figure.
In this case, the captured carriers are electrons. FE when no electron is captured in the interface trap and when it is captured
The threshold voltage of the T cell is V. . +VGL. In the captured state, the threshold voltage when monochromatic light is irradiated near the floating electrode of the cell for t hours is (■). (1).

第7図はFETセルのしきい電圧変化の初期値(V o
 □V 。o )との比、即ち(VG(t)−VG0)
 /(V a 1V 、、a )を単色光照射時間りど
の関係を示す。(VG(t)−VG0)/ (Vut−
VuJは、Lの指数関数で減衰している。この関係より
、(Va(t)−VG0) / (Vat−Vao)が
1 / e 40.37(eは自然対数の底)に減衰す
る迄の時定数τを求め、光子のキャリア励起確率ηを求
める。次に単色光の波長即ち、光子エネルギーEを変え
て、しきい電圧の減衰時定数τ(E)を測定し、光子の
キャリア励起確率η(E)を求める。
Figure 7 shows the initial value of the threshold voltage change (V o
□V. o), i.e. (VG(t)-VG0)
/(V a 1V,,a) represents the relationship between monochromatic light irradiation time. (VG(t)-VG0)/(Vut-
VuJ is attenuated by an exponential function of L. From this relationship, find the time constant τ until (Va(t)-VG0) / (Vat-Vao) decays to 1 / e 40.37 (e is the base of the natural logarithm), and calculate the photon carrier excitation probability η seek. Next, the wavelength of the monochromatic light, that is, the photon energy E is changed, the decay time constant τ(E) of the threshold voltage is measured, and the carrier excitation probability η(E) of the photon is determined.

第8図は光子のキャリア励起確率η(E)の光子−エネ
ルギーE依存性を示す。このときシリコン酸化膜の伝導
帯を基準として光子エネルギーEを考える。η(E)の
関数として近似式を求め、度n+t(E)のエネルギー
分布が求められる。
FIG. 8 shows the photon-energy E dependence of the photon carrier excitation probability η(E). At this time, consider the photon energy E with reference to the conduction band of the silicon oxide film. An approximate expression is obtained as a function of η(E), and the energy distribution of degrees n+t(E) is obtained.

第9図に多結晶シリコンとシリコン酸化膜の界面に形成
された電子トラップ準位密度の分布を示す。図中の破線
は、同一試料に高温放置試験をして、劣化させた時の電
子トラップ準位密度の分布を示す。熱ストレスによりシ
リコンのバンドギャップ中でトラップ準位密度は伝導帯
側で若干、減少し、中央から価電子帯にかけて増加して
いることが分かる。又、この時のトラップ密度も10”
/(1m”オーダーであり、シリコン基板とシリコン酸
化膜の界面準位密度の数値に近い、尚、PチャネルFE
Tセルを用い、ホールを多結晶シリコンとシリコン酸化
膜界面に形成されたトラップに捕獲させることにより、
ホールトラップ準位密度が求められることは言うまでも
ない。
FIG. 9 shows the distribution of electron trap level density formed at the interface between polycrystalline silicon and silicon oxide film. The broken line in the figure shows the distribution of electron trap level density when the same sample was subjected to a high temperature storage test and deteriorated. It can be seen that due to thermal stress, the trap level density in the band gap of silicon decreases slightly on the conduction band side, and increases from the center to the valence band. Also, the trap density at this time is also 10”
/(1m" order, which is close to the value of the interface state density between the silicon substrate and the silicon oxide film. Furthermore, P-channel FE
By using a T cell and trapping holes at the interface between polycrystalline silicon and silicon oxide film,
Needless to say, the hole trap level density is required.

上記、第1図から第3図に示した構造を有する評価用F
ETセルを、ウェハ上あるいはチップ上に設置した例を
第10図、及び第11図に示す。
Evaluation F with the structure shown in Figures 1 to 3 above.
Examples in which the ET cell is installed on a wafer or a chip are shown in FIGS. 10 and 11.

第10図は、評価用FETセル20を、ウェハ30のス
クライブエリア51、あるいはウェハ周辺上のチップ未
収得部分52に設置した例を示す。
FIG. 10 shows an example in which the evaluation FET cell 20 is installed in the scribe area 51 of the wafer 30 or in the uncollected chip portion 52 on the periphery of the wafer.

第11図は、集積回路チップ50上で、マスク合わせ用
ターゲラ)一部分53や、4J!、積回路を枯成する素
子、電極、配線のない空白部に評価用FETセル20を
設置した例を示す、DRAM、及び、SRAM等のMO
SメモリをはじめとしたLSIに於て、上記した評価用
FETセルをLSIウェハ、あるいはチップ上に設置し
、本発明の評価方法を用いることにより、半導体と絶g
膜の界面、及び、異なる絶縁材からなる絶縁膜界面を評
価できる。
FIG. 11 shows a portion 53 (for mask alignment) on an integrated circuit chip 50, 4J! MO of DRAM, SRAM, etc., which shows an example in which the evaluation FET cell 20 is installed in a blank area without elements, electrodes, or wiring that would dry up the product circuit.
In LSIs such as S memory, by installing the above evaluation FET cell on an LSI wafer or chip and using the evaluation method of the present invention, it is possible to
It is possible to evaluate the interface between films and the interface between insulating films made of different insulating materials.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、極めて微小面積で、微小容量の??J
t電極を有するFETセルを用いて、実際の半導体y5
造プロセスを経て製作された試料の、半導体と絶縁膜界
面の評価が正確にできる。現在のMOSメモリをはじめ
LSI製品の多結晶シリコンとシリコン酸化膜、異なる
二種の絶縁膜界面の評価ができ、シリコン酸化膜、及び
、多結晶シリコン薄膜、絶縁膜形成のプロセス条件の最
適化、素子の高性能化ができる。更に、将来のSOI技
術、新手導体材料、絶縁材料の選択、製造プロセス条件
のための評価法として活用できる。更に、本構造のFE
Tセルをウェハ上に分散配置しておくことにより、プロ
セスの評価、ウェハ内のばらつき評価、さらには、ロッ
ト間のばらつきがモニタでき、品質向上に寄与する。
According to the present invention, the ? ? J
Actual semiconductor y5 using FET cell with t electrode
It is possible to accurately evaluate the interface between the semiconductor and the insulating film of the sample manufactured through the manufacturing process. It is possible to evaluate the interface between two different types of insulating films, polycrystalline silicon and silicon oxide films, in current MOS memories and other LSI products, and to optimize process conditions for forming silicon oxide films, polycrystalline silicon thin films, and insulating films. It is possible to improve the performance of elements. Furthermore, it can be used as an evaluation method for future SOI technology, new conductor materials, insulation material selection, and manufacturing process conditions. Furthermore, the FE of this structure
By distributing T cells on a wafer, it is possible to evaluate processes, evaluate variations within a wafer, and monitor variations between lots, contributing to quality improvement.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は本発明の一実施例の浮遊電極を有す
るFETセルの縦断面図、第4図はFETセルのしきい
電圧測定と浮yIi電極へキャリア注入するための電気
回路を示すブロックダイヤ図、第5図はセルの浮遊電極
近傍へ一定光景で単色光を一定時間照射するための光学
系ブロックダイヤ図、第6図は浮遊電極のキャリアの有
無によるFETのソース電流とグー1−電圧の変化を示
す図、第7図はFETセルのしきい電圧の単色光照射時
の減衰特性を示す図、第8図は光子のキャリア励起確率
ηの光子エネルギーE依存性を示す図、第9図は電子ト
ラップ準位密度のエネルギー分布を示す図、第10図は
評価用FETセルのウェハ上への設置例を示す図、第1
1図は評価用FETセルのチップ上への12E1例を示
す図である。 1・・・シリコン基板、2・・埋込み層、3・・・ソー
ス、4・ ドレイン、5・・チャンネル領域、G−#A
縁層、7・轡l′M電極、8・・・絶縁膜、9・・・ゲ
ート電極9第 ] 図 策 ? 図 第 図 第 5 図 ゲートミル1 vr、 − 第 図 第g図 馬 図 亀子1半ルベー EIeVE− 1半ルキーー −雫 [eVl 第1O図 第 11図 zo−−−FETILl 4 −爪)テA〉7゛ハ0・ソト
1 to 3 are longitudinal cross-sectional views of an FET cell having a floating electrode according to an embodiment of the present invention, and FIG. 4 shows an electric circuit for measuring the threshold voltage of the FET cell and injecting carriers into the floating yIi electrode. Figure 5 is a block diagram of an optical system for irradiating monochromatic light with a fixed view for a fixed period of time near the floating electrode of the cell, and Figure 6 shows the FET source current and goo depending on the presence or absence of carriers in the floating electrode. 1 - A diagram showing the change in voltage, Figure 7 is a diagram showing the attenuation characteristic of the threshold voltage of the FET cell during monochromatic light irradiation, and Figure 8 is a diagram showing the dependence of photon carrier excitation probability η on photon energy E. , FIG. 9 is a diagram showing the energy distribution of electron trap level density, FIG. 10 is a diagram showing an example of installing an evaluation FET cell on a wafer, and FIG.
FIG. 1 is a diagram showing an example of 12E1 on a chip of an evaluation FET cell. 1... Silicon substrate, 2... Buried layer, 3... Source, 4. Drain, 5... Channel region, G-#A
Edge layer, 7・M electrode, 8... Insulating film, 9... Gate electrode 9th] Plan? Fig. Fig. Fig. 5 Gate mill 1 vr, - Fig. g Fig. Mazu Kameko 1 half rube EIeVE- 1 half ruki - Drop [eVl Fig. 1 O Fig. 11 zo---FETILl 4 - Claw) Te A〉7゛Ha0・Soto

Claims (1)

【特許請求の範囲】 1、半導体基板のソース、ドレインを有し、あるいは、
絶縁膜上に堆積させた非晶質シリコンを結晶化させた薄
膜中にソース、ドレインを有すると共に、ソース、ドレ
イン間の基板、あるいは薄膜上に、評価対象とする絶縁
膜と半導体からなる界面を有し、あるいは異なる二層の
絶縁膜界面を有し、この上を絶縁膜で被覆し、この上に
ゲート電極を設けた構造のMISFET(MetalI
nsulatorSemiconductorFiel
dEffectTransistor)において、上記
評価対象とする絶縁膜と半導体、あるいは、異なる二層
の絶縁膜からなる界面、及び、その近傍に形成されたト
ラップに、キャリア注入前後のゲート電極からみたFE
Tのしきい電圧V_G_0、及びV_G_1とするとき
、トラップにキャリア捕獲後に、この界面及び近傍に光
子エネルギーEの単色光を時間tだけ照射謝させ、キャ
リアを励起、消失させたときの該FETのしきい電圧V
_G(t)の変化より(V_G(t)−V_G_0)/
(V_G_1−V_G_0)の減衰時定数を求め、この
時定数より単色光の光子のキャリア励起確率ηを求め、
ηをEの関数として近似式を求め、これより、トラップ
準位密度のエネルギー分布、及びトラップ準位密度を求
めることを特徴とするMIS界面評価法。 2、評価用試料であるMISFETのしきい電圧の測定
手段、評価対象とする半導体と絶縁膜界面及び近傍、あ
るいは異なる絶縁膜界面及び近傍に形成されたトラップ
にキャリアを注入する手段、光量一定の単色光を試料表
面に一定時間照射する手段と、上記FETのしきい電圧
減衰の時定数から光子のキャリア励起確率ηを算出し、
上記界面及び近傍に形成されたトラップ準位密度と、そ
のエネルギー分布を求めるための演算手段とから構成さ
れたことを特徴とするMIS界面評価装置。 3、特許請求の範囲第1項において記述された構造の評
価用MISFETをウェハ上のチップ歩留りを低下させ
ない領域、例えば、ウェハの円周部、あるいは、スクラ
イブエリア等の領域に分散配置させ、半導体と絶縁膜、
あるいは、異なる絶縁膜の界面及び近傍に形成されたト
ラップ密度に関する情報を得ることを特徴とする半導体
製造方法。
[Claims] 1. Having a source and a drain of a semiconductor substrate, or
A thin film made by crystallizing amorphous silicon deposited on an insulating film has a source and a drain, and an interface between the insulating film and semiconductor to be evaluated is placed on the substrate or thin film between the source and drain. MISFET (Metal I
nsulatorSemiconductorFiel
dEffectTransistor), the FE observed from the gate electrode before and after carrier injection is applied to the interface between the insulating film and the semiconductor to be evaluated, or the interface between two different insulating films, and the trap formed in the vicinity thereof.
When the threshold voltages of T are V_G_0 and V_G_1, after capturing carriers in the trap, monochromatic light with photon energy E is irradiated on this interface and the vicinity for a time t to excite and extinguish the carriers. Threshold voltage V
From the change in _G(t), (V_G(t)-V_G_0)/
Find the decay time constant of (V_G_1-V_G_0), and from this time constant find the carrier excitation probability η of photons of monochromatic light,
An MIS interface evaluation method characterized in that an approximate expression is obtained using η as a function of E, and from this, an energy distribution of a trap level density and a trap level density are obtained. 2. Means for measuring the threshold voltage of the MISFET that is the evaluation sample, means for injecting carriers into traps formed at and near the interface between the semiconductor and insulating film to be evaluated, or at and near the interface of different insulating films, Calculating the photon carrier excitation probability η from the means for irradiating the sample surface with monochromatic light for a certain period of time and the time constant of the threshold voltage decay of the FET,
A MIS interface evaluation device comprising a calculation means for determining the trap level density formed at and near the interface and its energy distribution. 3. The evaluation MISFETs having the structure described in claim 1 are distributed and arranged in an area on the wafer that does not reduce the chip yield, for example, the circumference of the wafer or the scribe area, and the semiconductor and insulating film,
Alternatively, a semiconductor manufacturing method characterized by obtaining information regarding the density of traps formed at and near the interface of different insulating films.
JP26890089A 1989-10-18 1989-10-18 MIS interface evaluation method and apparatus Expired - Lifetime JP2609728B2 (en)

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JPH03132052A true JPH03132052A (en) 1991-06-05
JP2609728B2 JP2609728B2 (en) 1997-05-14

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075263A (en) * 1997-04-09 2000-06-13 Nec Corporation Method of evaluating the surface state and the interface trap of a semiconductor
JP2009239201A (en) * 2008-03-28 2009-10-15 Sanyo Electric Co Ltd Method of evaluating gate insulating film
JP2015122408A (en) * 2013-12-24 2015-07-02 三菱電機株式会社 Evaluation method, evaluation device, and method of manufacturing semiconductor device
JP2019087654A (en) * 2017-11-08 2019-06-06 グローバルウェーハズ・ジャパン株式会社 Interface level density measuring device
CN111855704A (en) * 2020-07-28 2020-10-30 哈尔滨工业大学 Method for detecting ionization damage sensitive part of bipolar transistor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075263A (en) * 1997-04-09 2000-06-13 Nec Corporation Method of evaluating the surface state and the interface trap of a semiconductor
JP2009239201A (en) * 2008-03-28 2009-10-15 Sanyo Electric Co Ltd Method of evaluating gate insulating film
JP2015122408A (en) * 2013-12-24 2015-07-02 三菱電機株式会社 Evaluation method, evaluation device, and method of manufacturing semiconductor device
JP2019087654A (en) * 2017-11-08 2019-06-06 グローバルウェーハズ・ジャパン株式会社 Interface level density measuring device
CN111855704A (en) * 2020-07-28 2020-10-30 哈尔滨工业大学 Method for detecting ionization damage sensitive part of bipolar transistor
CN111855704B (en) * 2020-07-28 2024-01-12 哈尔滨工业大学 Method for detecting ionization damage sensitive part of bipolar transistor

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