JP2609728B2 - MIS interface evaluation method and apparatus - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an evaluation method and an evaluation apparatus for an interface between a semiconductor and an insulating film, in particular, an interface between silicon and a silicon oxide film.

[Conventional technology]

Conventionally, as a method of evaluating the silicon-silicon oxide film interface, CV ((Capacitance-Voltag)
e)) There is a method, solid state electronics 13 (1970) pages 837 to 885 (Solid State Electr)
on. 13 (1970) pp 873-885).
DLTS (Deep Level Transient Spectroscop) is a method for determining the levels and densities of impurities and defects in semiconductors.
y)) method, and as an example of applying this method to the analysis of the interface state of a MOS structure, see Applied Physics, 18 (19
79) Pages 169 to 175 (App1. Phys. 18 (1979) pp169)
−175).

[Problems to be solved by the invention]

The CV method is a method of obtaining the interface state density of a silicon-silicon oxide film from a change in a depletion layer capacitance at a semiconductor junction when a bias voltage is changed by using a MOS capacitor. In the method and the photo-excited DLTS method, when a pulse voltage is applied to a MOS capacitor or when pulsed light is irradiated, the time constant of the transitional capacitance change of the junction caused by the thermal dissociation process of the carriers trapped in the interface state Are measured over a wide temperature range to determine interface states and interface state densities.In each case, a capacitance of several tens of PF or more is required to measure the change in minute capacitance. There are drawbacks such as the necessity of an element and low accuracy.

An object of the present invention is to provide a trap level and a trap level formed at the interface between silicon and a silicon oxide film, and further at the interface between a semiconductor and an insulating film, in the same area as a MOSFET which is a basic element constituting an actual LSI. An object of the present invention is to provide a method and an apparatus for accurately and easily determining a level density.

[Means for solving the problem]

In order to achieve the above object, in the gate insulating film between the gate electrode and the semiconductor substrate having the source and drain electrodes, the gate insulating film is insulated from the surroundings in the same area as the MOS / FET which is a constituent element of the LSI. An FET cell having a structure having a floating electrode made of a semiconductor material is used. Carriers are captured by traps formed at the interface between the floating electrode and the insulating film. When the threshold voltage of the FET cell viewed from the front and back of the gate electrode carrier in this trap is captured and V _G0, and V _G1, the difference V _G1 -V _G0 of both the amount of charge carriers trapped in the trap Is proportional to The vicinity of the interface between the floating electrode and the insulating film is irradiated with monochromatic light in the visible to ultraviolet region to excite the carriers trapped in the trap, and the threshold voltage V _G (t) of the FET cell is measured. Find the time constant τ of the characteristic. Next, the wavelength constant (photon energy E) of the monochromatic light is changed, and the time constant τ (E) is similarly obtained. The reciprocal of the time constant τ (E) corresponds to the ratio of the number of incident photons of monochromatic light to the number of excited carriers, that is, the quantum efficiency. By calculating the reciprocal 1 / τ (E) of this time constant as a function of the incident photon energy E, the interface state density formed at the interface between the floating electrode and the insulating film and its distribution function can be obtained.

To implement the above method, the above test sample, FET
Means for measuring the threshold voltage of the cell and injecting carriers,
A means for irradiating the sample with monochromatic light for a fixed time having a light source with a constant light amount and a variable wavelength, calculating a time constant of threshold voltage decay from the irradiation time and the measured threshold voltage, and calculating the time constant of the monochromatic light; An apparatus is used which is obtained as a function of the photon energy E and from which the energy distribution of the interface states and the interface state density are calculated. If measurement FET cells for evaluating this interface are set at a plurality of locations in the wafer, the distribution of the interface state between the semiconductor and the insulating film in the wafer can be monitored, and process evaluation, wafer lot-to-lot evaluation, Furthermore, it is possible to evaluate the quality of the new semiconductor and the insulating film material, and the combination thereof.

[Action]

Hereinafter, the principle of the method for measuring the interface state density between a semiconductor and an insulating film according to the present invention will be described.

The threshold voltages of the FET cell as viewed from the gate electrode in the state where carriers are not captured and in the state where carriers are captured in traps at the interface between the semiconductor and the insulating film are denoted by V _G0 and V _G1 , respectively. I do. In order to inject carriers into the trap, a saturation current flows between the source and the drain of the semiconductor substrate, and hot carriers generated in a high electric field portion near the drain are generated in the insulating film generated by the voltage applied to the gate electrode. There are a method of drawing by an electric field and a method of injecting as a tunnel current or a Fowler Nordheim tunnel current by an electric field existing in the insulating film between the gate electrode and the substrate. When the capacitance between the floating electrode and the gate electrode and C _2, the number of carriers trapped in the trap No, charge Qo is It is. Next, a monochromatic light having a wavelength λ (photon energy E) and a light amount P is irradiated to the vicinity of the interface between the floating electrode and the insulator for a time t to excite and trap carriers trapped in the trap. At this time, assuming that the threshold voltage of the FET cell viewed from the gate electrode is V _G (t), the number N (t) of carriers remaining in the trap and the charge Q (t) can be expressed by the following equation.

Photocurrent I that flows when excited from the trap during light irradiation
(T) is proportional to the electric field F _OX in the insulating film caused by the charge Q (t) remaining in the trap and the light amount P, so that the following differential equation is established.

Here, ε _I is the dielectric constant of the insulating film, and b is a constant. When the above differential equation is solved for Q (t), the following equation is established.

Therefore, _{Next, (V G (t) -V} G0) / (V G1 -V G0) , the time t
And the exponential relationship of the light amount P, Is the time constant of the decay. Here, the light amount P
The number n _P of incident photons per second when irradiating
It can be expressed by nstein relation, It is. Here, h is Planck's constant and C is the speed of light.

The accumulated number of photons n _P · τ incident during the time τ until N (t) / No decays to 1 / e ≒ 0.37 (e is the base of natural logarithm) and the carriers trapped in the trap are excited The ratio to the number of lost and lost carriers No-N (τ) is the photon carrier excitation probability η, which can be expressed by the following equation.

Therefore, the reciprocal of the time constant τ is proportional to the photon carrier excitation probability. In the energy level diagram of the interface trap caused by impurities and defects at the interface between the semiconductor and the insulating film, carriers trapped at a level lower than the photon energy E are excited, but are trapped at a level higher than E. No carriers are excited. Even if it is excited, the carrier trapped at a low level is excited and excited after the level is vacated. Therefore, the excitation probability of the carrier trapped above E is extremely high. Considered small. Therefore, assuming that the energy distribution function of the trap density existing at this interface is n _IT (E), when monochromatic light of photon energy E is irradiated, the density of the carriers still trapped in the trap is: Is It is. On the other hand, the number of carriers remaining in the trap is Therefore, when this equation is differentiated by the energy E and the value at t = τ is obtained, Becomes Therefore, assuming that η is a function of the photon energy E,
By performing a numerical analysis, an energy distribution function of the trap density is obtained. Further, the trap density N _1T existing at the interface between the insulating film and the semiconductor having a narrower energy band gap is represented by E _V and E _C , respectively, where the valence band and the conduction band of the semiconductor are E _V and E _C , respectively. Is required.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 11. Figures 1 to 3 show the evaluation FETs.
1 shows a cross-sectional structure of a cell. FIG. 1 shows a semiconductor substrate 1 and
A buried layer 2 deeply doped with an impurity having a polarity different from that of the substrate is provided with a source 3 and a drain chin formed by doping impurities of different polarities, respectively. Insulating film 6,
An FET cell having a structure in which a floating electrode 7 made of polycrystalline silicon is formed, and an insulating film 8 and a gate electrode 9 made of metal or polycrystalline silicon are further provided thereon is shown. Erasable nonvolatile memory EPROM (Ele
ctrically and programmable read only memory) can be created by the manufacturing process.

FIG. 2 shows that an amorphous silicon 11 is deposited on an insulating film 10, which is selectively monocrystallized, and a desired impurity is doped in this portion to form a source 3, a drain 4, and a channel region. 5, an insulating film 6 to be evaluated and a floating electrode 7 made of a semiconductor thin film are formed on the channel region 5, and an insulating film 8 and a gate electrode made of metal or polycrystalline silicon are formed thereon. 9 shows an FET cell having a structure provided with the semiconductor device 9 and can be manufactured using an SOI (Silicon On Insulator) process.

FIG. 3 shows a semiconductor substrate 1 and a buried layer 2 deeply doped with an impurity having a polarity different from that of the substrate, provided with a source 3 and a drain 4 formed by doping impurities of different polarities, respectively. The thin films 6a and 6b made of different kinds of insulating materials to be evaluated are formed on the channel portion 5 of the above.
An FET cell having a structure in which an insulating film 8 and a gate electrode 9 made of metal 8 or polycrystalline silicon or the like are provided thereon is shown. The semiconductor substrate 1 is made of silicon, and the insulating films 60 and 61 are made of silicon dioxide and silicon nitride, respectively. The one used is a normal
It can be manufactured by a manufacturing process of an MNOS (Metal Nitride Oxide Semiconductor) type nonvolatile memory.

The following evaluation FET cells are wired with a metal thin film from the substrate or the buried layer 2, the electrode 1, the source 3, the drain 4, and the gate electrode 9 in order to obtain electrical continuity with the probe for measuring electrical characteristics. An electrode pad is provided at the tip.

FIG. 4 is a block diagram showing an electric circuit means for measuring the threshold voltage of the evaluation FET cell, and injecting carriers into and around the floating electrode or the insulating film interface. FET cell 20 substrate or buried layer electrode pad 21, source electrode pad 22, drain electrode pad 2
3.Variable electrodes 31 and 3 for bringing a probe into contact with the gate electrode pad 24 and applying a voltage having a predetermined waveform to these electrodes.
2, and a square wave generator 33, a step wave or triangular wave generator 34 for measuring the threshold voltage of the FET cell, a comparator 35,
It comprises a reference voltage generator 36, a changeover switch 37 for threshold voltage measurement and carrier injection into the floating electrode, a microcomputer 38 for controlling these, and a light shielding box 40. To measure the threshold voltage, connect the changeover switch 37 to the R side, apply a predetermined voltage to the substrate and drain electrode of the FET cell, and apply a predetermined voltage to the gate electrode until the source current of the FET cell flows to the specified current value. Add a wave or triangle wave. When the source current reaches a predetermined value, the output from the comparator 35 measures the gate voltage V _G, the voltage applied to the electrodes to zero volts. These controls are controlled by the microcomputer 38
Done through. The injection into the carrier floating electrode is performed by connecting the changeover switch 37 to the W side and applying a predetermined voltage waveform to the substrate, source, drain, and gate of the FET cell.
The setting and application of these predetermined voltage waveforms are performed via the microcomputer 38.

FIG. 5 shows the evaluation FET cells 20 on the wafer 30 as X, Y, Z,
The light is attached to the three-axis movable table 41, and the light of the broad wavelength from the light source 42 is converted into monochromatic light by the spectroscope 43, and the monochromatic light is irradiated on the sample surface. An optical microscope 44 necessary for positioning the cell 20 on the wafer, a shutter 45 for irradiating monochromatic light for a certain time, a filter 46 for attenuating higher-order waves from the spectroscope, and a constant light amount for irradiating the sample And a feedback amplifier 49 for outputting the photosensor to a power source 48 of the light source.

As an example of the present invention, the results of an experiment performed using an n-channel FET cell having the structure shown in FIG. 1 formed of a polycrystalline silicon and a silicon oxide film on a sample are shown in FIGS.
Shown in the figure.

Figure 6 is viewed from the gate electrode in the case where the carrier in the floating electrode of the FET cells not injected, illustrating the relationship between threshold voltage V _G and the source current I _S. Injecting carriers, the substrate and the source electrode are grounded, and a predetermined voltage waveform for saturating the FET is applied to the gate and drain electrodes. At this time, hot carriers that are accelerated by a high electric field in the depletion layer near the drain and obtain energy equal to or higher than the barrier energy of silicon and the silicon oxide film are injected into the silicon oxide film by the electric field existing in the oxide film. The trap is formed at the interface between and around the polycrystalline silicon and the silicon oxide film. The threshold voltage V of the FET cell as viewed from the gate electrode at this time
The relationship between _G and the source current is indicated by a broken line in the figure. In this case, the captured carriers are electrons. The threshold voltages of the FET cell when electrons are not captured by the interface trap and when the electrons are captured are denoted by V _G0 and V _G1 . In the captured state, the threshold voltage when the monochromatic light is applied to the vicinity of the floating electrode of the cell for t hours is defined as V _G (t).

FIG. 7 shows the initial value (V _G1 −V
_G0) and the ratio of the show that is, the relationship between the monochromatic light irradiation time t a _{(V G (t) -V G0} ) / (V G1 -V G0). (V _G (t)-V _G0 )
/ (V _G1 −V _G0 ) is attenuated by an exponential function of t. From this _{relationship, (V G (t) -V} G0) / (V G1 -V G0) is 1 / e ≒ 0.
The time constant τ until the decay to 37 (e is the base of natural logarithm) is obtained, and the carrier excitation probability η of the photon is obtained. Next, the wavelength of monochromatic light, that is, the photon energy E is changed, and the decay time constant τ (E) of the threshold voltage is measured, and the carrier excitation probability η of the photon is determined.
(E) is obtained.

FIG. 8 shows the photon energy E dependency of the photon carrier excitation probability η (E). At this time, the photon energy E is considered based on the conduction band of the silicon oxide film. Find an approximate expression as a function of η (E), Accordingly, the energy distribution of the trap density n _IT (E) is obtained.

FIG. 9 shows the distribution of the electron trap level density formed at the interface between the polycrystalline silicon and the silicon oxide film. The broken line in the figure shows the distribution of electron trap state densities when the same sample was subjected to a high-temperature storage test and deteriorated. It can be seen that the trap level density slightly decreases on the conduction band side in the band gap of silicon due to thermal stress, and increases from the center to the valence band. Also, the trap density at this time was 10 ¹¹
/ cm ² order, which is close to the value of the interface state density between the silicon substrate and the silicon oxide film. It is needless to say that the hole trap level density is obtained by using a P-channel FET cell to trap holes in traps formed at the interface between the polycrystalline silicon and the silicon oxide film.

For evaluation, having the structure shown in FIGS. 1 to 3 above
FIGS. 10 and 11 show examples in which the FET cell is installed on a wafer or a chip.

FIG. 10 shows an example in which the evaluation FET cell 20 is stored in the scribe area 51 of the wafer 30 or in a portion where the chip has not been obtained on the wafer periphery.
An example of installation at 52 is shown.

FIG. 11 shows an example in which an evaluation FET cell 20 is placed on a mask alignment target portion 53 or a blank portion without elements, electrodes, and wirings constituting an integrated circuit on an integrated circuit chip 50. LSI including MOS memory such as DRAM and SRAM
In the above, the above-described evaluation FET cell was placed on an LSI wafer or chip, and the evaluation method of the present invention was used to evaluate the interface between the semiconductor and the insulating film and the interface between the insulating films made of different insulating materials. it can.

〔The invention's effect〕

According to the present invention, it is possible to accurately evaluate a semiconductor insulating film interface of a sample manufactured through an actual semiconductor manufacturing process using an FET cell having an extremely small area and a minute capacitance of a floating electrode. It is possible to evaluate the interface between two types of insulating films, polycrystalline silicon and silicon oxide film of LSI products including current MOS memory, and to optimize the process conditions for forming silicon oxide film, polycrystalline silicon thin film and insulating film. The performance of the device can be improved. In addition, it can be used as an evaluation method for future SOI technology, selection of new semiconductor materials and insulating materials, and manufacturing process conditions. Further, by distributing the FET cells of the present structure on the wafer, it is possible to evaluate the process, evaluate the variation in the wafer, and monitor the variation between lots, thereby contributing to quality improvement.

[Brief description of the drawings]

1 to 3 are longitudinal sectional views of an FET cell having a floating electrode according to an embodiment of the present invention, and FIG. 4 shows an electric circuit for measuring a threshold voltage of the FET cell and injecting carriers into the floating electrode. FIG. 5 is a block diagram of an optical system for irradiating a monochromatic light with a constant light amount to the vicinity of the floating electrode of the cell for a certain period of time, and FIG.
FIG. 7 shows a change in the source current and the gate voltage of T, and FIG.
FIG. 8 shows the attenuation characteristics of the threshold voltage of the ET cell when irradiated with monochromatic light, FIG. 8 shows the dependence of the carrier excitation probability η of photons on the photon energy E, and FIG. 9 shows the energy distribution of the electron trap level density. FIG. 10 is a view showing an example of installation of an evaluation FET cell on a wafer, and FIG. 11 is a view showing an example of installation of an evaluation FET cell on a chip. 1 ... silicon substrate, 2 ... buried layer, 3 ... source,
4 ... drain, 5 ... channel region, 6 ... insulating layer, 7 ... floating electrode, 8 ... insulating film, 9 ... gate electrode.

Claims (3)

(57) [Claims] A semiconductor substrate having a source and a drain, a source and a drain in a thin film obtained by crystallizing non-quality silicon deposited on an insulating film, and a substrate between the source and the drain, or On the thin film, having an interface composed of an insulating film and a semiconductor to be evaluated, or having two different insulating film interfaces, and covering this with an insulating film,
A MISFET (Metal Insu
In the field effect transistor (FET), the interface between the insulating film to be evaluated and the semiconductor, or the interface formed of two different insulating films, and the trap formed in the vicinity of the interface, the FET viewed from the gate electrode before and after the carrier injection. When the threshold voltages V _G0 and V _G1 are set, after trapping carriers in the trap, the interface and the vicinity thereof are irradiated with monochromatic light of photon energy E for a time t, and the FETs when the carriers are excited or eliminated are excited. Determination of the decay time constant of the threshold voltage than the change in _{V G (t) (V G} (t) -V G0) / (V G1 -V G0), the carrier excitation probability of photons of monochromatic light from the time constant η MIS interface evaluation method, wherein an approximate expression is obtained by using η as a function of E, and the energy distribution of trap order density and the trap level density are obtained therefrom. 2. A means for measuring a threshold voltage of a MISFET as an evaluation sample, an interface between a semiconductor to be evaluated and an insulating film and its vicinity,
Alternatively, means for injecting carriers into traps formed at and near different insulating film interfaces, means for irradiating the sample surface with a constant amount of monochromatic light for a fixed time, and carrier excitation of photons based on the time constant of the threshold voltage decay of the FET. Calculate the probability η,
An MIS interface evaluation device, comprising: a trap level density formed at the interface and the vicinity thereof; and arithmetic means for obtaining an energy distribution thereof. 3. The MISFET for evaluation of the structure described in claim 1 is dispersedly arranged in a region on the wafer which does not lower the chip yield, for example, a circumferential portion of the wafer or a scribe area. And obtaining information on the density of traps formed at and near the interface between the semiconductor and the insulating film or between different insulating films.