JPH0313086A - Decoder - Google Patents

Abstract

PURPOSE:To eliminate oscillation of a decoded value completely by discriminating a specific pattern string of an input code and correcting an output of a decoding means. CONSTITUTION:A code inputted to an input terminal 40 is applied to a decoding circuit 49 and a discrimination circuit 50. The discrimination circuit 50 uses flip-flops 61-66 to latch the inputted code for each clock sequentially and supplies codes y1, yi+1, yi+2, yi+3, yi+4, yi+5 to a comparator circuit 67. Since code string of -1, 1, -1, 1, -1 is formed at a picture flat portion and the comparator circuit 67 outputs '1' when a coded representative is -1 with respect to the code string as above and outputs '0' in the case of other code string. An output signal of a switch 76 is -xi-1 when a discrimination signal is logical 1 and -xi when the discrimination signal is logical 0. Thus, the signal at an output terminal 78 of a correction circuit 52 is a signal string of -xi-1, -xi-1, -xi+1, -xi+1, -xi+2, -x1+3,... at the picture flat portion and it is outputted from an output terminal 54 as a corrected decoding value. When a representative value of a difference 0 is 1, a level of a decoded value 101 is corrected to 1000 and when representative value of a difference 0 is -1, a level of a decoded value 99 is corrected to 100 to reduce shot noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding device in a digital transmission device for audio and image signals.

[Prior Art] When digitally transmitting information such as images and audio, various encoding methods have been proposed as a method of narrowing the transmission band. For example, a predictive coding method (DPCM) that aims to compress the amount of information by using the correlation between adjacent sample values.
There is. In DPCM, a predicted value for a sample value to be encoded is obtained from a decoded value of a transmission value, and a difference value (prediction error) between the predicted value and the sample value is quantized and transmitted. There are various predictive encoding methods depending on the method of generating predicted values, and Fig. 6A shows an encoding device for the simplest previous value predictive encoding method (predictive encoding method that uses the previous decoded value as the predicted value). FIG. 6B shows a basic configuration block diagram of the decoding device.

In FIG. 6A, the subtracter 12 subtracts the predicted value (in this embodiment, the previous decoded value X+-t) from the sample value X1 input to the input terminal 10, and outputs a difference value e.

The quantizer 14 quantizes the difference value e1 and outputs an encoded code y1, and this encoded code y1 is sent from the output terminal 16 to the transmission path. The encoded code Yl is also applied to the inverse quantizer 18. The inverse quantizer 18 converts the encoded code y1 into a differential value (ffi representation). By adding the predicted value to this quantized representative value in the adder 20, the input sample value can be restored. Since the manually sampled value contains a quantization error, there is a possibility that it exceeds the range of the original manually sampled value.Therefore, the limiter 22 limits the range in amplitude.The output of the limiter 22 becomes the locally decoded value X,
is applied to the D flip-flop (predictor) 24. Since the previous value decoded value is used as the predicted value, the predictor becomes a D flip-flop. The D flip-flop 24 applies the locally decoded value X as a predicted value to the subtracter 12 and the adder 20 in the next clock cycle. A block 25 surrounded by a broken line constitutes a local decoder.

FIG. 6B is a block diagram of a decoding device corresponding to the encoding device of FIG. 6A, and is structurally the same as the local decoder 25 of FIG. 6A. The encoded code y1 inputted to the input terminal 26 is converted into a quantized representative value by the inverse quantizer 28, and a predicted value is added by the adder 30. Limiter 32 limits the amplitude of the output of adder 30. Limiter 3
The output X of 2 is output from the output terminal 34 as a decoded value. This decoded value is delayed by one cycle clock by D flip-flop 36 and applied to adder 30 as a predicted value.

Generally, the probability distribution of the difference value between the predicted value and the input sample value is biased toward the small value part, so the quantization step is finer where the difference is small, and coarser (nonlinear quantization) where the difference is large. This allows the amount of information to be compressed.

[Problems to be Solved by the Invention] As one of the nonlinear quantization or linear quantization characteristics used in DPCM, the m1driser type shown in FIG. 4(a) and the m1dtread type shown in FIG. 4(b) are known. . m
Since the 1driser type does not have an O level, it can take 2″ steps, and the m1d with an O level
It has the characteristic that it can take one more step than the tread type.

However, in the m1driser type quantization characteristic, the sample value
There is a drawback that when the encoded code y1 continues at the same level as in a flat part of the image, the decoded value X+, which is the same as the encoded code y1, oscillates. For example, input sample value X,
Suppose that continues at a level of "100" in binary representation.

At this time, if the difference value O corresponds to the representative value 1, the decoded value x1 will be "101", the representative value at i+1 cycle is -1, the decoded value is "100", i÷2 cycles Then, the representative value is 1, the decoded value Xl+2 is "10F,"
As shown in FIG. 5(a), the level of the flat portion oscillates. In addition, when the difference value 0 corresponds to the representative value -1, the decoded value is 100,99 as shown in FIG. 5(C).
．． 100,99,100. ...and it vibrates. Such vibrations become granular noise and degrade image quality.

It is an object of the present invention to provide a decoding device that eliminates such drawbacks.

[Means for Solving the Problems] A decoding device according to the present invention includes a decoding means for decoding a manually encoded code, a determining means for determining a specific pattern sequence of the input encoded code, and a decoding device for decoding a manually encoded code, a determining means for determining a specific pattern sequence of the input encoded code, and a decoding device for decoding a manually encoded code. It is characterized by comprising a correction means for correcting the output of the decoding means according to the determination result of the means.

[Operation] The determination means described above can detect a specific pattern sequence corresponding to, for example, a flat portion of the image. Then, based on the determination result of the determination means, the correction means performs a correction to eliminate the vibration of the decoded value of the flat part of the image. Thereby, the oscillation of the decoded value in the conventional example can be completely eliminated.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. 4
0 is an input terminal for an encoded code by an encoding circuit as shown in FIG. 6A, 42 is an inverse quantizer, 44 is an adder, 46
is a limiter, and 48 is a D flip-flop. circuit 4
The decoding circuit 49 consisting of 2, 44, 46, and 48
It has the same configuration as Figure B. 50 is a determination circuit that determines a flat part of an image; 52 is a correction circuit that corrects the decoded value by the decoding circuit 59 (specifically, the output of the limiter 46) based on the determination result of the determination circuit 50; and 54 is a final correction circuit. This is an output terminal for decoded values.

An example of the configuration of the determination circuit 50 is shown in FIG. 60 is an input terminal of the determination circuit 50, which is connected to the input terminal 40 in FIG. 61, 62, 63, 64, 65, and 66 are flip-flops; 67 is a comparison circuit for the outputs of the flip-flops 61 to 66; and 68 is an output terminal of a determination circuit 68.

An example of the configuration of the correction circuit 52 is shown in FIG. 70 is an input terminal to which the output of the decoding circuit 49 is input; 72 is a delay circuit; 7
4 is a D flip-flop for delaying the output of the delay circuit 72 by one clock; 76 is a switch that is switched by a determination signal from the determination circuit 50; 78 is an output terminal;
o is an input terminal for a determination signal.

The operation will be explained below. The encoded code input to the input terminal 40 is applied to a decoding circuit 49 and a determination circuit 50. The decoding circuit 49 decodes the encoded code in the same manner as in FIG. 6B. In the determination circuit 50, flip-flops 61 to 66 sequentially latch the input encoded codes for each clock, and send the encoded codes Y+, ! to the comparison circuit 67. /l◆
+, YI+x, yI+s・y++a・y. , supply. Comparison circuit 67 compares these and outputs a determination signal. That is, when the representative value of the difference value O is 1, in the flat part of the image, 1. -1゜1 -1 1. -1 encoded code string, the comparison circuit 67 outputs '1' when the quantization representative value is 1 for such a code string, and always outputs '0' for other code strings. Output.If the representative value of the difference value 0 is -1, the flat part of the image is -1,1°-
Since the encoded code string is 1, 1, -1, 1, the comparator circuit 67 calculates that the quantization representative value is - for such a code string.
When it is 1, it outputs “1”, and for other code strings, it outputs “1”.
The output (judgment signal) of the comparison circuit 67 is applied to the correction circuit 52 via the output terminal 68.

In the correction circuit 52, the output of the decoding circuit 49 is sent to the delay circuit 7.
2, the signal is delayed by a time corresponding to the processing time in the determination circuit 50, and the delayed output is applied to the D flip-flop 74 and the b contact of the switch 76. The signal delayed by one clock in the D flip-flop 74 is applied to the a contact point of the switch 76. The switch 76 is connected to the a contact when the determination signal from the determination circuit 50 is "1", and is connected to "0".
When , connect to b contact. That is, when the determination signal is "1", the output side signal of the switch 76 is X, -1,
When the determination signal is "0", it becomes Xl. Therefore, in the flat part of the image, the signal at the output terminal 78 of the correction circuit 52 is %
X+-+, X+-+, X++l+X+++, X++a+
A signal sequence of X++m, "' is generated, and these are output from the output terminal 54 as corrected decoded values.

In this way, by correcting the decoded value in the flat part of the image, when the representative value of the difference value O is 1, as shown in FIG. 5(b)
As shown in Figure 5 (d), when the level of the decoded value lot is corrected to 100 and the representative value of the difference value O is -1,
), the level of the decoded value 99 is corrected to 100, and granular noise can be reduced.

In the above embodiment, the encoded code for 6 pixels was used to determine the flat portion of the image, but in the above example as well, the flat portion can be determined using the continuous encoded code for 3 or more pixels. That is, in the present invention, the number of encoding codes for determining an image flat part is not limited to the above embodiment.

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, even when m1driser type quantization characteristics are used in a DPCM encoding device, grainy noise in flat areas of an image can be reduced and high quality can be achieved. You can get a good image.

[Brief explanation of the drawing]

1 is a configuration block diagram of an embodiment of the present invention, FIG. 2 is an example of the circuit configuration of the determination circuit 50 in FIG. 1, FIG. 3 is an example of the circuit configuration of the correction circuit 52 in FIG. 1, and FIG. l) Characteristic diagram of quantization characteristics of PCM encoding, Figure 5 is a diagram of conventional decoded values in the flat part of the image and correction results according to this embodiment, Figure gA is a basic configuration block diagram of the DPCM encoding device, FIG. 6B is a block diagram of a conventional decoding device. 40: Encoding code input terminal 42: Inverse quantization circuit 4
4: Adder 46: Limiter 48: D flip-flop 50: Judgment circuit 52: Correction circuit 54: Output terminal

Claims (1)

[Claims] a decoding means for decoding an input encoded code; a determining means for determining a specific pattern sequence of the input encoded code; and a correcting means for correcting the output of the decoding means according to the determination result of the determining means. A decoding device comprising: