JPS6150424A - Digital modulator - Google Patents

Abstract

PURPOSE:To attain A/D conversion with low noise even at a low sampling frequency by changing over a time constant of a demodulation integration device of a delta modulator quickly in response to the state of an analog input signal. CONSTITUTION:A differentiation circuit 13 detects a steep change in an analog input signal 1 in addition to the loop operation and when the change is caused steeply, an output signal of a voltage comparator 14 goes to a high level and when the signal is dropped suddenly, an output signal of the voltage comparator 15 goes to a high level and an output signal of an OR gate 16 is a detection output signal going to a high level only when a high frequency component analog input signal 1 is inputted. The signal is sampled by a D flip-flop 17 to close a switch 12, and a resistor 11 is inserted in parallel with a resistor 8 to decrease the time constant of the integration device 7 so as to suppress overload noise. On the other hand, when the analog input signal 1 is within a normal frequency range, the time constant of the integration device 7 is brought into a comparatively large time constant decided by the resistor 8 and a capacitor 9 to suppress granular noise.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a delta modulation device, which is a type of analog/digital converter (hereinafter referred to as an A/D converter) that modulates an analog signal into a binary digital signal. It is something.

Conventional configuration and its problems Delta modulation devices are known as A/D converters that can be constructed at low cost, and have recently been put into practical use as integrated circuits due to advances in high-speed operation technology for circuit elements. has been made into

A basic delta modulation device will be described below with reference to the drawings.

FIG. 1 shows its circuit configuration, and FIG. 2 shows waveform diagrams of its various parts. First, in FIG. 1, 1 is an analog signal input signal, 2 is a delta modulation output signal, 3 is a sampling clock signal, 4 is a voltage comparator, 6 is an output signal of voltage comparator 4, and 6 is a D flip-flop. , 7 is an integrator, which is composed of a resistor 8 and a cano (jitter 9). 10 is a signal obtained by integrating the delta modulated output signal 2 by the integrator 7 and demodulating it into an analog signal.

Regarding the delta modulation device configured as above, the second
The operation will be explained with reference to the waveform diagram in the figure.

The dotted line in the waveform diagram a is the analog input signal 1, and the solid line is the demodulated output signal 10. b is the sampling clock signal 3 and C is the waveform of the delta modulated output signal 2.

Now, assuming that the input of the voltage comparator 4 is as shown in waveform diagram a, the analog input signal 1 is higher than the demodulated output signal 1.
During the period where the dotted line waveform is higher than the solid line, the output signal 5 of the voltage comparator 4 is at a high level.

In the opposite case, the level is low. This output signal 5 is then sampled by a D flip-flop 6.

That is, when plotting the waveform of the sampling clock 3, the output signal 6 of the voltage comparator 4 is detected only at the moment the clock rises, and the output signal 2 of the D flip-flop 6 follows the detected state until the next clock rises. Hold.

In the case of the example of the waveform diagram, it would be as shown in C. This is the v-modulated output signal 2 of the analog input signal 1 (dotted line in waveform diagram a). This is multiplied by integrator 7.
When the delta modulation output signal 2 is at a high level, the capacitor 9 is charged via the resistor 8, so the input signal 1o of the voltage comparator 4 rises, and conversely, when the delta modulation output signal 2 is at a low level, it falls. The solid line in the waveform diagram B shows the demodulated output signal 1o plotted from the waveform diagram C assuming that the voltage change range of the analog input signal 1 is sufficiently small and the charging/discharging characteristics of the resistor 8 and capacitor 9 can be approximated by a straight line.

The delta modulator performs digital/digital conversion of the analog input signal 1 into a delta modulated output signal 2 (1-bit quantized digital signal) by such a loop operation.

On the other hand, in order to perform D/M conversion on this signal, the delta modulation output signal 2 may be passed through an integrator equivalent to the integrator 7 and re-converted.

The waveform of the D/MU conversion output signal obtained at that time is equal to that shown by the solid line B in the waveform diagram.

Looking at this waveform diagram a, there is a large error due to Mu/D conversion and D/Human conversion, but if the clock signal 30 frequency is set sufficiently high relative to the maximum frequency of the analog input signal, the error can be reduced. Since the frequency of the clock signal 3 cannot be made infinite, error noise under the following two contradictory conditions becomes a problem. One of them is an error when the analog signal has a low frequency such as direct current. The delta modulated output signal 2 repeatedly goes from high level to low level every sample interval. Since this is smoothed through the integrator 7, it is necessary to increase the integration time constant in order to reduce the error.

Another problem and serious error is the error when the voltage of the analog input signal 1 changes rapidly.

In this case, the delta modulated output signal will be either high or low level continuously. At this time, if the time constant of the integral booklet is small, the demodulated output signal 1o can also follow. That is, in this case, the smaller the integration time constant, the better.

In general K, the former is called granular noise and the latter is called overload noise, but to improve it, increase the time constant of the integrator 7 for the former, and increase the time constant for the latter. There is a way to switch to make it smaller.

A delta modulator applying this method is called an adaptive delta modulator. For example, there is a conventional method in which the information of n consecutive sample sections of the delta modulated output is stored in n D flip-flops, and the time constant of the integrator 7 is changed according to the information.

However, if the analog input signal 1 has a relatively low frequency such as an audio signal, the frequency of the sampling clock signal 3 can be made sufficiently large, for example, by about 100 times, so there is no problem even if n=4 in adaptive delta modulation. There is no. However, in the case of an analog input signal of several M)Iz, it is difficult to increase the clock frequency to several hundred MHz when using ordinary logic elements. If the clock frequency is about 10 times the highest frequency of the input, the adaptive delta modulation method described above is unreasonable. This is because large errors occur while examining past information. Therefore, the conventional D/D modulator has difficulty as a M/D converter for high frequency analog input signals.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a delta modulation device that can be used even for high-frequency input signals such as television video signals.

Structure of the Invention A delta modulation device according to the present invention includes: an integrator that demodulates a delta modulation output signal into an analog signal; a first voltage comparator that compares an analog input signal with its demodulated output signal; a flip-flop that samples the output signal and outputs a delta modulation signal; a circuit that differentiates the analog input signal; a second voltage comparator that compares the differentiated output signal with a constant voltage; A second flip-flop samples at the same period as the flip-flop.
It is equipped with a flop and a circuit that switches the time constant of the integrator based on the output of the flop, and immediately switches off the time constant of the integrator when an analog input signal that causes a large error in Mu/D conversion due to differentiation is detected. In other words, it is possible to perform Mu/D conversion with small error noise even at a sampling frequency lower than K.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a circuit configuration diagram of a delta modulation device in an embodiment of the present invention.

In addition, in the figure, the parts 1 to 1o correspond to the parts with the same numbers in FIG. 11 is a resistor for switching the time constant of the integrator 7;
2 is a time constant switching switch, 13 is a differentiating circuit for differentiating the analog input signal 1, and 14°15 is the differentiating circuit 1.
3 is a circuit for comparing the output signal with a constant voltage, 16 is an OR gate, and 17 is a second D flip-flop whose clock signal is the same clock signal 3 as the D flip-flop 6. The output signal of D flip-flop 17 controls switch 12 while being output from terminal 18.

The operation of the delta modulation device configured as described above will be described below. 1 to 10 are the same as described in FIG. 1, so their explanation will be omitted.

Apart from this loop operation, the differentiating circuit 13 detects a sharp change in the analog input signal 1. When the analog input signal 1 rises steeply, the output signal of the voltage comparator 14 goes to a high level, and when it falls sharply, the output signal of the voltage comparator 15 goes to a high level. For the frequency component analog input signal 1, the output signals of the voltage comparators 14 and 15 are both at a low level. Therefore, the output signal of the OR gate 16 becomes a detection output signal that becomes high level only when the high frequency component analog input signal 1 is input. This is sampled by the D flip-flop 17 and the switch 12 is controlled. That is, the analog input signal IV
c When there is a high frequency component, the switch 12 is closed and a resistor 11 is inserted in parallel with the resistor 8 to reduce the time constant of the integrator 7 and suppress overload noise.

On the other hand, when the analog input signal 1 is within the normal frequency range, the time constant of the integrator A is set to a relatively large time constant determined by the resistor 8 and capacitor 9 to suppress granular noise.

Further, if the output signal of the differentiating circuit 13 is compared with multiple values using more voltage comparators, and the integration time constant is changed in accordance with the comparison, even more detailed compensation can be achieved.

It is also possible to consider a method in which the integrator 7 is configured to charge and discharge a capacitor with a constant current, and the magnitude of the constant current is switched to change the time constant.

Note that this delta modulation device has a delta modulation output signal 2 and a time constant switching output signal 18 for the analog input signal 1.
Although there are two output signals, there are multiple analog input signals that are input in parallel and have a correlation with each other (for example, R, G of a television video signal).

In the case where the same number of delta modulators are installed in parallel to process the same number of delta modulators, the time constant switching detectors 13 to 18 are provided only for one analog input signal, and the time constant switching output signal is used to process the other analog input signals. By switching the integral time constant of the delta modulator at the same time, the circuit can be simplified and the number of output signal lines can be reduced.

Effects of the Invention As described above, according to the present invention, the time constant of the integrator for demodulation of the delta modulation device can be quickly switched according to the state of the analog input signal, thereby achieving low noise even at a low sampling frequency. This provides the excellent effect of being able to perform MU/D conversion.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional delta modulator, and Figure 2 is a circuit diagram of a conventional delta modulator.
FIG. 3 is a waveform diagram of each part in an example of the operation of the circuit shown in the figure, and FIG. 3 is a circuit diagram of a delta modulation device in an embodiment of the present invention. 1... Analog signal input terminal, 2... Demodulation signal output terminal, 3... Sampling clock signal input terminal, 4, 14.16...・Voltage comparator, 6, 17...D flip fist flop, 7...
...integrator, 13...differentiation circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2rlA-1

Claims (1)

[Claims] an integrator that demodulates a delta modulated output signal into an analog signal; a first voltage comparator that compares the analog input signal with its demodulated output signal; and a binary signal output from the voltage comparator that samples the binary signal and performs delta modulation. The first flip that outputs the signal
a flop, a circuit for differentiating the analog input signal,
a second voltage comparator that compares the differential output signal with a constant voltage; and a second flip-flop that samples the output signal of the second voltage comparator at the same period as the first flip-flop. and a circuit that switches the time constant of the integrator based on the output of the second flip-flop.