JPH0313088A - Decoder - Google Patents

Abstract

PURPOSE:To reduce edge business by setting a quantization representative value of a current frame to a value between the quantization representative value of the current frame and a preceding frame when the quantization representative value is adjacent to each other between frames. CONSTITUTION:When an adjacent representative value discrimination circuit 44 represents a quantization representative value in which a DPCM code Y1 of a current frame and a DPCM code Y1' of the preceding frame are adjacent to each other, the circuit 44 outputs logical H and in other cases, the circuit 44 outputs an L level discrimination signal d1. A switch 50 is turned to the position of a contact (a) when the discrimination signal d1 is logical L and the switch 50 is turned to the position of a contact (b) when the discrimination signal d1 is logical H. Thus, when the DPCM code of the current frame and the DPCM code of the preceding frame represent adjacent quantization representative values, a decoded value taking its border as the quantization representative value is outputted and the same decoding as that of a conventional system is outputted in other cases. Thus, the edge business is considerably reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a decoding device, and more specifically to a decoding device in a digital image data transmission system.

[Prior Art] When digitally transmitting information such as images and audio, various types of encoding are applied to reduce the amount of transmitted information. One of the encoding methods is the predictive encoding method (hereinafter referred to as DPCM), which compresses information 1 by using the correlation between adjacent sample values.
). In DPCM, a predicted value for a sample value to be encoded is obtained from a decoded value that has already been transmitted, and a difference value (prediction error) between this predicted value and the sample value is quantized and transmitted.

There are various predictive encoding methods depending on the method of generating predicted values. FIG. 4 shows a block diagram of the configuration of an encoding apparatus using the simplest previous value predictive encoding method (predictive encoding method using the immediately previous decoded value as a predicted value).

In addition, in the following, the difference value is expressed as e for the sample value X-2.
5. The DPCM code is expressed as Yl, the representative value based on the DPCM:l-code Y1 as Q(at), the decoded value as XI, and the predicted value as X with the subscript p added.

In FIG. 4, a subtracter 12 subtracts a predicted value X1 . (In this example, the previous decoded value)
is subtracted, and the difference value e1 is output. The quantizer 14 quantizes the difference value el and outputs a quantization code Y, and this quantization code Y is sent from the output terminal 16 to the transmission path. The DPCIJ code Y is also applied to the quantization representative value generation circuit 18. The quantization representative value generation circuit 18 is D
The PCM code Y is converted into a quantized representative value Q (eI). By adding the predicted value to this quantized representative value Q(e,) using the adder 20, the manually sampled value can be restored. Since the restored input sample values include quantization errors, they may exceed the range of the original input sample values. Therefore, the limiter 22 limits the range in amplitude. The output of the limiter 22 is the locally decoded value X1, and the D flip-flop (predictor)
24. In this example, since the previous decoded value is used as the predicted value, the predictor is a D flip-flop. D
Flip-flop 24 applies the locally decoded value as a predicted value to subtracter 12 and adder 20 in the next clock cycle.

Generally, the probability distribution of the difference value between the predicted value and the input sample value is biased towards the small value part, and the amount of information can be reduced by making the quantization step finer where the difference is small and coarser where the difference is large. Can be compressed.

FIG. 5 shows a configuration block diagram of a decoding device corresponding to the encoding device of FIG. 4. DPCM input to input terminal 26
The code Yl is converted into a quantized representative value Q(e,) by the quantized representative value generation circuit 18, and a predicted value is added by the adder 30. The limiter 32 limits the amplitude of the output of the adder 30. The output XI of the limiter 32 is outputted from the output terminal 34 as a decoded value. This decoded value is delayed by one cycle clock by the D flip-flop 36, and the predicted value X1. The signal is then applied to the adder 30.

[Problems to be Solved by the Invention] In the conventional example shown in FIG. The range is (2n-1) levels from -n+1 to n-1, which is about twice the input sample value. As a result, when the compression ratio is increased and the quantization characteristic is set to the nonlinear characteristic described above (the quantization step becomes finer when the difference value is near O, and the quantization step becomes coarser as the difference value moves away from 0), , the maximum absolute value of the quantization error (difference between the difference values before and after quantization) in a portion far from the predicted value becomes a very large value.

This causes image quality deterioration (
This was a major factor in the growth of

Therefore, it is an object of the present invention to provide a decoding device that eliminates such drawbacks.

[Means for Solving the Problems] A decoding device according to the present invention includes a delay means for delaying an encoded code by a frame, and a determination means for determining whether quantization representative values are adjacent values between frames. The quantization representative value of the current frame is set to a value between the quantization representative values of the current frame and the previous frame when the quantization representative values are adjacent to each other between frames.

[Operation] By the above means, the difference or change in the quantization representative value between frames can be reduced, and therefore edge business can be reduced.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. 4
0 is a DPCM code input terminal, 41 is a representative value generation circuit, 42 is a frame memory, 43 is a quantization boundary value generation circuit, 44 is an adjacent representative value determination circuit, 45.56 is an adder, 4
7.49 is a limiter, 48 is a D flip-flop, 50
51 is a switch for selecting a decoded value, and 51 is an output terminal for the decoded value.

DPCMPCM code input to input terminal 40
The representative value generation circuit 41 generates a difference value (m representative value Q(e
, )), and the adder 45 adds the predicted value X→ to this. The limiter 47 limits the amplitude of the output of the adder 45, and the output of the limiter 47 is sent to the switch 50 as the decoded value x1.
is applied to the a contact of the On the other hand, the DPCM code Y is also applied to the frame memory 42, the quantization boundary value generation circuit 43, and the adjacent representative value determination circuit 44. frame memory 4
2, the signal is delayed by one Y frame of the DPCMPCM code and applied to the quantization boundary value generation circuit 43 and the adjacent representative value determination circuit 44.

The quantization boundary value generation circuit 43 generates a boundary value for quantization when the quantization representative values indicated by the DPCM code Y+ of the current frame and the DPCM code of the previous frame are adjacent values, and otherwise generates a boundary value for quantization. A quantization representative value indicated by the DPCM code of the current frame is generated. The adder 46 adds the predicted value X8 . The limiter 49 limits the amplitude of the output of the adder 46. The output of the limiter 49 is applied to the b contact of the switch 50 as a corrected decoded value XI'.

The adjacent representative value determination circuit 44 determines the DPCMPCM of the current frame.
If the DPCM code Yl° of the code Y frame indicates a representative quantization value that is adjacent to each other, a determination signal d of "H" is output, and otherwise, a determination signal d of "L" is output. The switch 50 connects to contact a when this judgment/determination signal d is “L”, and connects to “H”.
”, the signal z1 selected by the switch 50 is output from the output terminal 51 as a decoded value. That is, the DPCM code of the current frame and the D of the previous frame are
When the PCM code indicates adjacent quantization representative values, a decoded value with the boundary value as the quantization representative value is output,
Otherwise, the same decoded value as before is output.

The output of the limiter 47 (decoded value X1) is also applied to the D flip-flop, and the D flip-flop 48 applies it to the adder 45.46 as the predicted value XI in the next clock cycle. The input of the D flip-flop 48 is the switch 5
The reason why it is connected to the output of the limiter 47 instead of the output of 0 is to match the predicted value of the encoding device.

Next, the operation will be explained based on a specific example. input data 8
bit (0~255), DPCM code 3 bits,
The quantization characteristics are shown in Table 1, and the DPC of the current frame is
Assume that the M code Y is "010" in binary and its predicted value X1 is 50. 91 (=50+41) is applied to the a contact of the switch 50. On the other hand, the output Q'(e■) of the boundary value generation circuit 43 is output from the frame memory 4.
DPCM code Y of the previous frame supplied from 2,
For, when Ylo 001, Q'(e+)=26Yl'
= 011, Q'(e,) = 60, other than these, Q'(e+) = 41 or indeterminate, and the predicted value is
=50 are added, respectively X,' =76.110
is applied to the b contact of the switch 5o. Further, the output d of the adjacent representative value determination circuit 44 is: when Y,' = 001 or 011, d = "H"; otherwise, d+ = "L", and controls the switch 50. Therefore, the decoded value 2. output from the output terminal 51. For the DPCM code Y,° of the previous frame, when Y+' = 001, Z, = 76Y1° = 0
When 11, Z, = 110 When other than the above, Z
,=91.

Now, the difference value (prediction error) before quantization of the previous frame is 60
．． Assuming that the difference value before quantization of the current frame is 61, in the conventional example, the quantization representative value of the previous frame is 41, the quantization representative value of the current frame is 83, and the difference value before quantization (or before encoding) is 41. A slight difference in level appears as a difference in 42 levels upon decoding. This was the cause of the edge business. That is, even in a stationary portion, the quantization representative value changes greatly due to slight noise near the boundaries of quantization steps, and this is recognized on the screen as image quality deterioration.

In this embodiment, the boundary value (=60) is selected as the quantization representative value in the above case, so that the above image quality deterioration is hardly detected on the screen. Further, even if two consecutive frames have the same quantized representative value and the next frame has the same quantized representative value, the change in the decoded value will be approximately 1/2 that of the conventional example. That is, for example, if the difference value before quantization is 60 in the frame before the previous frame, 60 in the previous frame, and 61 in the current frame, the quantization representative values are 41 and 41.60, respectively, and in the conventional example, the decoded value is While the change is at 42 levels, in this example, the change is about 1/2.
Reach level 9. Furthermore, in the moving image portion, unless the quantization representative value of the previous frame and the quantization representative value of the current frame happen to be adjacent to each other, the above correction is not performed and there is no problem. In the moving image part, the time correlation of the difference values is low, so almost no correction is made. Even if 10,000 corrections are made, the difference is corrected instead of calculating the decoded value between frames, so the effect is very small, and it is completed in a single frame and propagated to another frame. Because it does not, it is almost undetectable.

FIG. 2 shows a block diagram of a second embodiment of the present invention. 52 is a DPCM code input terminal, 53 is a frame memory, 54.55 is a quantization representative value generation circuit, 56 is an adjacent representative value determination circuit, 57 is an averaging circuit, 58.59 is an adder, and 60.61 is a limiter. , 62 is a D flip-flop, 63 is a switch for selecting a decoded value, and 64 is an output terminal for the decoded value.

In the embodiment shown in FIG. 2, correction is performed not by the boundary value but by the inter-frame average of the quantized representative values. Below, the first
The parts that are different from the embodiment shown in the figures will be explained.

DPC of the previous frame output from the frame memory 53
The M code Y1' is converted into a difference value Q(e+'') by the quantization representative value generation circuit 55 and applied to the averaging circuit 57.The averaging circuit 57 converts the quantization representative value of the previous frame and the current frame. The adder 59 averages the quantized representative values and adds the predicted value to the average value.The limiter 61 adds the predicted value to the average value.
The amplitude of the output of 9 is limited to a predetermined range. limiter 61
The output is applied to the b contact of the switch 63 as the corrected decoded value X1°. The same decoded value as in the conventional example is applied to the a contact of the switch 63. The switch 63 is controlled by the judgment output dl of an adjacent representative value judgment circuit 56 similar to the adjacent representative value judgment circuit 44, and when the quantized representative values of the previous frame and the current frame are adjacent values, the b contact is Select the decoded value, otherwise select the decoded value of the a contact. Therefore, when the quantization representative values of the previous frame and the current frame are adjacent to each other, the decoded value z1 of the output terminal 64 is the average value of the quantization representative values of the previous frame and the current frame,
Other than that, the decoded values are the same as in the conventional example.

In the embodiment shown in FIG. 1, if the boundary value is set to a value close to either of the quantization representative values, the change between frames due to noise will increase, and the effect will be somewhat degraded. On the other hand, in the embodiment shown in FIG. 2, the change between frames (ie, edge business) is suppressed by using the inter-frame average value of the quantized representative value.

FIG. 3 shows a block diagram of a third embodiment of the present invention. 65 is a DPCM code input terminal, 66 is a representative value generation circuit, 67 is a frame memory, 68 is a correction value generation circuit, 69 is an adder, 70 is a limiter, 71 is a D flip-flop, and 73 is a decoded value output terminal. be.

The quantization representative value generation circuit 66 inputs D to the input terminal 65.
The PCM code Y, is converted into a representative difference value Q(e,), the adder 69 adds the predicted value XI, to this, and the limiter 70
limits the amplitude of the output of adder 69 to a predetermined range. The output of limiter 70 is applied to adder 72 and D flip-flop 71 as decoded value L'. D flip-flop 71 predicts the next clock cycle and adds adder 69
to be applied. The above process is exactly the same as that of a conventional DPCM decoding device.

The DPCM code Y+ of the input terminal 65 is the frame memory 6
7 and the correction value generation circuit 68. The frame memory 67 functions as a delay element for one frame, and applies the DPCM code Y+" of the previous frame to the correction value generation circuit 68. The correction value generation circuit 68 applies the quantized representative value of the current frame and the previous frame When are adjacent values, output a correction value ΔX corresponding to 1/2 of the difference between the quantization representative value of the current frame and the previous frame (or the difference between the boundary value and the quantization representative value of the current frame). , otherwise the correction value ΔX of O is output.

That is, when the quantization representative values between frames are adjacent to each other, Δx
= (Q(e,')-Q(e,)) / 2 or =
Q(e,°)−Q(e,), otherwise ΔX=0.

Adder 72 adds correction value ΔX to the output of limiter 70 (decoded value X+), and the output of adder 72 is output from output terminal 73 as corrected decoded value Zl. Therefore, the decoded value X1 is corrected by 1/2 of the inter-frame difference in quantized representative values only when the quantized representative values between frames are adjacent to each other.

Table 1 The correction value circuit 68 can be formed from a ROM. That is, the correction value may be stored in the addresses indicated by the DPCM codes of the previous frame and the current frame.

If the DPCM code is 3 bits, the required ROM capacity is 2' = 64 as an address, and the number of data bits can be expressed as 1/2 of the maximum step width of the quantization representative value, so 6 bits (±3 If it is about 64X
64=4 bits.

In the third embodiment, the hardware is greatly simplified;
Furthermore, since the correction value can be set arbitrarily, flexibility is increased.

Although the above-mentioned embodiment has been explained by taking the prior value predictive DPCM as an example, the present invention is not limited to this, but can also be applied to other predictive coding methods such as two-dimensional, three-dimensional, or adaptive prediction.

[Effects of the Invention] As can be easily understood from the above description, according to the present invention, edge business can be significantly reduced by simply adding a small amount of circuitry to a conventional decoding device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of the second embodiment, FIG. 3 is a block diagram of the third embodiment, and FIG. 4 is the encoding of the conventional example. FIG. 5 is a block diagram of a conventional decoding device corresponding to FIG. 4. 41.54, 55, 66: Quantization representative value generation circuit 42.
53.67: Frame memory 43: Quantization boundary value generation circuit 44.56: Adjacent quantization representative value determination circuit 57:
Averaging circuit 68: Correction value generation circuit

Claims (1)

[Claims] The method includes a delay means for delaying the encoded code by a frame, and a determination means for determining whether the quantization representative values are adjacent values between frames, and when the quantization representative values are adjacent between the frames, A decoding device characterized in that the quantization representative value of the current frame is set to a value between the quantization representative values of the current frame and the previous frame.