JPH03129823A - Lapping of semiconductor substrate - Google Patents

Lapping of semiconductor substrate

Info

Publication number
JPH03129823A
JPH03129823A JP1268788A JP26878889A JPH03129823A JP H03129823 A JPH03129823 A JP H03129823A JP 1268788 A JP1268788 A JP 1268788A JP 26878889 A JP26878889 A JP 26878889A JP H03129823 A JPH03129823 A JP H03129823A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
lapping
film
lapping jig
photoresist film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1268788A
Other languages
Japanese (ja)
Inventor
Masaki Kobayashi
正樹 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1268788A priority Critical patent/JPH03129823A/en
Publication of JPH03129823A publication Critical patent/JPH03129823A/en
Pending legal-status Critical Current

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  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To enable a semiconductor substrate to be lapped in even thickness by a method wherein the first film comprising a surface protective organic matter is coated on one side main surface of the semiconductor substrate and after forming the second film of an inorganic matter on the first film, the semiconductor substrate is bonded onto a lapping jig. CONSTITUTION:A photoresist film 2 is coated on the element surface of a semiconductor substrate 1 and after baking and drying the photoresist film 2, a gold layer 3 is laminated and evaporated on the photoresist film 2. Next, the gold layer 3 is bonded onto the reference surface 4a of a heated lapping jig 4 through the intermediary of a wax layer 5. Successively, after cooling down the lapping jig 4 for setting the wax layer 5, the rear surface of the semiconductor substrate 1 is spin-ground to manufacture another semiconductor 1a in the thickness specified by the positions of stoppers 6. At this time, the semiconductor substrate 1 can be bonded onto the reference surface 4a of the lapping jig 4 in parallel with each other with high precision since the photoresist film 2 and the wax layer 5 are mutually isolated not to be mixed with each other as they are indirectly in contact with each other through the intermediary of the gold layer 3.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は半導体基板のラッピング方法に係り、特に半導
体基板を均一な厚さにラッピングする方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for lapping a semiconductor substrate, and more particularly to a method for lapping a semiconductor substrate to a uniform thickness.

(従来の技術) マイクロ波通信システムの高性能化を図る為に、GaA
s等を材料とした電界効果トランジスタ(以下、FET
を略称する)の採用が不可欠なものとなりつつある。例
えば、高出力電力増幅用FET (以下、電力FETと
略称する)については、電子管に比べて長寿命であり、
小形、かつ軽量化が図れるなどの利点をもつため、製造
・開発が精力的に進められている。
(Conventional technology) In order to improve the performance of microwave communication systems, GaA
Field effect transistor (hereinafter referred to as FET) made of materials such as s
) is becoming essential. For example, FETs for high output power amplification (hereinafter abbreviated as power FETs) have a longer lifespan than electron tubes.
Because they have the advantage of being small and lightweight, their production and development are being actively pursued.

電力FETの寿命は、動作層温度と密接な関係があり、
動作層温度を低く抑えて寿命を長くするためには、ヒー
トシンクとなるチップ裏面と動作層のある表面との熱抵
抗を低減することが効果的である。この為、FETのチ
ップ厚みを30μ鴎程度の薄いものとし、チップ裏面に
金を厚くめっきすることが行なわれている。
The life of a power FET is closely related to the operating layer temperature.
In order to keep the operating layer temperature low and extend the lifetime, it is effective to reduce the thermal resistance between the back surface of the chip, which serves as a heat sink, and the surface where the operating layer is located. For this reason, the thickness of the FET chip is made as thin as about 30 μm, and the back surface of the chip is plated with a thick layer of gold.

厚さ30μ■のFETを製造する為には、半導体基板を
薄くラッピングする工程が不可欠である。
In order to manufacture an FET with a thickness of 30 μm, a process of thinly lapping the semiconductor substrate is essential.

なぜならば、通常半導体基板は、ハンドリング性を考慮
して300μ園から500μm程度の厚さになっている
からである。
This is because semiconductor substrates usually have a thickness of approximately 300 μm to 500 μm in consideration of handling properties.

ラッピング゛には通常、半導体基板の素子面側に、後に
容易に除去できるホトレジスト等の有機物よりなる表面
保護膜を形成した後、半導体基板の素子面側をワックス
等でラッピング治具の基準面に貼付け、半導体基板の裏
面を研磨することにより行なわれる。このラッピング工
程において、半導体基板をラッピング治具の基準面に平
行に貼付ける事は難しく、例えば3′φの半導体基板を
ラッピング治具に貼付ける場合、 ±10μ−程度の平
行度のばらつきを生じていた。従って半導体基板が同一
基板面内で均一な厚さに形成されず、±10μ踵程度0
厚さのばらつきが生じていた。
Lapping usually involves forming a surface protection film made of organic material such as photoresist on the element side of the semiconductor substrate, which can be easily removed later, and then applying wax or the like to the element side of the semiconductor substrate as a reference surface of the lapping jig. This is done by pasting and polishing the back side of the semiconductor substrate. In this lapping process, it is difficult to attach the semiconductor substrate parallel to the reference surface of the lapping jig. For example, when attaching a 3'φ semiconductor substrate to the lapping jig, there is a variation in parallelism of about ±10 μ-. was. Therefore, the semiconductor substrate is not formed with a uniform thickness within the same substrate surface, and the thickness is approximately ±10μ.
There were variations in thickness.

すなわち、同一基板面内で厚さが所望値30μIの部分
のほか、最大40μmと厚い部分、最小20μ−と薄い
部分が生じていた。厚い部分から切り出されたチップで
は熱抵抗が大きくなり寿命低下が生じる。また薄い部分
から切り出されたチップでは大きなそりを生じたり、割
れやすくなったりする問題が生じていた。
That is, in addition to a portion with a desired thickness of 30 .mu.I within the same substrate surface, there were also a thick portion with a maximum thickness of 40 .mu.m and a thin portion with a minimum thickness of 20 .mu.m. Chips cut from thicker parts have higher thermal resistance and shorter lifespans. Additionally, chips cut from thin sections have the problem of causing large warpage and being susceptible to cracking.

半導体基板をラッピング治具の基準面に平行に貼付ける
ことが難しいのは、半導体基板上に形成した表面保護膜
とラッピング治具への貼付けに用いるワックス等の接着
剤が、いずれも有機物により構成されている為、両者が
混合され易く、またこの混合物及びワックス等が比較的
大きな粘性を有するからである。
The reason why it is difficult to attach the semiconductor substrate parallel to the reference plane of the lapping jig is that the surface protective film formed on the semiconductor substrate and the adhesive such as wax used to attach it to the lapping jig are both composed of organic substances. This is because the two are easily mixed together, and this mixture and wax have relatively high viscosity.

(発明が解決しようとする課題) 上記従来のラッピング法によれば、半導体基板をラッピ
ング治具に貼付けるとき、両者の平行度を高精度にする
ことが重要であるが、半導体基板の表面保護膜とラッピ
ング治具への接着剤が混合し、平行度が劣化するという
重大な問題がある。
(Problems to be Solved by the Invention) According to the above-mentioned conventional lapping method, when attaching a semiconductor substrate to a lapping jig, it is important to make the parallelism of both parts highly accurate; There is a serious problem in that the film and the adhesive to the wrapping jig mix and the parallelism deteriorates.

本発明は叙上の従来技術における問題点を改良するため
になされたもので、半導体基板をラッピング治具の基準
面に平行に貼り付けることにより、半導体基板に均一な
厚さにラッピングを施すラッピング方法を提供すること
を目的とする。
The present invention has been made in order to improve the problems in the prior art described above, and is a lapping method in which the semiconductor substrate is lapped to a uniform thickness by attaching the semiconductor substrate parallel to the reference plane of the lapping jig. The purpose is to provide a method.

〔発明の構成〕[Structure of the invention]

(11題を解決するための手段) 本発明にかかる半導体基板のラッピング方法は、半導体
基板の一方の主面にその表面保護のための有機物よりな
る第1被膜を被着し、ついで該第1被膜上に無機物より
なる第2被膜を積層し形成した後、前記半導体基板をラ
ッピング用治具に貼着保持させ、半導体基板の他方の主
面にラッピングを施すことを特徴とする。
(Means for Solving Problem 11) A semiconductor substrate lapping method according to the present invention includes depositing a first film made of an organic material on one main surface of a semiconductor substrate for surface protection, and then After a second coating made of an inorganic material is laminated and formed on the coating, the semiconductor substrate is adhered and held on a lapping jig, and the other main surface of the semiconductor substrate is subjected to lapping.

(作 用) 本発明は半導体基板上に形成した有機物の表面保護膜と
、ラッピング治具への貼り付けに用いるワックス等の接
着剤との混合を防止することが出来るため、半導体基板
をラッピング治具の基準面に対して高精度に平行を保っ
て貼付けが達成される。これにより均一な厚さに半導体
基板をラッピングすることが出来る。
(Function) The present invention can prevent the organic surface protective film formed on the semiconductor substrate from mixing with the adhesive such as wax used for attaching the semiconductor substrate to the lapping jig. Pasting is achieved while maintaining parallelism with high accuracy to the reference plane of the tool. This makes it possible to wrap the semiconductor substrate to a uniform thickness.

(実施例) 以下、本発明の一実施例を図面を参照して説明する。(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

まず、第1図に断面図で示すように、半導体基板1の素
子面側に例えばA21350(商品名、ヘキスト社製)
の如きホトレジストwA2を塗着けし、100℃にて2
0分間ベーキング、乾燥を施したのち、ホトレジスト膜
2上にこれと積層し金層3を約1000人厚さに蒸着す
る。次いで、上記半導体基板1はその上面に被着された
金層3を、150℃に加熱されたラッピング治具4の基
準面4aに、ワックス層5で貼付けられる。
First, as shown in the cross-sectional view in FIG.
Apply photoresist wA2 such as
After baking and drying for 0 minutes, a gold layer 3 is deposited on the photoresist film 2 to a thickness of about 1,000 layers. Next, the gold layer 3 deposited on the upper surface of the semiconductor substrate 1 is pasted onto the reference surface 4a of the lapping jig 4 heated to 150° C. using the wax layer 5.

続いて第2図に示すように、ラッピング治具4を冷却し
てワックス層5を固化させたのち、半導体基板1の裏面
に回転研磨を施し、ストッパ6の位置できまる所望の厚
さの半導体基板1aが得られる。
Next, as shown in FIG. 2, the lapping jig 4 is cooled to solidify the wax layer 5, and then the back surface of the semiconductor substrate 1 is rotary polished to form a semiconductor of a desired thickness at the position of the stopper 6. A substrate 1a is obtained.

上記において、ホトレジスト膜2とワックス層5は金層
3を介して接し、隔離されており、両者は混合されるこ
とがないので、ラッピング治具の基準面4aに半導体基
板1を高精度で平行に貼付けることができる。この平行
度のばらつきは 3′径の半導体基板の場合に±5μ醜
以内に収められた。
In the above, the photoresist film 2 and the wax layer 5 are in contact with each other through the gold layer 3 and are separated from each other, and the two are not mixed. Therefore, the semiconductor substrate 1 is parallel to the reference surface 4a of the lapping jig with high precision. It can be pasted on. This variation in parallelism was kept within ±5μ in the case of a 3' diameter semiconductor substrate.

【発明の効果〕【Effect of the invention〕

以上述べたように本発明によれば、半導体基板上に形成
した表面保護膜と、ラッピング治具への貼付けに用いる
ワックス等の接着剤との混合を防ぐことができる為、半
導体基板をラッピング治具の基準面に対して平行に貼付
けることができ、均一な厚さに半導体基板をラッピング
することができる。
As described above, according to the present invention, it is possible to prevent the surface protective film formed on the semiconductor substrate from mixing with the adhesive such as wax used for attaching it to the lapping jig. It can be attached parallel to the reference plane of the tool, and the semiconductor substrate can be wrapped to a uniform thickness.

なお、本実施例においては、表面保護膜としてホトレジ
ストA21350(商品名、ヘキスト社製)を用いたが
、同様の効果を有するホトレジスト例えば1350J(
商品名、ヘキスト社製)などでもよく、また他の有機物
例えばポリイミドを用いてもよい。
In this example, photoresist A21350 (trade name, manufactured by Hoechst Co., Ltd.) was used as the surface protective film, but a photoresist having a similar effect, such as 1350J (
(trade name, manufactured by Hoechst), or other organic materials such as polyimide may be used.

また1表面保護膜を形成した後1本実施例では金を蒸着
しているが、表面保護膜とワックス等の接着剤とが混合
しなければ何でもよく1例えばアルミニウム等の金属膜
を蒸着しても良いし、酸化膜等の絶縁膜をスパッタによ
り形成しても良い。
In addition, after forming the surface protective film, gold is vapor-deposited in this example, but as long as the surface-protective film and wax or other adhesive do not mix, any material may be used.For example, a metal film such as aluminum may be vapor-deposited. Alternatively, an insulating film such as an oxide film may be formed by sputtering.

さらに、半導体基板をラッピング治具に貼付ける接着剤
として、ワックス以外の有機物1例えばホトレジストA
Z 1350(商品名、ヘキスト社製)などを用いても
構わない。
Furthermore, organic substances other than wax such as photoresist A can be used as an adhesive for attaching the semiconductor substrate to the lapping jig.
Z 1350 (trade name, manufactured by Hoechst) or the like may be used.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明にかかる一実施例の半導体基板のラッピン
グ方法を説明するためのもので、第1図は半導体基板を
ラッピング治具に貼付けした状態の断面図、第2図は半
導体基板のラッピング後の状態を示す断面図である。 1、la・・・半導体基板   2・・・ホトレジスト
膜3・・・金層        4・・・ラッピング治
具4a・・・ラッピング治具の基準面 5・・・ワックス層
The drawings are for explaining a semiconductor substrate lapping method according to an embodiment of the present invention. Fig. 1 is a cross-sectional view of the semiconductor substrate attached to a lapping jig, and Fig. 2 is a cross-sectional view of the semiconductor substrate after lapping. FIG. 1, la... Semiconductor substrate 2... Photoresist film 3... Gold layer 4... Lapping jig 4a... Reference surface of lapping jig 5... Wax layer

Claims (1)

【特許請求の範囲】[Claims]  半導体基板の一方の主面にその表面保護のための有機
物よりなる第1被膜を被着し、ついで該第1被膜上に無
機物よりなる第2被膜を積層し形成した後、前記半導体
基板をラッピング用治具に貼着保持させ、半導体基板の
他方の主面にラッピングを施すことを特徴とする半導体
基板のラッピング方法。
A first film made of an organic material is applied to one main surface of the semiconductor substrate for surface protection, and then a second film made of an inorganic material is laminated and formed on the first film, and then the semiconductor substrate is wrapped. 1. A method for lapping a semiconductor substrate, which comprises lapping the other main surface of the semiconductor substrate by attaching and holding the semiconductor substrate to a jig.
JP1268788A 1989-10-16 1989-10-16 Lapping of semiconductor substrate Pending JPH03129823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1268788A JPH03129823A (en) 1989-10-16 1989-10-16 Lapping of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1268788A JPH03129823A (en) 1989-10-16 1989-10-16 Lapping of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH03129823A true JPH03129823A (en) 1991-06-03

Family

ID=17463287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1268788A Pending JPH03129823A (en) 1989-10-16 1989-10-16 Lapping of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH03129823A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7459397B2 (en) 2004-05-06 2008-12-02 Opnext Japan, Inc. Polishing method for semiconductor substrate, and polishing jig used therein
CN103489756A (en) * 2013-10-11 2014-01-01 中国科学院微电子研究所 Sheet bonding method in substrate thinning technique

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7459397B2 (en) 2004-05-06 2008-12-02 Opnext Japan, Inc. Polishing method for semiconductor substrate, and polishing jig used therein
DE102005001259B4 (en) * 2004-05-06 2011-02-17 OpNext Japan, Inc., Yokohama Polishing method for a semiconductor substrate
CN103489756A (en) * 2013-10-11 2014-01-01 中国科学院微电子研究所 Sheet bonding method in substrate thinning technique

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