JPH03129752A - Manufacture of dielectric isolation substrate - Google Patents

Abstract

PURPOSE:To reduce a warp of a substrate to 50mum or lower by a method wherein a polycrystalline silicon layer having a specific film thickness is formed, by reducing and decomposing a chlorosilane, on a first single-crystal silicon substrate in which an insulating film of silicon dioxide is formed in an isolation groove. CONSTITUTION:Isolation grooves 3 are formed in one face 2 of a first single-crystal silicon substrate 1; the first single-crystal silicon substrate 1 in which the isolation grooves 3 have been formed in its one face 2 is thermally oxidized; a thermal oxide film 4 is formed on a substrate face; a polycrystalline silicon layer 5 having a film thickness of 100mum or lower is deposited, by reducing and decomposing a chlorosilane, on the side where the isolation grooves have been formed. The main surface of the deposited polycrystalline layer 5 is polished; its flatness is set to 5mum or lower and its surface roughness is set to 50nm or lower; a polished face of the polycrystalline silicon layer 5 is thermocompression-bonded and bonded to a polished face of a second single-crystal silicon substrate whose surface roughness is 50mum or lower; the first single-crystal silicon substrate 1 is polished and removed down to a position of at least the bottom of the isolation grooves from the side where the polycrystalline silicon layer 5 is not deposited.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a method for manufacturing a dielectric plate, and in particular to a method for manufacturing a dielectric isolation board for integrated circuits with small warpage and no alkali metal contamination. Regarding the manufacturing method.

(b) Conventional technology The dielectric isolation substrate has a silicon dioxide isolation layer around it, and a monocrystalline silicon semiconductor island is insulated and isolated by a groove IIK filled with a polycrystalline silicon support layer. Since the semiconductor integrated circuit element is formed by using a semiconductor integrated circuit, it is suitable for manufacturing a semiconductor integrated circuit element having a large capacity and a high breakdown voltage.

However, the dielectric isolation substrate uses a polycrystalline silicon layer as a support layer. For example, in a single crystal silicon semiconductor substrate with a diameter of 100 mm (4"φ), the polycrystalline silicon layer is layered to a thickness of about 550 μm. Since the semiconductor substrate is formed by a phase growth method, the difference in thermal expansion coefficient between the two causes the semiconductor substrate to warp significantly by 150 μm or more, resulting in problems such as lower processing accuracy in the polishing step and difficulty in processing in subsequent steps.

Therefore, in order to form a dielectric isolation substrate with small warpage, a method has been proposed in which a plurality of silicon dioxide layers are provided in a polycrystalline silicon layer.

(c) Problems to be solved by the invention Generally, in order to improve the processing accuracy of semiconductor substrates, the warpage of the substrate is set to be 100 μm or less, but multiple silicon dioxide layers are provided in the polycrystalline silicon layer. Even though it is possible to reduce the warpage to 150 μm or less by creating a multilayer structure, it is necessary to stabilize the warp to 100 μm or less to improve processing accuracy.
It is difficult to make it 11 inches.

Moreover, while forming the polycrystalline silicon layer in a pancake-type vertical furnace, a process of forming multiple silicon dioxide layers must be performed, and furthermore, this requires complicated operations and is usually This is problematic because it takes a long time compared to the growth cycle time of a polycrystalline silicon layer.

Therefore, as a method for forming a support with small warpage and high productivity, a method has been proposed in which a single-crystal silicon substrate that will become a support layer is bonded to a single-crystal silicon substrate with separation grooves.

But in this case minutes! After filling the grooves in the single-crystal silicon substrate with 1 lil by applying, for example, BzO* 5iOz-based glass, it is necessary to heat and press it to the support substrate to fix it. The problem of alkali metal contamination arises.The present invention aims to solve such problems in manufacturing dielectric separation substrates such as warpage and contamination that occur during the formation of the support layer.

(d) Means for Solving the Problems The present invention aims to provide a method for manufacturing a dielectric isolation substrate that exhibits small warpage and no alkali metal contamination even when the diameter is increased to 100 am or more. There is.

That is, the present invention forms an Ili groove on one side of a first single crystal silicon substrate, thermally oxidizes the first single crystal silicon substrate with an isolation groove formed on one side, and heats the substrate surface. An oxide film is formed, and then isolation trenches are formed!
i11, by reductive decomposition of chlorosilane, 100 μm
A polycrystalline silicon layer having the following thickness is deposited, and the main surface of the deposited polycrystalline silicon layer is polished to a flatness of 5 μm or less and a surface roughness of 50 nm or less. The polished surface is bonded to the polished surface of the second single-crystal silicon substrate with a surface roughness of 50 nm or less by heat-pressing, and the first single-crystal silicon substrate is attached at least from the side on which the polycrystalline silicon layer is not deposited. A method of manufacturing a dielectric isolation substrate is characterized in that the isolation groove is removed by polishing down to the bottom of the isolation groove.

In the present invention, similarly to the conventional method for manufacturing a dielectric isolation substrate, an isolation groove is formed on one side of a first single crystal silicon substrate, and the single crystal silicon substrate with the isolation groove formed on one side is heated. The substrate is oxidized to form an insulating thermal oxide film on the surface of the substrate.

In the present invention, after the thermal oxidation film is formed, chlorosilane is heated together with hydrogen to form a polycrystalline silicon layer by vapor phase growth. When the thickness of the polycrystalline silicon layer is set to 100 μm or less, the warpage of the substrate can be kept to 50 μm or less. Therefore, in the present invention, the thickness of the polycrystalline silicon layer formed by vapor phase growth is From the relationship with warpage 1
00μ resistance or less.

In the present invention, in order to bond the formed polycrystalline silicon layer to the second single-crystal silicon substrate that serves as a support, it is necessary to bond the polycrystalline silicon layer and the second single-crystal silicon substrate that serves as a support. Both bonding surfaces have a surface roughness of 50 nm.
Polished as shown below. The bonding surface of the second single crystal silicon substrate of the support and the bonding surface of the polycrystalline silicon layer is
By polishing to a surface roughness of nm or less, the single crystal silicon substrate of the support and the polycrystalline silicon layer can be bonded without requiring a binder.

In the present invention, polycrystalline silicon is produced by reductive decomposition of chlorosilane on a first single-crystal silicon substrate on which an insulating film of silicon dioxide is formed in the isolation grooves, similar to the conventional manufacturing method of dielectric isolation substrates. The thickness is the depth of the groove plus 40 μm, typically 100 μm.
It may be less than m. After this polycrystalline silicon is deposited, the surface is
Since unevenness is formed with the same depth as the separation groove, that is, several tens of microns, the surface layer is flattened by surface grinding and polishing to a maximum depth of 40 μm. During this polishing,
Immediately after polycrystalline deposition, the warpage of the tool is controlled to 50 μm or less, so the processing can be performed with high precision.

Next, the roughness of the polished surfaces is set to 50 nm or less, similar to the second single crystal substrate serving as a support, and when these polished surfaces are brought into close contact and heat-pressed, there are no voids at the interface and the bond is bonded. This is preferable because a strong and good bond can be obtained. In this case, for example, the compression pressure may be IKg per square centimeter, and the temperature may be 1000°C.

In such thermocompression bonding, it is preferable that the flatness of the bonded surface is 5 μm or less because a good bonded surface can be obtained. Further, it is preferable that the surface roughness is 50 nm or less, since a good bond without voids of 500 Kg/cm' or more can be obtained by thermocompression bonding.

(E) Function The present invention provides a method for manufacturing a dielectric isolation substrate by bonding, by applying a layer of 100 μm or less by reductive decomposition of chlorosilane onto a first single crystal silicon substrate on which an insulating film of silicon dioxide is formed in the isolation groove. Since the polycrystalline silicon JM having a film thickness is deposited, the warpage of the substrate can be reduced to 50 μm or less, making processing easier, and making it possible to
This enables high-yield production of a dielectric isolation substrate by bonding with a single-crystal silicon substrate, and in particular, enables complete bonding without using a binder.

In the present invention, since the polycrystalline silicon layer formed on the first single-crystal silicon substrate has small warpage, its surface can be
Flatness is less than 5μrn and surface roughness is 50nm
By polishing the surface roughness of the second single-crystal silicon substrate serving as a support to 50 nm or less, and joining the polished surfaces on both sides by heating and pressing, it is possible to eliminate cracks. It is possible to easily manufacture a dielectric isolation substrate while preventing a decrease in yield due to the above.

(F) Examples 1.4.1 of the implementation of the present invention will be explained below with reference to Examples, but the present invention is not limited in any way by the following examples and explanations.

Example 1 The main surface 2 of an n-type <100> single-crystal silicon wafer 1 with a diameter of 100 mm is thermally oxidized, and then an M4-shaped portion N? il 3 is formed, a silicon dioxide film 4 is formed on the entire surface, and a 91 crystal silicon semi-dedicated substrate having a section (2) with an isolation oxide film is produced.

Next, the single-crystal silicon wafer on which the silicon dioxide film has been formed is placed in a Pangeki-type vertical furnace, and polycrystalline silicon 5 is deposited on the silicon dioxide film 4 on the wafer.
is deposited by vapor phase epitaxy. This growth was performed by reductively decomposing 5% trichlorosilane diluted with hydrogen in a vertical furnace at 1200°C at a growth rate of 3.5 μm/min, and the thickness of the polycrystalline silicon layer 5 was 100 μm. I ended it when I got there. The warpage of the single crystal silicon wafer 1 due to the formation of the polycrystalline silicon layer 5 was approximately 40 μm on the polycrystalline silicon 5 side.

The single-crystal silicon wafer on which the polycrystalline silicon layer 5 is formed is mirror-finished by plane-grounding the surface 6 of the polycrystalline silicon layer 5 by 20 μm and then polishing by 15 μm to have a flatness of 3 μm and a surface roughness of 10 nm. Ta. (No. 11) In order to bond the monocrystalline silicon wafer 7 for the support to be bonded to the bonding surface 6 of the polycrystalline silicon layer 5, the base surface 8 of the -fil crystal silicon wafer for the support is bonded. Polished to a mirror surface with a surface roughness of 5 nm or less.

Each of the wafers 1 and 7 polished in this way is cleaned with a cleaning solution consisting of ammonia and hydrogen peroxide (RCA cleaning), and then the bonding surface 8 of the single crystal silicon wafer 7 for the support is bonded to the single crystal silicon wafer 1. The polycrystalline silicon layer 5 is sent into a heating furnace 9 in which a temperature gradient of 600 to 1200"C is formed in accordance with the bonding surface 6, heated along the temperature gradient, and finally pressurized at 1200"C. Joined (
Figure 2.

In this example, from the joining process? The warpage remained unchanged at 40μm even after the 1Jls removal process.
Furthermore, a suitable dielectric separation substrate was obtained that was easy to polish, had no voids on the bonding surface, and did not cause contamination.

In FIG. 3, the heating furnace 9 used in this example is shown in a simplified manner for convenience of explanation.

The heating furnace 9 includes a heating chamber 11 surrounded by a furnace wall 1o made of quartz. The ceiling portion 12 of the heating chamber 11 is formed thick in order to receive pressurizing force. Single-crystal silicon wafer 1 having a mirror-polished polycrystalline silicon layer 5
and the lit silicon wafer 7 for the support has a polished surface 6
and 8 are stacked facing each other and placed on the pressure mounting portion 14 of the protruding member 13 made of silicon carbide. The protruding member 13 is driven by a drive device (not shown) provided with a control motor provided in a drive section 15 below the heating chamber 11. ), and a temperature gradient is formed such that the lower part is lower in temperature and the upper part is lower in temperature.

Since this example is constructed as described above, a bonding material in which a single-crystal silicon wafer 7 for a support and a single-crystal silicon wafer 1 having a polycrystalline silicon layer 5 are stacked on a pressurizing mounting part 14 16 is placed, and the silicon carbide protrusion member 13 is moved upward.

In this example, the temperature gradient of the heating furnace is 600'C at the bottom and 1200'C at the top, so the joining material 1
6 is heated to a predetermined temperature before contacting the pressurizing ceiling part 12. The joining material 16 is heated to a predetermined temperature, for example, 1200° C., and its upper surface comes into contact with the ceiling portion 12.

When the joining material 16 touches the ceiling, the protruding member 13 is further pushed up, and the joining material 16 is loaded with 100 g.
/cm2 to 1000 g/cm'' is applied to the polycrystalline silicon layer 5 and the single crystal silicon wafer 7 for support.
are joined.

In this example, the cleanliness level was maintained at class 10 from the washing process to the bonding process.

(G) Effects of the Invention In manufacturing a dielectric isolation substrate, the present invention provides a polycrystalline silicon substrate on which an insulating film of silicon dioxide is formed in the isolation groove, and which has a film thickness of 100 μm or less by reductive decomposition of chlorosilane. Since a polycrystalline silicon network is deposited, the warpage is smaller than that of conventional substrates, and processing such as bonding and polishing removal is easy, and the rate of non-defective chips can be improved.

Moreover, in the dielectric separation substrate of the present invention, since the polycrystalline silicon layer and the single crystal silicon support are directly pressure-bonded, peeling and alkali metal contamination do not occur as compared to conventional dielectric separation substrates.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a polycrystalline silicon semiconductor substrate having a V-groove with an isolation oxide film on which a polycrystalline silicon layer is formed by vapor phase growth, and FIG. FIG. 2 is a cross-sectional view schematically showing a bonding structure between a single crystal silicon semiconductor substrate having a vortex and a single crystal silicon wafer for a support with an isolation oxide film formed by a vapor phase epitaxy method. Figure 3 shows the heat-press bonding of a single-crystal silicon half-barrel substrate with a separation oxide film on which a polycrystalline silicon layer of the present invention is formed by vapor phase growth and a single-crystal silicon wafer for a support. FIG. 2 is a schematic explanatory diagram of a heating furnace used. Regarding the symbols in the figure, 1 is the n-type single crystal silicon wafer, 2 is the main surface, 3 is the mesh portion M if4.4 is the silicon dioxide film, 5 is the polycrystalline silicon layer, and 6 is the polycrystalline silicon layer. Bonding surface, 7 is a bonded silicon wafer for support, 8
1 is a bonding surface of a single crystal silicon wafer for a support, 9 is a heating furnace, 10 is a quartz furnace wall, 11 is a heating chamber, 12 is a ceiling, 13 is a protruding member made of silicon carbide, and 14 is a pressurizing mounting. 15 is a drive section, and 16 is a joining material. Figure 3q

Claims (1)

[Claims] (1) A separation groove is formed on one side of a first single crystal silicon substrate, and a thermal oxide film is formed on the substrate surface by thermally oxidizing the first single crystal silicon substrate on which the separation groove is formed on one side. Then, on the side where the separation groove is formed, a polycrystalline silicon layer having a thickness of 100 μm or less is deposited by reductive decomposition of chlorosilane, and the main surface of the deposited polycrystalline silicon layer is polished to make it flat. The polishing surface of this polycrystalline silicon layer is polished to a surface roughness of 5 μm or less and a surface roughness of 50 nm or less.
A dielectric characterized in that the first single-crystal silicon substrate is bonded to a polished surface of nm or less by heating and pressure bonding, and the first single-crystal silicon substrate is polished away from the side on which the polycrystalline silicon layer is not deposited to at least the position of the bottom of the separation groove. A method for manufacturing a body separation substrate.