JPH0312896A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To decode a variable length code and to improve the performance of CAM by providing address information of m-number of words in an output data memory and deciding one word concerned from m-number of words as address information of content coincidence based on a comparison result from m-number of comparison circuits. CONSTITUTION:M-number of comparison circuits 13 in a comparison means hold code data and comparison masks and compare external information with code data as to the bits of a specified value designated by comparison masks when external information having the number of total codes (m) having the length of maximum (n) bits. The output data memory decides one word concerned from m-number of words as address information of content coincidence. Thus, individual comparison masks are held for data one word even in the case of the variable length code and the bits corresponding to the variable length code are compared with code data. Thus, the variable length code can be decoded and performance can be improved.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a semiconductor memory device called CAM that can decode variable length codes and improve performance. In the semiconductor memory device, the memory contents are compared by a comparison means, and when the comparison results in a match with external information, the address information of the contents matching is outputted from the output data memory to the outside, the comparison means is configured to compare the total number m of codes of the external information. The comparator circuit holds two parameters, code data and comparison mask, as memory contents, and stores external information of a total number m of codes with a maximum length of n bits. When input from the F part, only bits of a specific value specified by the comparison mask are compared with the external information and the code data, and the comparison result is transmitted to the output data memory, and the output data memory , m words of address information, and is configured to determine one corresponding word from among the m words as address information whose content matches, based on the comparison results from the m comparison circuits.

[Industrial application field]

TECHNICAL FIELD The present invention relates to a semiconductor memory device, and more particularly, the present invention relates to a semiconductor memory device.
(Content Addressable Mem
The present invention relates to a semiconductor memory device called ``ory''.

A CAM is a memory capable of outputting an address holding the same data as data given from the outside, and is used, for example, in a computer's cassette memory.

[Conventional technology]

While normal memory reads and writes stored data by specifying the address of the storage cell, CAM inputs search data (interrogative data) and searches for a group of storage cells whose contents match the stored data. (corresponding word) and reads the stored data belonging to this word. That is, search data with a number of bits smaller than the focus width of the cell array is input, and the bits 1- for which there is no search data are unnecessary bits for the search and are masked during the search. Next, matching of the search data and the stored data of each word is executed simultaneously for all words, and a flag (responding flag) is set for the word for which a matching search is established.
is erected.

If there are a plurality of words for which a matching search has been established, one word among them is selected and the stored data is read out. In addition, C
In addition to this search function, the AM must also have a normal memory function for reading and writing stored data by specifying an address.

An example of the logical configuration of a basic cell in a CAM, as shown in FIG. 8, has a word line Si for address designation, data lines DI and Dix for passing read and write information, and a transistor Q (MOS)
In addition to the usual memory cell elements consisting of the memory cell I, Q4 and the memory cell I, an MO3I-transistor Q2. Q3. Q4. Q
Exclusive OR (exclusive OR) between the output of memory cell 1 and the search data (corresponding to the datum of the comparison result).
It has a circuit that performs sive OR), and is configured to output the result of a match search (comparison) to a common flag output line (signal line) EQj for each word.

The above is from IEEE Journal of 5olid
5tate C1rcuits, Vol, 5C-2
0,'No, 5. October 1985 issue, pp, 951
This is an example published in 957.

[Problem to be solved by the invention]

However, such conventional CAMs have a problem in that they cannot decode so-called variable-length codes during data processing and can only compare fixed-length codes.

To explain this in detail, first, variable length codes are used to efficiently transfer and record by assigning different code lengths depending on the probability of occurrence of the element to be encoded. Although such variable length codes have high transfer and recording efficiency, there are problems with the decoding circuit. -For example,
Consider a case where the code length is 1 to 16 bits and the total number of codes is 256. Conventionally, when decoding this code at high speed, a 64-word memory was used, the variable length code was input manually as an address, and the read data was used as the decoding result. The disadvantage of this method is that it requires a large amount of memory.

This is because the maximum code length is 16 bits, so a memory capacity corresponding to the maximum bit is required.

On the other hand, when CAM is used, the result is as follows.

That is, when the CAM 4 stores all codes and decodes the code, it is sufficient to output from the CAM the address where the code matching the code to be decoded is held. In this case, the amount of data that must be held in the CAM is 256 in the above example, and the amount of memory required is significantly reduced.

However, the problem here is that conventional CAMs can only compare fixed lengths. Therefore, it is desired to improve the performance of CAM.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that can decode variable length codes and improve performance.

[Means to solve the problem]

In order to achieve the above object, the semiconductor memory device according to the present invention compares external information and memory contents using a comparing means, and as a result of the comparison,
When a match is made with the external information, the comparing means selects a semiconductor memory device number that outputs the address information whose contents match to the outside from the output data memory, and the comparing means operates m comparing circuits corresponding to the total number m of codes of the external information. The comparator circuit holds two parameters, code data and a comparison mask, as memory contents, and when external information of a total number m of codes with a maximum length of n bits is inputted from the outside, The code data is compared with external information only for bits of a specified specific value, and the comparison result is transmitted to an output data memory, and the output data memory has m words of address information and m words of address information. Based on the comparison result from the comparison circuit, one word out of the m words is determined as address information whose contents match.

[Effect]

In the present invention, the m comparison circuits in the comparison means hold code data and a comparison mask, and when external information of a total number m of codes having a maximum length of n bits is input from the outside, the comparison circuits hold the code data and the comparison mask. External information and the code data are compared only for a focus of a specific value specified by , and based on the comparison result, the output data memory determines one corresponding word from m words as address information with matching contents. .

Therefore, even in the case of a variable length code, if a separate comparison mask is maintained for each word of data and the bits corresponding to the variable length code are compared with the code data, variable length codes can be decoded. Become.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 7 are diagrams showing an embodiment of a semiconductor memory device according to the present invention. Figure 1 is a block diagram showing the overall configuration of CAM, and in this figure, CAM is roughly divided into 1
0 control circuit 11, address decoder 12, 16-bit comparison circuit group 13, dummy comparison circuit 14, and output code R
It is composed of OM15.

Note that the CAM shown in this embodiment has 1 word-16 bits,
This is an example applied to 256 words, and this CAM has the following 3
Controlled by one signal.

OR (Output Enable) OE=1 specifies that reading is to be performed.

W E (Write Enable) WE=1 specifies that writing is to be performed.

CE (Compare Enable) CB=1 specifies that a comparison is to be performed.

Activating the above three signals simultaneously is prohibited.

First, the 16-bit comparison circuit group 13 (corresponding to comparison means) consists of 256 circuits (corresponding to comparison circuits) divided by O to 255, and one circuit connects one word of basic cells. The details are shown in FIG. The 16-bit comparison circuit group 13 has an EQ for each circuit.
O~E Output code RO via signal line Q255
M15, and the specific signal line EQj is connected to CE,
It is precharged when the OB and WE signals are all "O". One 16-bit comparison circuit group 13
The bisothocomparison circuit holds 16 bits of data and comparison mask bits, but the following is taken into account. The comparison mask can ignore comparisons of any bits among the 16 bits. Therefore, it is also possible to ignore all bit comparisons. Note that it is meaningless to ignore comparisons of all bits, so a comparison mask of 15 bits is sufficient.

FIG. 2 shows, as an example, a certain (j-th) 16-bit comparison circuit 13j (corresponding to a comparison circuit).
The 16-bit comparison circuit 13j has 16 basic cells 20, and the signal vAEQj is connected to the power supply Vcc by a MOS transistor 210 when CB, OB, and WE are all "0".
The file will be displayed during the process. Also, in Figure 2, Do
, DOX-DI5. D15X is a data line, SDj is a word line corresponding to memory cell 1, and SMj is memory cell 2.
(details will be described later).

The basic cell 20 is shown as shown in FIG. 3, and a memory cell 2 is added to the conventional memory cell 1 shown in FIG. It is configured by adding Mo3) transistors Q7 to QIO.

The basic cell 20 shown in FIG. 3 operates as follows.

(1) Read operation A word to be read is selected by word line SDjSMj, and data lines Di and DiX are set to a high impedance state at the time of reading.

When SDj becomes “1”, Mo3) Ranjisk Ql, Q
4 is turned on, and the data in memory cell 1 is transferred to data line Di.
, DiX. Similarly, when SMj becomes "1", Mo5t transistor Q9. QlO is turned on, and data in memory cell 2 is read to data lines Di and DiX. Note that the data output to Di and DiX is differentially amplified by a sense amplifier in the IO control circuit 11 and output to the outside.

(II) Write Operation The word to be written is selected by the word line SDjSMj, and at the time of writing, the IO control circuit 11 outputs the data to be written to the data line DiDiX. In this case, data having mutually inverted values is output to the data line DiDiX. When SDj becomes "1", Mo3+- transistors Qi and Q4 are turned on, and memory cell 1 receives Di,
DiX(7) value is written. Similarly, when S MJ becomes 1, Mo3I-transistor Q9. Q10 is turned on, and the values of Di and DiX are written into memory cell 2.

(III) Comparison operation Comparisons are performed on all words simultaneously.

1 2 Before executing the comparison, precharge the signal line EQj that outputs the comparison result. Thereafter, the IO control circuit 11 outputs the data to be compared to DI and DiX, and at this time outputs mutually inverted values to the data lines Di and DiX.

The bit that can output the comparison result is only when the memory cell 2 holds "1", and whether or not to output the comparison result is controlled by MOS transistors Q7 and Q8.In other words, when MOS transistor Q7 is on, When the value of memory cell 1 is "'0" and Di=1, Mo3+- transistor Q
2. Q3. The signal line EQj is discharged through Q7.

Also, Q8 is on and the value of memory cell 1 is “1” DiX=
1, Mo3) transistor Q5゜Q6. The signal line EQj is discharged through Q8. Therefore, when the value of memory cell 2 is "0" or when the data to be compared and the value of memory cell 1 match, the signal 'TaEQj is set to "0".
1” is output.The comparison result of the same word is EQ
Wired AND processing is performed on j, resulting in a comparison result for one word.

Next, the address decoder 12 selects one target word according to the address signal AO-A8 during a read/write operation, and the LSB of the address selects data (memory cell 1) or comparison mask (memory cell 2). Use to select. Selected output SD only when OB+WE=l
Output "1" to one of j, SMj (j-〇, 1...255).

The dummy comparator circuit 14 is for determining the end of discharging of one circuit in the 16-bit comparator circuit group 13 and determining the discharge start time of the output code ROM 15, and its detailed configuration is shown in FIG. The dummy comparator circuit 14 includes 15 load elements 22a, 22b to 22c, and 22p that are composed of a pair of Mo3) transistors that serve as a capacitive load equal to that of the signal line EQj, and a MOS transistor 23 for precharge control. , control line ENE
Mo3I-ransistor 2 for QX discharge control
It consists of 4 to 29. The dummy comparison circuit 14 is CE, OE
, WE signals 34 are all 0', the Mo3+- transistor 23 is turned on to precharge the control line ENEQ)ζ, and the charge charges are stored in the 15 load elements 222 to 22p. When data is output to the data lines DO and DOX, the Mo3L transistors 25 and 28 are turned on to start discharging the charges on the control line ENEQX stored in the load elements 22a to 22p, and ENEQX=0. When this occurs, the signal line EQj is also set to have finished discharging. That is, this is to ensure the data comparison time in the basic cell 20 described above.

An output code ROM (corresponding to an output data memory) 15 is a ROM for outputting the address of a word whose comparison result is "1", and its detailed configuration is shown in FIG. In FIG. 5, WO to W255 are word lines in the ROM, BO to B8 are focus lines, and bit lines B
is 9 Mo3 for precharge control when CE=0
It is precharged by I-transistors 31a to 31i. Then, after CE=1 and the discharge of the comparison result is completed to the signal lines EQO to EQ255, R
Start discharging the bit lines BO to B8 in OM. That is, the comparison results appear in EQO to EQ255. Among EQO to EQ255, signal lines for which the comparison results do not match are discharged and become 0, and only signal lines that match become 1. This comparison result is latched into the launch circuit 33. On the other hand, the control line ENEQX is discharged at the same timing as EQO to EQ255 to determine the comparison end time. ENEQX is latched by the launch circuit 34, passes through gates 35, 36, and 37, and is set to W by gate 38.
Enable O~W255. At this time, the comparison result is 1.
1 is output only to Wj corresponding to Qj.

Therefore, in the example of FIG. 5, the Mos+ transistors 39 and 40 connected to the pinto line BO-88 are turned on, and the pinto lines BO and Bl are discharged, and the pinto lines to which no MoS transistor is connected are not discharged. In other words, only the word whose comparison result is 1'' outputs a value to the bit line BO-BS, and the value to be output is programmed depending on the presence or absence of Mo3) transistors 40 to 42 connected to the B5 6 SOTO line in the 5th time, for example. Therefore, for example, all bit lines that output AO are programmed to output "O". Based on this value, it is detected that all comparison results are "o". If the comparison result of multiple words becomes "1", the AND of those addresses will be output, but this CAM does not handle data where the comparison result of multiple words becomes "L" at the same time. There is.

In practice, when decoding a variable length code, the comparison result is “1”.
” is only one word, and there is no problem with this restriction.The output of the Nant gate 37 is the comparison result output E.
This signal prohibits word line selection until QO to EQ255 are determined.

In addition, the values of bit lines BO to B8 of the ROM are determined by the output circuit 43.
is output as the address of AO-A8, and the output circuit 43
The details are shown in FIG. FIG. 6 is a circuit example for one bit line Bn, in which the output circuit 43 includes a launch circuit 44, a Nant gate 45, an in-hark circuit 46, and a Mo
It is composed of a 3h transistor 47. Now, when the value of the bit line Bn is "1", "0" is output from the Nant Gate 1.45 at the timing of CE=1, which is inverted by the inverter 46 and supplied to the gate of the MOS transistor 47. , one address An becomes "o".The reason why the output address An is an open drain is to allow a plurality of CAMs AO to A8 having the same configuration to be connected in common.

10 control circuit 11 controls data input/output,
The data transfer direction is as follows.

Write operation, comparison operation (WE+CB=1) external → Di,
DiX read operation (OE=1) Di, DiX-external non-operating state (WE+OB+CE=O) 0→D! , D I >C At the time of writing and comparison, external data is output to the non-inverted output Di and the inverted output DIX. During reading, the value of memory cell 1 or 2 is the non-inverted output Di and the inverted output Di.
The value is differentially amplified by a safety amplifier and output to the outside.

The above operation is similar to that of conventional static RAM.
It is exactly the same as the control circuit. Furthermore, when in the non-operating state, both Di and DiX output Q''.

This means that when inactive, MO3+-LandiskQ3,
This is to precharge EQj and ENEQX by turning off Q6.

Next, the effect will be explained.

FIG. 5 is a timing chart during a comparison operation of variable length codes. A variable length code is stored in the CAM in advance, and the variable length code is decoded by comparing it with the input variable length code.In this case, an individual comparison mask is applied to each bit of one word of data in the basic cell. The focus is held in 20 memory cells 2 and compared independently for each word using the comparison mask. Then, in the via t which can output the comparison result, memory cell 2 is “1”
It cannot be output when it holds "P0". Also, in the 16-bit comparison circuit group 13, the code data is held in memory cell 1 of the basic cell 20, and the comparison mask is stored in the memory. By holding in cell 2, two barracks are held, and when a variable length code is input from the outside, the comparison mask compares only the bits of a specific value with the variable length code and the code data, and displays the comparison result. is transmitted to the output code ROM 15, which determines which word out of the 256 circuits of the 16-bit comparison circuit group 13 is to be output, and outputs the output address AO~
A8 is taken out.

To do this, first, during the period of CB=0 (corresponding to the precharge period) before starting the comparison operation, the signal line EQj, the control line ENEQX, and the bit line Bn of the output code ROM 15 (
(corresponding to output address An) is executed. Next, when CE=1, the 0 control circuit 11 outputs external data to the data line Di, and outputs its inverted data to the other data line DiX. DI, D
When data is output to i The signal line EQj of the word that does not match (held in memory cell 1 of cell 20) is discharged, and is not discharged when they match.

On the other hand, the control line ENEQX is always discharged when the comparison is started, and it is determined that the output of the signal line EQj is determined when the discharge of ENEQX is completed. As a result, the word line of the output code ROM15 becomes valid, and the ROM in the output code ROM15 becomes valid.
Discharge of the focus line within the camera will begin. When the discharge of the bit line in the ROM is completed, a valid value is output as the output address An, and the variable length code is eventually decoded.

Specifically, for example, maximum length = 3 bits, total number of codes -
256, variable length code - 101 code, fixed length code =
When decoding to 11011100, the following value is CAM
write to.

88~AO data 110111000 00000000000001
01 Code 110111001 00000000
00000111 When decoding a comparison mask variable length code, only the bits of comparison master 1 are compared. Therefore, the data of the value (101) on the LSB side is input as the sign, and after comparison is performed, it is stored in A8 to A1 (
11011100] is output to achieve decoding of the variable length code.

Although the above embodiment is an example of 1 word - 16 bits and 256 words, the present invention is not limited to this, and it is possible to decode variable length codes with a maximum length of n bits and a total number of codes m. In that case, the 16-bit comparison circuit group 13 should have m comparison circuits, and the output code ROM 15 should have m words of output data memory.

〔Effect of the invention〕

According to the present invention, variable length codes can be decoded, and the performance of CAM can be improved.

[Brief explanation of drawings]

1 to 7 are diagrams showing one embodiment of the semiconductor memory device according to the present invention, FIG. 1 is a block diagram showing the overall configuration of the CAM, FIG. 2 is a configuration diagram of the 16-bit comparison circuit, Figure 3 is a circuit diagram of its basic cell, Figure 4 is a circuit diagram of its dummy comparison circuit, Figure 5 is a configuration diagram of its output code ROM, and Figure 6 is its output code ROM.
FIG. 7 is a timing chart of the comparison operation, and FIG. 8 is a circuit diagram of the basic cell of a conventional CAM. 13...16-bit comparison circuit group (comparison means),
13j...16-bit comparison circuit (comparison circuit),
14... Dummy comparison circuit, 15... Output code ROM (output data memory), 20... Basic cell, 21.23, ~29.31.40, ~42 .47...
...MO3+-Lanzisk, 22...Load element, 32-34.44...Launch circuit, 35.36
．． 46...Inhaak, 38.39...
・Noah gate, 43...Output circuit. Agent Patent Attorney Sada Igeta 1.2...Memory cell, 11...IO control circuit, 12...Address vocoder, 3 4 16-bit comparison of one embodiment Circuit diagram box diagram - Circuit diagram of the basic cell of the example

Claims (1)

[Scope of Claims] A semiconductor memory device in which external information and memory contents are compared by a comparing means, and when the comparison results in a match with the external information, address information whose contents match is outputted from the output data memory to the outside, the comparing means has m comparison circuits corresponding to the total number of codes m of external information, and the comparison circuit holds two parameters, code data and comparison mask, as memory contents, and has a maximum length of n bits. When external information with a total number m of codes is input from the outside, only bits of a specific value specified by the comparison mask are compared with the external information and the code data, and the comparison result is transmitted to the output data memory. The output data memory has m words of address information, and is configured to determine one corresponding word from among the m words as address information with matching contents based on the comparison results from the m comparison circuits. 1. A semiconductor memory device comprising: