JP2002197877A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which banks can be divided so as to be able to utilize a DUAL function to the utmost in accordance with the purpose of use of a user, or the like. SOLUTION: A memory section 13 of a semiconductor memory is constituted of a first to a fourth blocks. For example, a user inputs a write command from an IO terminal 42 and inputs a write address indicating a region in the first block from an AD terminal. A block decoder 11 turns off switches 201, 202, and 205, and turns on switches 203, 204, and 206 to 212. Then, a user inputs a read address indicating a region in the second to the fourth blocks from the AD terminal. In the semiconductor memory, write operation is performed as a bank A in the first block, read operation is performed as a bank B in the second to the fourth blocks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a simultaneous operation function (hereinafter referred to as a dual function) in which two banks operate independently. .

[0002]

2. Description of the Related Art At present, a flash memory is employed as a nonvolatile semiconductor memory device, and a dual-function product having a bank structure is mainly used (for example, Japanese Patent Application Laid-Open No. H11-86576). The dual function-equipped product has two banks, in which writing or erasing is performed in one bank and reading is simultaneously performed in the other bank.

FIG. 8 is a block diagram of a conventional nonvolatile semiconductor memory device (hereinafter referred to as a flash memory). The semiconductor memory device includes an address interface unit 15 to which an address is input, an operation control unit 16 that performs control based on a command, and a memory unit 1 including four blocks
4 and a data interface unit 17 for inputting and outputting data.

The switching circuit 21, the decoder 23, the memory cell group 24, and the memory control circuit 27 of the memory section 14
Constitute the first block. Similarly, second to fourth blocks are formed by a combination of each switching circuit, each decoder, each memory cell group, and each memory control circuit. In the memory unit 14, the first and second blocks are allocated as a bank A, and the third and fourth blocks are allocated as a bank B.

The command monitoring circuit 10 of the data interface unit 17 inputs a command permission signal 120 to the input / output control circuit 8 when each level of the input terminals 43 to 45 is in a predetermined state. When the command permission signal 120 is input, the input / output control circuit 8 uses the IO data 119 input from the IO terminal 42 via the IO buffer 9 as an operation command 118 and operates the internal control circuit 3 of the operation control unit 16.
To enter.

When the contents of the operation command 118 are writing or erasing, the internal control circuit 3 of the operation control section 16 inputs a write activating signal 104 to activate the write power supply generating circuit 4 or an erasing activating signal. 107 is inputted to activate the erasing power supply generating circuit 7 to execute the auto program. Thereafter, the internal control circuit 3 outputs the read activation signal 10
6 to activate the read power supply generating circuit 6.

The switching circuits 21, 22, 3 of the memory section 14
Activated power is input to 1 and 32.
The switching circuits 21 and 22 receive the bank A power signal 112 from the internal control circuit 3 of the operation control unit 16, and the switching circuits 31 and 32 receive the bank B power signal from the internal control circuit 3.
The power signal 113 is input.

The user issues a write command to the IO terminal 42.
, And a write address indicating an area in the bank A, for example, in the first block is input to the AD terminal 41, and write data is input to the IO terminal 42. After that, a read address indicating an area in the third block, for example, in the bank B is input to the AD terminal 41.

The AD buffer 1 of the address interface unit 15 latches a write address and inputs it to the bank decoder 2 as an input address 101. The bank decoder 2 inputs the bank A selection signal 102 to the AD buffer 1, the internal control circuit 3 of the operation control section 16, and the input / output control circuit 8 of the data interface section 17 based on the write address.

The AD buffer 1 has a bank A selection signal 10
When 2 is input, until the auto program ends
The write address is input to the decoders 23 and 26 of the memory unit 14 as the bank A address 114. Decoder 2
3 selects a designated area in the memory cell group 24 of the memory unit 14 based on the write address.

The input / output control circuit 8 of the data interface unit 17 latches the write data and inputs it as the bank A data 116 to the memory control circuits 27 and 28 until the write auto program ends. The memory control circuit 27 writes the write data to a designated area in the memory cell group 24.

The AD buffer 1 latches the write address and unconditionally inputs the read address indicating the area in the third block to the bank decoder 2 as the input address 101. The bank decoder 2 inputs the bank B selection signal 103 to the AD buffer 1, the internal control circuit 3 of the operation control unit 16, and the input / output control circuit 10 of the data interface unit 17. The AD buffer 1 sets the read address as the bank B address 115 to the memory unit 14.
To the decoders 33 and 36.

The decoder 33 of the memory unit 14 specifies a region in the memory cell group 34 based on the read address.
The memory control circuit 37 determines a level using a sense amplifier, and reads out a region in the specified memory cell group 34. The memory control circuit 37 inputs the read data as the bank B data 117 to the input / output control circuit 8 of the data interface unit 17.

Since the input / output control circuit 8 latches the write data, the bank B data 117 is unconditionally
The data 119 is output from the IO terminal 42 via the IO buffer 9.

The semiconductor memory device simultaneously executes a write operation for bank A and a read operation for bank B, thereby realizing a dual function.

[0016]

In the above-mentioned conventional flash memory, the dual function is realized while the number of blocks constituting the banks A and B is always fixed.

Incidentally, the required memory capacity of each bank is different depending on the use purpose of the flash memory. Even if a write address indicating an area in the first block is specified for the bank A, the read address for the bank B is set to the third and fourth blocks because the second block is fixedly allocated as the bank A. You can specify only the area inside.

The user uses a large-capacity flash memory when one of the memory capacities for performing the read operation or the write operation of each bank performing the dual operation is smaller than the required memory capacity. Must.

The present invention has been made in order to solve the above-mentioned problems of the conventional technology, and it is possible to separate a bank in which the dual function can be maximized according to a user's intended use. It is an object to provide a possible semiconductor memory device.

[0020]

In order to achieve the above object, a semiconductor memory device according to the present invention is characterized in that a memory area consisting of three or more blocks arranged sequentially is divided into two banks in block units, and In the semiconductor memory device having a dual function in which both banks operate independently based on the input first address and second address,
A block decoder that determines a bank separation position based on the first address.

According to the semiconductor memory device of the present invention, the block decoder determines the bank separation position on the basis of the first input first address, so that the first memory can be continuously used.
By inputting a second address specifying a block other than the block specified by the address, the dual function works effectively. In this case, a wide range of blocks can be specified as the second address.

In the semiconductor memory device according to the present invention, it is preferable that the block decoder determines a bank dividing position so that the second address can designate a widest address space. In this case, it is possible to divide the bank in which the dual function can be utilized to the maximum, according to the usage of the user.

Further, in the semiconductor memory device of the present invention, the memory area composed of three or more blocks sequentially arranged is divided into two banks in block units, and based on the first address and the second address sequentially inputted. A semiconductor memory device having a dual function in which both banks operate independently, comprising a bank separation control circuit for determining a bank separation position based on a separation command input by a user. .

In the semiconductor memory device of the present invention, since the bank separation control circuit determines the separation position based on the separation command and the separation information input by the user, the bank storage control circuit determines the separation position according to the usage of the user. Separation becomes possible.

It is also a preferred embodiment of the present invention that the collation data indicated by the write address or the erasure address is collated with the write data or the erasure data, and if the collation results match, the writing or erasing does not operate. In this case, unnecessary writing or erasing operations on the memory are suppressed, and thus there is an effect of preventing deterioration of the memory.

In the semiconductor memory device of the present invention, writing or erasing is performed based on the first address and reading is performed based on the second address, or the memory area is formed of a flash memory. Can also.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to the present invention will be described below with reference to the drawings based on an embodiment of the present invention. FIG. 1 is a block diagram of a flash memory according to a first embodiment of the present invention. For ease of explanation,
A two-bank memory composed of four blocks will be described.

The flash memory includes an address interface unit 15, an operation control unit 16, a memory unit 13, a data interface unit 17, and a block decoder 11.
It consists of. The address interface unit 15
It is composed of a D buffer 1 and a bank decoder 2, and has an AD terminal 41. The operation control unit 16 includes the internal control circuit 3,
It comprises a write power generation circuit 4, a verification power generation circuit 5, a read power generation circuit 6, and an erase power generation circuit 7.

The memory section 13 includes four switching circuits, four decoders, four memory cell groups, four memory control circuits, and twelve switches. Each memory cell group is composed of flash memory cells.

The switching circuit 21, the decoder 23, the memory cell group 24, and the memory control circuit 27 constitute a first block. Similarly, by the combination of each switching circuit, each decoder, each memory cell group, and each memory control circuit,
Second to fourth blocks are formed.

FIG. 2 is a circuit diagram showing one of the switches 201 to 212 of FIG. Each switch 201-21
Reference numeral 2 denotes a transfer gate having a p-channel transistor Qp1, an n-channel transistor Qn1, and an inverter IV1.

The distance between the terminals a and b of each switch is c
It turns on when the terminal is at H level, and turns off when the terminal c is at L level.

Switches 201, 203, 207, and
209 are sequentially connected, and when one of them is turned off, the bank A power signal 112 and the bank B power signal 113 are separated at that position. Switches 202, 20
4, 208 and 210 are connected sequentially,
When one of them turns off, the bank A address 1
14 and the bank B address 115 are separated. The switches 205, 206, 211, and 212 are sequentially connected, and when one of them is turned off, the bank A data 116 and the bank B data 117 are separated at that position.

Selection inputs of the switching circuits 21 and 22 are connected to terminals a of switches 201 and 203, respectively. Select inputs of the switching circuits 31 and 32 are connected to terminals b of the switches 207 and 209, respectively.

The address inputs of the decoders 23 and 26 are:
The switches 202 and 204 are connected to terminal a, respectively.
The address inputs of the decoders 33 and 36 are
8 and 210, respectively.

Data inputs and outputs of the memory control circuits 27 and 28 are connected to terminals a of switches 205 and 206, respectively. The data input / output of the memory control circuits 37 and 38
The switches 211 and 212 are respectively connected to the terminal b.

The data interface unit 17 includes an input / output control circuit 8, an IO buffer 9, and a command monitoring circuit 10, and has an IO terminal 42, a CE terminal 43, a WE terminal 44, and an OE terminal 44.

The AD buffer 1 receives an address designating a specific area from the AD terminal 41, and inputs the input address to the bank decoder 2 and the block decoder 11 as an input address 101. The AD buffer 1 has a function of latching an input address as a write address or an erase address immediately after the start of a write operation or an erase operation.

The block decoder 11 receives the input address 1
The bank is divided based on the first address which is input first as 01. In the memory unit 13, the left block group is assigned as the bank A and the right block group is assigned as the bank B from the bank separation position.

The block decoder 11 checks which block the area indicated by the first address is, and determines a bank separation position such that the number of blocks in one bank including the specified block is as small as possible. . In this case, the number of blocks in the other bank is as large as possible, so that the next input second address can specify the widest address space.

The block decoder 11 inputs a division position signal 128 indicating the division position of the bank to the bank decoder 2. The block decoder 11 controls the switches 201 to 212 by inputting an H level signal to the c terminal of each switch to be turned on and inputting an L level signal to the c terminal of each switch to be turned off. Block decoder 11
Turns off the switch corresponding to the bank separation position.

The bank decoder 2 outputs the separation position signal 12
8, it is determined whether the area specified by the input address 101 is the bank A or the bank B.
For bank A, a bank A selection signal 102 is generated. For bank B, a bank B selection signal 103 is generated.
Buffer 1, internal control circuit 3, and input / output control circuit 8
To enter.

When the bank A selection signal 102 is input to the input address, the AD buffer 1 inputs the address as the bank A address 114 to the terminal a of the switch 202, and receives the bank B selection signal 103. Is input to the terminal b of the switch 210 as the bank B address 115.

Transfer data is input / output to / from a microcomputer (not shown) from the IO terminal 42 of the IO buffer 9, and the transfer data is input / output to / from the input / output control circuit 8 as IO data 119.

The command monitoring circuit 10 has a CE terminal 43,
The state of each level of the WE terminal 44 and the OE input terminal 45 is monitored, and when the OE terminal 45 goes high and the CE terminal 43 and the WE terminal 44 go low, the command enable signal 120 is sent to the input / output control circuit. Enter 8

The input / output control circuit 8 receives the command enable signal 1
When 20 is input, the IO data 119 is input to the internal control circuit 3 as an operation command 118.

The internal control circuit 3 recognizes the contents of the operation command 118 and, based on the bank A selection signal 102 or the bank B selection signal 103, determines whether the bank A and the bank B are to write, read, collate or erase. It recognizes whether it is the operation | movement of each.

The internal control circuit 3 switches the bank A power supply signal 112 indicating the type of operation power supply for the bank A to the switch 2
01 to the terminal a of the switch 209, and outputs the bank B power signal 113 indicating the type of operation power supply to the bank B
Input to the terminal.

The internal control circuit 3 outputs the bank A power signal 11
Each power supply generation circuit is activated according to the type of operation indicated by 2 or bank B power supply signal 113. In the case of a write operation, a write activation signal 104 is input to the write power supply generation circuit 4, and in the case of a collation operation, the collation activation signal 105 is input to the collation power supply circuit 5, and in the case of a read operation, read activation is performed. Read signal 106 to read power supply generating circuit 6
In the case of an erase operation, the erase activation signal 107 is input to the erase power supply generation circuit 7.

Write power supply generation circuit 4 is activated when write activation signal 104 is input, and generates write power supply 108. The collation power generation circuit 5 outputs the collation activation signal 10
When 5 is input, it is activated and the collation power supply 109 is generated. Read power supply generating circuit 6 provides read activation signal 106
Is activated, and a read power supply 110 is generated. The erase power supply generation circuit 7 is activated when the erase activation signal 107 is input, and generates the erase power supply 111.

Switching circuits 21, 22, 31, and 32
Are based on the bank A power signal 112 or the bank B power signal 113 from the selection input, and based on the write power 108, the verification power 109, the read power 110, or the erase power 111
Of the decoders 23 and 2
6, 33 and 36, respectively.

One of the decoders 23, 26, 33, and 36 receives the bank A address 1 from the address input.
Based on the address 14 or the bank B address 115, two areas corresponding to the bank A or the bank B are selected by referring to the memory cell groups 24, 25, 34, and 35, respectively. The decoders 23, 26, 33, and 36
The selected operating power is supplied to the memory control circuits 27, 28, 3
7 and 38 respectively.

The first to fourth blocks perform writing when the write power supply 108 is supplied based on the bank A address 114 or the bank B address 115, and
When 09 is supplied, collation is performed. When the read power supply 110 is supplied, reading is performed. When the erasing power supply 111 is supplied, erasing is performed.

The memory control circuits 27, 28, 37, and
38 has a sense amplifier and a write circuit. The write circuit supplies a write power supply 108 to the drain of each memory cell in the selected region and writes write data during a write operation. At the time of a read operation, the sense amplifier determines the level of the holding voltage of each memory cell in the selected region and outputs the same as read data. Memory control circuits 27, 28, 3
7 and 38 input and output write data or read data as bank A data 116 or bank B data 117.

The input / output control circuit 8 outputs the bank A data 11
6 is input / output to / from the terminal a of the switch 205, and bank B data 117 is input / output to / from the terminal b of the switch 212.

The input / output control circuit 8 outputs the bank A data 11
6 or bank B data 117 is input / output to / from the IO buffer 9 as IO data 119. IO buffer 9
Inputs / outputs the contents of the IO data 119 to / from the microcomputer via the IO terminal 42.

Hereinafter, the operation of separating the banks will be described. For example, using a microcomputer, the user inputs a write command to the IO terminal 42 and inputs a write address indicating an area in the first block to the AD terminal 41 as a first address. Thereafter, a read address indicating an area in the third block is input to the AD terminal 41 as a second address.

The block decoder 11 includes a switch 20
1, 202 and 205 are turned off, and the switch 203,
204 and 206 to 212 are turned on. The first block is allocated to the bank A for the write operation, and the second to fourth blocks are allocated to the bank B for the read operation.

When recognizing that the contents of the operation command 118 from the user are writing, the internal control circuit 3 executes an automatic program.

FIG. 3 is a flowchart of the auto program. The auto program is executed when the content of the input command is writing or erasing. The writing operation or the erasing operation differs only in the electrical operation from each other, and is performed on the area indicated by the address input immediately after the command input. In addition, an erasing operation can be performed on a wide area in a block unit.

The AD buffer 1 and the input / output control circuit 8
The contents of the latch are cleared, the AD buffer 1 latches the write address, and the input / output control circuit 8 latches the write data (step S11). The verification power supply generation circuit 5 is activated to generate a bank A power supply signal 112 indicating a verification operation, and input a write address to the decoder 23. The collation data is read from the area in the memory cell group 24 indicated by the write address, and a collation operation for comparing the collation data with the write data is performed (step S12).

The memory of the memory section 13 deteriorates as the number of write operations and erase operations increases. The collation operation has an effect of preventing the memory from deteriorating by suppressing unnecessary operation of overwriting the same value at the time of writing or erasing.

If the collation result in step S12 is "match", the automatic program ends. If the collation result is “mismatch”, the write power supply generation circuit 4 is activated, a bank A power signal 112 indicating a write operation is generated, and write data is written to the area in the memory cell group 24 indicated by the write address ( Step S13). Thereafter, the processing is continued from step S12.

The bank decoder 2 receives the input address 101
When the write address is input as, a bank A selection signal 102 for designating the first block is generated based on the contents of the write address. AD buffer 1 is connected to bank A
When the selection signal 102 is input, the bank A address 114 is generated until the auto program ends.

The input / output control circuit 8 outputs the bank A selection signal 1
02, the write data is transferred to bank A data 1
As 16, input to the first block until the end of the auto program.

The bank A power signal 112 is supplied to the switching circuit 2
1, and the bank B power signal 113 is input to the switching circuits 22, 31, and 32. The bank A address 114 is input to the decoder 23, and the bank B address 115 is input to the decoders 26, 33, and 36. Bank A data 116 indicates write data,
The data is input from the input / output control circuit 8 to the memory control circuit 27. Bank B data 117 indicates read data, and is input from the memory control circuit 37 to the input / output control circuit 8.

Thereafter, during the execution of the auto program, an address indicating the area of the third block is input to the AD buffer 1 as the second address. Since the second address is unconditionally recognized as a read address, a read operation is performed on the area of the third block of the bank B.

In the first block, writing is performed as a bank A by an automatic program. The second to fourth blocks are read as bank B.

According to the above embodiment, the block decoder determines the partitioning position of the bank on the basis of the first input first address, so that the blocks other than the block designated by the first address are continuously determined. By inputting the designated second address, the dual function works effectively. In this case, a wide range of blocks can be specified as the second address.

FIG. 4 is a block diagram of a flash memory according to the second embodiment of the present invention. In the present embodiment, instead of performing the bank separation based on the write address (first address) in the previous embodiment, the present embodiment is based on the separation command and the separation position information input by the user. The bank is separated.

The flash memory comprises a block decoder 1
In place of 1, a bank separation control circuit 12 is provided. Since all operations other than the bank separation operation are the same as those of the above-described embodiment, only the bank separation operation will be described.

FIG. 5 is a block diagram of the bank separation control circuit 12. The bank separation control circuit 12 includes a latch circuit 51, a bank cut circuit 52, and a memory cell control circuit 5.
3, 54, memory cells 55 and 56, a decoder 57, and a switching circuit 58.

The switching circuit 58 is provided with a write power supply 108 and a verification power supply 1 based on the input power supply signal 121.
09, the read power supply 110, or the erase power supply 111 is selected and supplied to the decoder 57.

The memory cell control circuits 53 and 54, the memory cells 55 and 56, and the decoder 57 constitute a memory block having a fixed address. The memory block is
Two bits of information can be stored.

The decoder 57 supplies the selected operation power supply to the memory cell control circuits 53 and 54, the memory cell 55,
To 56. Since the address is fixed, the decoder 57 does not need to input an address to the memory cells 55 and 56.

The memory cells 55 and 56 are constituted by flash memories. Memory cell control circuits 53 and 54
Has a sense amplifier and a write circuit, and performs each operation on the memory cells 55 and 56, respectively.

The memory cell control circuit 53 writes the information of the least significant bit of the separation data 122 into the memory cell 55, and stores the information stored in the memory cell 55 into the bank cut circuit 52.
To the d terminal. The memory cell control circuit 54 stores information of the most significant bit of the separation data 122 into the memory cell 56
And the storage information of the memory cell 56 is input to the e terminal of the bank cut circuit 52. The separation data 122 is
This is 2-bit information. As for the level of the signal line, “1” is H
“0” corresponds to the L level.

The terminal f, the terminal g of the bank cut circuit 52,
The h terminal and the i terminal are the j terminal of the latch circuit 51, k
Terminal, l terminal, and m terminal.

The latch circuit 51 inputs a switch signal 124 from the q terminal to the switches 201, 202, and 205, and a switch signal 125 from the p terminal to the switch 20.
3, 204 and 206, and the switch signal 12
6 from the o terminal to switches 207, 208 and 211
And the switch signal 127 is supplied from the n terminal to the switch 2
09, 210, and 212.

FIG. 6 is a circuit diagram of the bank cut circuit 52 of FIG. The bank cut circuit 52 includes an inverter IV2
To IV9 and two-input NAND gates ND1 to ND4. The first input of the NAND gate ND1 is a d terminal,
The input of the inverter IV2, the first input of the NAND gate ND3, and the input of the inverter IV4. NAN
The second input of the D gate ND1 is the e terminal, the NAND gate N
The second input of D2, the input of inverter IV3, and the input of inverter IV5. First of NAND gate ND2
The input is connected to the output of inverter IV2. NAND
The second input of gate ND3 is connected to the output of inverter IV3. A first input of the NAND gate ND4 is connected to the output of the inverter IV4. The second input of the NAND gate ND4 is connected to the output of the inverter IV5.

The output of NAND gate ND1 is connected to terminal f via inverter IV6. NAND gate ND2
Is connected to the g terminal via the inverter IV7. The output of NAND gate ND3 is connected to terminal h via inverter IV8. The output of NAND gate ND4 is connected to terminal i via inverter IV9.

The bank cut circuit 52 outputs an f terminal, a g terminal, an h terminal,
Or, a decoder that sets one of the four i terminals to H level and sets the other three to L level.

FIG. 7 is a circuit diagram of the latch circuit 51 of FIG. The latch circuit 51 includes inverters IV10 and 4
It is composed of two latch portions 61 to 64. Latch portions 61-
Reference numeral 64 includes inverters IV11 and IV12 and n-channel transistors Qn2 and Qn3.

The latch inputs of the latch units 61 to 64 are connected to the input of the inverter IV11 via the transistor Qn2 and
Connected to the output of inverter IV12. Inverter IV11
Is connected to the ground via the transistor Qn3. The output of the inverter IV11 and the inverter IV12
Are connected to the latch outputs of the latch units 61 to 64.

The gates of the transistors Qn2 of the latch sections 61 to 64 are all connected to the r terminal and the input of the inverter IV10. The transistors Qn3 of the latch units 61 to 64
Are all connected to the output of the inverter IV10.

The latch inputs of the latch units 61, 62, 63, and 64 are connected to the j terminal, k terminal, l terminal, and m terminal, respectively, and the latch units 61, 62, 63, and 6 are connected.
4 are output from the n terminal, o terminal, p terminal, and q terminal.
Each is connected to a terminal.

When the r terminal goes high, the latch circuit 51 latches signals input from the j terminal, the k terminal, the l terminal, and the m terminal, and outputs the latched signal and the inverted signal to the n terminal. Output from the o terminal, the p terminal, and the q terminal, respectively.

The latch circuit 51 has an internal signal generation circuit (not shown). The internal signal generation circuit inputs a separation position signal 128 corresponding to the latched content to the internal control circuit 3.

For example, the microcomputer inputs a separation command for requesting bank separation from the IO terminal 42, and then inputs separation position information from the IO terminal 42. “0” is designated as the value of the separation position information.

The values of the separation position information are “0”, “1”,
If "2" or "3" is specified, bank A
Blocks, first and second blocks, first and second blocks,
Alternatively, the bank B is set as the first to third blocks, respectively, and the bank B is set as the second to fourth blocks, the third and fourth blocks, the third and fourth blocks, or the fourth blocks, respectively.

When the isolation command is input as the operation command 118, the internal control circuit 3 activates the write power generation circuit 4 and inputs the first isolation power signal 121 to the bank isolation control circuit 12. The first isolated power signal 121 indicates a write operation. Input / output control circuit 8
Inputs the input isolation information to the bank isolation control circuit 12 as isolation data 122. The bank separation control circuit 12 performs a write operation. Memory control circuit 53
And write the separation information “0” into the memory cells 55 and 56, respectively.

Internal control circuit 3 includes read power supply generation circuit 6
And inputs the second separation power supply signal 121 to the bank separation control circuit 12. The second isolated power signal 121 indicates a read operation. Bank separation control circuit 1
2 performs a read operation. The memory control circuit 53 transfers the read data from the memory cell 55 to the bank cut circuit 52.
, And the memory control circuit 54 inputs the read data from the memory cell 56 to the e terminal of the bank cut circuit 52.

The bank cut circuit 52 sets the f terminal, the g terminal, and the h terminal to L based on the read data of “0”.
Level, and the i terminal becomes H level. Switching circuit 5
When the read operation 8 recognizes the read operation based on the separation power supply signal 121, it inputs an H-level latch signal 123 to the r terminal of the latch circuit 51. The latch circuit 51 receives the L-level switch signal 124 and the H-level switch signals 125 to 127.

In the above-described embodiment, since the bank separation position is determined by the write address of the auto program, the bank separation position may change every time the auto program is executed. In the present embodiment, since the division position of the bank is determined by the division command and the division position information input from the user, the division of the bank which is not intended by the user does not occur.

According to the above-described embodiment, the bank separation control circuit determines the separation position based on the separation command and the separation information input by the user. Separation becomes possible.

In the above embodiment, the memory unit 13
Has been described as being composed of four blocks, but if the number of blocks is increased, more optimal bank separation can be performed.

As described above, the present invention has been described based on the preferred embodiment. However, the semiconductor memory device of the present invention is not limited to the configuration of the above-described embodiment, but the configuration of the above-described embodiment. Various modifications and changes of the present invention are also included in the scope of the present invention.

[0098]

As described above, in the semiconductor memory device according to the present invention, it is possible to divide the bank in which the dual function can be utilized to the maximum, according to the usage of the user, and so the product is mounted. The circuit board can be easily designed, and the cost and the size of the circuit board can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a flash memory according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing one of switches 201 to 212 in FIG.

FIG. 3 is a flowchart of an auto program.

FIG. 4 is a block diagram of a flash memory according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a bank separation control circuit 12.

6 is a circuit diagram of the bank cut circuit 52 of FIG.

FIG. 7 is a circuit diagram of the latch circuit 51 of FIG.

FIG. 8 is a block diagram of a conventional flash memory.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 AD buffer 2 bank decoder 3 internal control circuit 4 write power generation circuit 5 verification power generation circuit 6 read power generation circuit 7 erase power generation circuit 8 input / output control circuit 9 IO buffer 10 command monitoring circuit 11 block decoder 12 bank separation control Circuits 13, 14 Memory unit 15 Address interface unit 16 Operation control unit 17 Data interface unit 21, 22, 31, 32, 58 Switching circuit 23, 24, 33, 34, 57 Decoder 24, 25, 34, 35 Memory cell group 27 , 28, 37, 38 Memory control circuit 41 AD terminal 42 IO terminal 43 CE terminal 44 WE terminal 45 OE terminal 51 Latch circuit 52 Bank cut circuit 53, 54 Memory cell control circuit 55, 56 Memory cell 61-64 Latch section 101 Input address 102 Bank A selection signal 103 Bank B selection signal 104 Write activation signal 105 Verification activation signal 106 Read activation signal 107 Erase activation signal 108 Write power supply 109 Reference power supply 110 Read power supply 111 Erase power supply 112 Bank A power supply signal 113 Bank B Power signal 114 Bank A address 115 Bank B address 116 Bank A data 117 Bank B data 118 Operation command 119 IO data 120 Command enable signal 121 Isolation power signal 122 Isolation data 123 Latch signal 124 to 127 Switch signal 128 Isolation position signal Qp1 P-channel type transistor Qn1, Qn2 N-channel type transistor INV1-INV12 Inverter ND1-ND4 NAND gate

Claims (6)

[Claims] 1. A memory area composed of three or more blocks arranged sequentially is divided into two banks in block units, and both banks are independently controlled based on a first address and a second address sequentially input. An operating semiconductor memory device having a dual function, comprising: a block decoder that determines a bank separation position based on the first address. 2. The semiconductor memory device according to claim 1, wherein said block decoder determines a bank partitioning position so that said second address can designate a widest address space. 3. A memory area composed of three or more blocks arranged sequentially is divided into two banks in block units, and both banks are independently controlled based on a first address and a second address sequentially input. 1. A semiconductor memory device having an operating dual function, comprising: a bank isolation control circuit for determining a bank isolation position based on an isolation command input by a user. 4. The semiconductor memory device according to claim 1, wherein writing or erasing is performed based on said first address, and reading is performed based on said second address. 5. Matching the collation data indicated by the write address or erase address with the write data or erase data,
5. The semiconductor memory device according to claim 4, wherein said writing or erasing does not operate when said collation results match. 6. The semiconductor memory device according to claim 1, wherein said memory area is constituted by a flash memory.