JPH07192477A - Retrieval memory device, retrieval memory, data retrieval device and method for using retrieval memory - Google Patents

Abstract

PURPOSE:To enable contents to be referred, and coincident key string data set to be efficiently accessed by comparing string data externally inputted with data in each column block, and performing coincidence retrieving marking some column blocks. CONSTITUTION:In writing data in a memory cell array, some word line is selected and a cell is connected to a bit line, pairs of IO line pairs of 100 to 107, /100 to/107 are connected to bit line pairs of B0-B7, /B0-/B7. Write-in is serially performed for cells belonging to a selected word line by 8 bits. After selecting a word line, and after an IOGON signal is made to be in H state and CRC is reset, a SAC signal is made to be in a H state of a pulse like and all cyclic write-in circuits CRC are made to be in a selected state. Next, when a CR signal is given in pulse like, an IOG signal is made to be in a H state during being in a H state of the CR signal, a pair of I/O line is connected to a bit line. That is, the circuits CRC are selected sequentially for each pulse of the CRC and connected sequentially to the I/O line by light columns. Data is given to the I/O line and written in a cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a search memory and a search data transfer device, and particularly to a memory capable of accessing a large amount of contents for efficient access of a matched data set of key string data and a large capacity. Search memory device and search data transfer device.

[0002]

2. Description of the Related Art With the recent increase in the capacity of semiconductor memories, the amount of data handled by information devices has become enormous. In such a situation, the importance of so-called data search for finding out data satisfying the condition from the accumulated data is increasing.

On the other hand, in a general memory device, as shown in FIG. 20, the address Add and the cell data CD have a one-to-one correspondence. Therefore, in order to retrieve data, all addresses are accessed. It is necessary to read the cell data and search for the data. However, as the memory capacity increases, the time required for memory access and data search increases accordingly.

In order to solve such a situation, in recent years,
Content access access methods have been proposed. In this method, a part of a group of stored data in the memory is used as key string data, and when the memory is accessed, this key string is given, and only the group of data which matches this is accessed.

FIG. 21 is an explanatory view showing the concept of such content reference access.

The key string data KSD is, for example, 2
It can be set arbitrarily from the 8th power of data. What kind of data set DS is associated with this one key is completely arbitrary. For example, the key string data can be associated with the data set DS0 within the dotted line and the data set DS1 within the solid line. in this way,
Reading of the data set stored by association is
This is done by providing the key string data, rather than reading all the data in memory.

As described above, a dynamic memory of a content reference access type suitable for data retrieval of a large capacity memory is described in US Pat. No. 4,989,180, which is entitled "Dynamic Memory with Log."
ic-In-Refresh ".
What is disclosed here is that when a dynamic memory is refreshed, a data search is also performed using key string data, and if a match is detected, the specific bit of the data is used as a mark bit to identify the specific data. It is to write it down. Also, when reading data, this bit is detected and read, and when there are a plurality of matching data in the search row, the priority circuit selects and outputs only one matching data. For the second and subsequent matching data, , The idea of reselecting a row and reading it is shown.

[0008]

The conventional memory device has the following problems.
Since it is configured as described above, even if it is technically established, a large-capacity memory, for example, a DRAM
Etc. is difficult to apply immediately. In addition, when there are a plurality of pieces of data to be read in the same row, there is also a problem that the reading efficiency becomes extremely poor.

The present invention has been made in view of the above,
An object of the present invention is to provide a large capacity memory device and data transfer device capable of content reference access and more efficient access of a matched data set of key string data.

[0010]

In order to achieve the above object, according to the present invention, a memory cell array composed of a plurality of memory cells arranged in a matrix is divided into a plurality of column blocks, and from the outside. The input string data is compared with the data in each column block, some of the column blocks are marked according to the comparison result, and the data in the marked column blocks are sequentially transferred and output. A search memory device including search data transfer means is provided.

[0011]

By using the above means, the string data input from the outside is compared with the data in each column block, and some of the column blocks are marked according to the result of the comparison. Is done. Then, in the second step, the search data transfer means sequentially transfers and outputs the data in the column block marked with this mark. As a result, the content reference access can be performed, and the matching data set of the key string data can be efficiently accessed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a search system using a search memory according to the first embodiment of the present invention. This search system is composed of a search memory device 100 and a search control circuit 200, both of which are connected by an external bus 108.

The search memory device 100 comprises a memory cell array 101, a search data transfer circuit 102, a row decode circuit 103, a data input / output circuit 104 and a control circuit 105. The memory cell array 101 and the search data transfer circuit 102 are divided into a plurality of column locks CB, and data transfer is performed for each column block. Further, the search data transfer circuit 102 and the data input / output circuit 104 are connected by the data bus 106 and the string data bus 107.

The memory cell array 101 is formed by arranging random access memory cells such as dynamic cells and static cells or mask ROM cells, and writable / erasable nonvolatile memory cells in a matrix.

The search data transfer circuit 102 compares read data for each column block based on the string data input from the outside or obtained in the previous cycle, stores the comparison result, and stores the comparison result. Data transfer is performed based on the comparison result. This data transfer is sequentially performed based on the clock signal supplied from the control circuit 105. This data transfer is not performed for all column block data, but is partially performed based on the comparison result. As will be described later, the fact that the search data transfer circuit 102 partially transfers the data based on the comparison result contributes to the improvement of the search speed.

The control circuit 105 is a row decode circuit 103.
Control of the addressing operation of the search data transfer circuit 102
Control of various operations, operation control of the data input / output circuit 104, and the like. In particular, a clock signal is generated based on a signal given from the search control circuit 200, and the data transfer of the search data transfer circuit 102 is sequentially controlled.

The search control circuit 200 uses the register file 2
01, a string data register 202, a data input / output circuit 203, and a control circuit 204. The register file 201 sequentially stores the search data sequentially transferred by the search data transfer circuit 102 in the search memory device 100. The string data register 202 holds the string data supplied to the search data transfer circuit 102. The data input / output circuit 104 interfaces with the external data bus 108. The control circuit 204 controls the register file 201, the string data register 202, the data input / output circuit 203, and the like, and gives a control signal to the control circuit 105 in the search memory device 100. With the above configuration, the search control circuit 200 provides the search memory 100 with the string data, receives the search data sequentially, and stores the internal register file 201.
In some cases, the string data of the next cycle is selected from the search data stored in the register file 201.

Subsequently, the search data transfer circuit 102 is shown in FIG.
The circuit configuration of is shown. As described above, the search data transfer circuit is composed of column search units belonging to each column block CB. Each column search unit or each column block has an 8-bit data bus IO (extended data bus 106 in FIG. 1) and an 8-bit string data bus SB (extended string data bus 107 in FIG. 1). Connected with.

Each column block CB includes an 8-bit column data line bundle 303 connected to a memory cell, and this column data line bundle 303 includes a 1-bit upper column data line 3031 and a 7-bit lower column data line bundle 303.
Composed of two. Each column block CB further includes a column gate circuit 301, a cyclic read circuit CRC, a string bit register SBR, and a bit comparison / mark circuit 3.
It consists of 02.

The column gate circuit 301 is a data bus IO.
And column data bundle.

The cyclic read circuit uses the column gate circuit 301 based on the data of the 1-bit upper column data line and the signal CR supplied from the column block adjacent to the upper side.
To control.

The string bit register SBR is composed of an 8-bit register string, and has a string data bus S
The data of B is fetched, and this is temporarily held.

The bit comparison / mark circuit 302 compares the 8-bit data of the column data line bundle 303 with the 8-bit string data held in the string bit register SBR, and the comparison result is the column data line bundle 303.
Write back to. There are various methods for this write-back method as will be described later, but as a typical method, when they match, the "H" data is transferred to the next upper column (in the column block adjacent to the lower side in FIG. 2). When writing to the data line 3031 ', if there is a match, "H" data may be written to its own column data line 3031 (of the column block to which the column search unit belongs). The bit comparison / mark circuit 302 is composed of a bit comparator BCM and a string match mark circuit SMM as described later.

FIG. 3 is a block diagram of a memory device according to an embodiment of the present invention. As shown in FIG. 3, bit line B
Each of 0 to B7 has an 8-bit structure and is paired with each of bit lines / B0 to / B7. These 8-bit bit line pairs form one column block CB1. In FIG. 2, the column data line bundle 303 corresponds to this 8-bit line pair, the upper column data line 3031 corresponds to the bit line pair B0, / B0, and the lower column data line bundle 3
032 corresponds to the bit line pairs B1, / B1 to B7, / B7, respectively. Of these, the key string data is 8 bits, and the 8-bit data set following this key string data is one content data belonging to the key string. The 9th bit corresponds to the upper column data line 3031 'of the next column data line bundle 303' and is also used as an attribute bit (that is, a mark bit) corresponding to the data of the column data line bundle 303.

The dynamic cell is not shown in the figure.

A sense amplifier S is provided for each column line.
A and the equalizer EQ are connected.

On the other hand, the data bus IO is for 8 bits and constitutes a pair with IO0, / IO0 to IO7, / IO7, and these IO line pairs are IOG (In
It is connected to the bit line pair through a gate G1 controlled by a putOutput Gate signal. These gates form a column gate circuit 301. The cyclic read circuit CRC controls ON / OFF of these gates G1. In this cyclic read circuit CRC, IOGON (I
O Gate ON) signal, SAC (Serial A)
Ccess) signal is provided. A CR signal is input to the cyclic read circuit CRC from another cyclic read circuit (cyclic read circuit belonging to the upper column block in the figure) CRC, and the next cyclic read circuit (which belongs to the lower column block in the figure). Cyclic read circuit) Outputs a CR 'signal to CRC'.

On the other hand, the string bit register SBR is provided corresponding to each bit line pair B0 to B8. As the key string data, 8 bits of the key string bit data lines SB0 to SB7 correspond. The string bit register SBR has an STR (String).
(TRTransfer) signal is supplied and key string data is taken in from the key string bit data lines SB0 to SB7.

A bit comparator BCM is connected to the string bit register SBR. The bit comparator BCM has a CMP (CoMPare) signal and a CMPTR (CoMPre) signal.
are data transfer) signal.

The bit comparator BCM provides the string match mark circuit SMM with BMTC (Bit MaTCh) i.
Connect (0-7) signal. The string match mark circuit SMM receives the SMTC (String MaTCh) signal from the other string match mark circuit SMM, and outputs S to the other string match mark circuit SMM.
Output the MTC 'signal. On the other hand, in the string match mark circuit SMM, the / RSMK signal, which is an inverted signal of the RSMK (ReSet MarK) signal, and the RS (ReSe
t) signal, which is the inverted signal of the MKCMP (MarK CoMPare) signal, / MKCMP signal, MKCNT (M
arK CoNTent) signal which is the inverted signal of / MK
The CNT signal is input. String match mark circuit S
The MMs are connected by the SMTC 'signal.

It should be noted that this memory device does not require a column decoder. As shown in FIG. 1, the row decode circuit decodes an address supplied from inside or outside the memory chip to activate and select a word line in a certain row.

Next, the operation of the above-mentioned configuration will be described.

First, the data write operation to the memory cell array will be described.

In writing data to the cell array, a certain word line is selected to connect the cell and the bit line, and the IO line pairs IO0 to IO7 and / IO0 to / IO7 are connected to the bit line pairs B0 to B7 and / B0. ~ / B7. Since it is assumed in FIG. 3 that 8 bits are simultaneously written, there are IO line pairs for each bit.

Writing is serially performed on the cells belonging to the selected word line in units of 8 bits. After selecting the word line, the IOGON signal is once set to the "H" level to reset the CRC, and then the SAC signal is pulsed to the "H" level to bring all the cyclic read circuits CRC into the selected state. After that, when the CR signal is applied in a pulsed manner, the IOG signal becomes "H" level while the CR signal is at "H" level, and the I / O line pair and the bit line are connected. That is, the cyclic read circuit CR is provided for each pulse of the CR signal.
C is sequentially selected, and eight columns are sequentially connected to the I / O line. In this state, data can be written in the cell by giving appropriate data to the I / O line pair.

Through the above operation, when writing data to the memory cell, the key string data is also stored in association with the data set. Here, the key string data is data used as a data search key and is located at the beginning of the normal data structure. That is, assuming that the column block 1 corresponds to the key string data, the column blocks 2, 3, 4, etc. are the searched data. Further, if the column block 5 corresponds to the key string data, the column block 6,
7 and 8 are the searched data.

Next, the data search will be described.

At the time of writing data, the key string data is stored in the memory cell in association with the data set. A preparatory operation for searching and reading this will be described.

First, the STR signal is set to "H" level,
The string bit register SBR corresponding to the string bits 0 to 7 is opened, and in this state, the key string data to be searched is applied to the string bit data lines SB0 to SB7. As a result, the key string data is written in the string bit register SBR. The string bit register SBR is composed of 8 bits,
In this case, the same key string data is written in all 8-bit string bit registers SBR.

Since the search is carried out row by row in the cell array, as shown in FIG.
When the AM cell array is used, the cell data can be refreshed at the same time. As for the operation sequence, first, as in the conventional DRAM, a certain row is selected, the word line is activated, and the cell data is sensed by the sense amplifier SA. Next, the data determined on the bit lines Bi and / Bi is taken into the bit comparator BCM by setting the CMPTR signal to the “H” level in a pulse form. Next, by setting the CMP signal to the “H” level, the data determined on the bit line of the column and the data of each bit written in the string bit register SBR are compared. If the compared bit data match, the bit comparator BCM outputs / BMT.
The Ci signal changes to "L" level. When all of the 8 bit string bits match, the SMTC signal from the string match mark circuit SMM becomes "H" level.
This signal is supplied to the next string match mark circuit SMM as an SMTC 'signal.

Here, the operation is divided into two types depending on how the match search result is used. First, the data search belonging to the key string data will be described, and then the search for the column having the key string data will be described.

(1) Retrieval of data belonging to key string data When data matching the key string is found as a result of the search, it is adjacent to the matching key string data 8
It can be seen that the bit is the data that belongs to it. In this case, you need to mark this dataset. In this embodiment, the mark bit is the 0th bit in 8-bit units. Therefore, assuming that the first 8 bits (0 to 7) shown in the figure are the key string data, the SMTC 'signal becomes the "H" level, and the string match marks of the columns B8 and / B8 in FIG. Provided to the circuit SMM. Here / MKCNT signal is "L"
When the level is set, "1" is written in the B8 / B8 column. Writing "1" like this
This is performed simultaneously in the column blocks to which all matching strings in the selectively activated row belong.

(2-1) Retrieval of column having key string data (set of marks) When rewriting a part of the key string data or changing and rewriting the matched data set itself, there is the matched key string data. The column must be marked. At this time, the string match mark circuit SMM writes the "1" mark in the 0th bit of the matched 8th bit by using the SMTC 'signal created by itself. Therefore, the / MKCMP signal is set to the "L" level instead of the / MKCNT signal.

(2-2) Retrieval of column having key string data (reset of mark) In addition, although the key string data itself may use the mark whose 0th bit is "1", the matched string Then, sometimes I want to reset this mark. It is the / RSMK signal that does this, and when this is set to the "L" level, the string match mark circuit SM
If the SMTC 'signal generated by itself is at "H" level, M writes "0" in the 0th bit of the string data.

By performing the above operation during the refresh of each row, the search for all cells can be performed simultaneously with the refresh. The string selected by the search is marked with the 0th bit as "1" or reset to "0".

As described above, two kinds of processing have been described with respect to the result of the match search. Next, access to the selected string will be described.

Access is made to the string with the 0th bit marked "1". There are many marked strings, and there can be multiple marked strings in one selected row.

These are accessed cyclically. That is, whether or not a marked string exists in a certain line is unknown at the time of access, but first, the line to be searched is selected and activated. Then, in each sensed column, the IOGON signal is pulsed to the “H” level in order to fetch the 0th bit of the string into the cyclic read circuit CRC. Then IOG
The ON signal is set to the “L” level, and the CR signal is toggled as in the case of access in the normal DRAM page mode.
As a result, 8 bits of the first marked string are first connected to the I / O line in the selected row while the CR signal is at "H" level.

Further, by continuing toggling the CR signal, it is possible to access the sequentially marked strings and read and write data to the strings.

When there is no marked string in the selected row or when the CR signal becomes "H" level after the last marked string is accessed, C
The RL signal becomes "H" level. Now this line contains
It turns out that there is no string to access.

Further, in order to access another row, the same operation can be performed for each row to access the marked string.
Then, if the same access operation is performed for all the rows of the memory, the access operation can be performed simultaneously with the refresh operation.

The example using the DRAM cell has been described above for writing the key string data and the data set, searching the string, and accessing the marked string. However, it goes without saying that the above configuration can be used not only for DRAM but also for random access memory such as SRAM. Furthermore, NAND type E
The EPROM and the above configuration are very compatible. This is because the NAND type EEPROM has a data latch / sense amplifier for each column, and the circuit configuration exactly the same as that of FIG. 3 can be used except the equalize circuit EQ. Further, when used for searching a Kanji ROM, etc., the memory cell array will need to be a ROM cell array.

Next, the individual elements in the circuit of FIG. 3 will be described in detail.

FIG. 4 is a block diagram showing a detailed structure of the cyclic read circuit CRC. As shown in FIG. 4, the data B0 or B8 connected to the bit line is an N channel MOS.
It is input through the transistor 4 and supplied to the input side of the inverter 6, the output side of the inverter 8, the NAND circuit 22, and the drain of the N-channel MOS transistor 12.
The IOGON signal is input to the gate of the transistor 4 and the gate of the N-channel MOS transistor 16. S
The AC signal is input to the gate of the N-channel MOS transistor 2. The drain of the transistor 2 is the output side of the inverter 6, the input side of the inverter 8, and the N-channel MO.
The gate of the S transistor 10 is connected to the NAND circuit 18. The CR signal is supplied to the NAND circuits 18 and 22 and the source of the transistor 12. The drain of the transistor 16 is connected to the drain of the P-channel MOS transistor 14, the gate of the transistor 12, and the drain of the transistor 10. The output of the NAND circuit 22 is given to the gate of the transistor 14 and the inverter 24. Also,
The output of the NAND circuit 20 is given to the inverter 20.
The output of the inverter 20 is derived as a CR 'signal and the output of the inverter 24 is derived as an IOG signal. The sources of the transistors 2, 10 and 16 are grounded, and the source of the transistor 14 is connected to the power supply.

In the structure as described above, B0, B
8 is a bit of the bit line corresponding to the 0th bit column of the string data in FIG. 3, which becomes "H" level when marked. The level of this bit line is taken into this circuit through the transistor 4 while the IOGON signal is at the "H" level. After capturing the level, the bit line and the cyclic read circuit CRC are disconnected. Here, when the SAC signal is set to the “H” level, the cyclic read circuit CR is irrespective of the level of the bit line.
C is in the same state as when the bit line is at "H" level.

In this cyclic read circuit CRC, first, C
It is assumed that the R signal is input as "H" level. If the state of the bit line taken in at this time is "L" level, C
The change of the R signal is as it is, the NAND circuit 18, the inverter 2
It is output as a CR ′ signal through 0. If the state of the fetched bit line is "H" level, the NAND circuit 22 and the inverter 24 are in the period in which the CR signal is "H" level.
Through, the IOG signal becomes "H" level, and the node N1 becomes "H" level through the transistor 14.

Next, when the CR signal changes to "L" level, the IOG signal is set to "L" level while resetting the held "H" level state of the fetched bit line.
Therefore, even if the CR signal is pulse-changed to the "H" level next time, the cyclic read circuit CRC only outputs the CR 'signal as the "H" level.

The cyclic read circuits CRC are connected in series as shown in FIG. 5 along the rows of the cell array. Therefore, it is assumed that the bit lines of the cyclic read circuit CRC indicated by "select", "select '", and "select" are at "H" level, and this state is taken in. In this case, the "selection" IOG signal is raised by the first CR signal pulse, and the "selection" IOG signal is raised by the second CR signal pulse.
At the third CR signal pulse, the IOG signal of "selection" is raised.

The above-mentioned operation status is shown in the timing chart of FIG. 6A shows a CR signal, and FIG. 6B shows it.
Is the IOGON signal, (C) is the state of node N1, (D) is the state of node N1 ', and (E) is the node N.
1N. By the way, the node N1, the node N1 ′, and the node N1 ″ represent the same node of different cyclic read circuits CRC, and the node N1 is “selected” and the node N1 ′ is "Selection" and node N1 "correspond to" selection ".

First, at time t1, the IOGON signal is set to the "H" level pulse and the bit line level is taken into the cyclic read circuit CRC, as described above. After that, the CR signal is sequentially toggled at time t2, time t3, and time t4, so that the node N
1, the node N1 ′, and the node N1 ″ sequentially become “H” level.

In the circuit of FIG. 5, after the IOG signals have risen in all the cyclic read circuits CRC, if there is no IOG signal that should be raised even if the CR signal pulse is given next, the last cyclic read circuit CRC Outputs a CRL signal synchronized with the CR signal. This ensures that all applicable IOGs
It can be seen that the signals have been selected.

The outline of the operation of the cyclic read circuit CRC has been described above with reference to FIGS.
Details of the operation of the RC will be described again more specifically with reference to FIGS.

As shown in FIG. 7, the cyclic read circuit CRC
Is determined based on the data holding states of the inverters 6 and 8. When the output of the inverter 8 is at "H" level, it is defined as "1" state, and when it is at low level, it is defined as "0" state. When it is "1", the output CR 'is fixed at "L" level. The output of IOG is the input C
The signal has the same phase as R, the output CR 'becomes the same phase as the input CR when in the "0" state, and another output IOG is fixed at the "L" level. Figure 7
(A) and (b) of FIG.

FIG. 8 is an explanatory diagram of the operation of the cyclic read circuit CRC assuming a memory cell array consisting of 6 column blocks. At time t1, the “H” pulse of IOGON is input to all the cyclic read circuits CRC, and is transferred to the data of the upper column data bus line. As a result, CRC2, CRC4, and CRC5 are in the “1” state, Others are in the "0" state. That is, the states of the cyclic read circuit are 01011, in order from the top.
It becomes 0. At this time, CRC is driven in the same phase as CR.
There are only 2 IOGs, and the others are fixed to "L" level. Then, at time t2, CR changes from "L" to "H".
Then, the IOG of CRC2 rises to "H" level, and as a result, the data of the second column block is transferred. Then, when CR falls at time t3, the state of CRC2 changes from "1" to "0". As a result, the states of the cyclic read circuit are, in order from the top,
It becomes 000110. At this time, only the IOG of CRC4 is driven in phase with CR, and the others are fixed at "L" level. Then, when CR rises from "L" to "H" at time t4, IOG of CRC4 rises to "H" level, and as a result, the data of the fourth column block is transferred. Then, at time t5, C
When R falls, the state of CRC4 changes from "1" to "0".
Transition to. As a result, the states of the cyclic read circuit become 000010 in order from the top. At this time, only the IOG of CRC5 is driven in the same phase as CR, and the others are "L".
Fixed to the level. Then, at time t6, when CR rises from "L" to "H", IOG of CRC5 rises to "H" level, and as a result, the data of the fifth column block is transferred. Then, time t7
When CR falls at, the status of CRC5 is "1".
To "0". As a result, the states of the cyclic read circuit become 000000 in order from the top. Then, at time t8, when CR rises from "L" to "H",
CR ', which is the output of CRC6, transits to "H" level for the first time. As a result, it is acknowledged that all data (corresponding key string data matched and marked) has been transferred.

As described above with reference to FIGS. 7 and 8,
Only the data of the marked column block can be read, and the reading operation of the data of the other column blocks is not performed, so that extremely high-speed data transfer is possible. For example, if there are 256 column blocks,
When the marks are added to the three column blocks, the data transfer is performed only three times, and it is not necessary to perform the data transfer 256 times as in the conventional case. The end of output of all marked data is detected by the output of the cyclic read circuit in the final column block, CR.
'Is used. This CR 'is the control circuit 1 in FIG.
05 is output to the outside of the search memory device 100.
More specifically, the data is transferred to the peripheral circuit device 200.

FIG. 9 is a circuit diagram showing a concrete example of the bit comparator BCM and the string bit register SBR of FIG.

As shown in FIG. 9, the string bit register SBR has two inverters connected in anti-parallel with each other to form a self-holding system, and an N-channel MOS transistor 30 to which the string bit SBi is input. The STR signal is input to the gate of the transistor 30. Further, the held string bit SBi ′ is output from the inverter 28, and the held string bit / SBi is output from the inverter 26, both of which are supplied to the bit comparator BCM.

In the bit comparator BCM, the string bit SBi 'is the N-channel MOS transistor 5
6 and the gate of the P-channel MOS transistor 46, respectively. The string bit / SBi is input to the gates of the P channel MOS transistor 54 and the N channel MOS transistor 48, respectively. The drains of the transistors 54, 46, 56 and 48 are commonly connected to each other and output the / BMTCi signal. Bit line Bi is connected to the source of N channel MOS transistor 34, and bit line / Bi is connected to the source of N channel MOS transistor 36. Transistor 34,
The CMPTR signal is connected to the gate of 36. The drain of the transistor 34 is the gate of the P-channel MOS transistor 50, and the N-channel MOS transistor 52.
Connected to the gate. On the other hand, the drain of the transistor 36 is the gate of the P-channel MOS transistor 42,
It is connected to the gate of N-channel MOS transistor 44. The drain of the transistor 50 is the transistor 54
The source, the drain of the transistor 42 are connected to the source of the transistor 46, the drain of the transistor 52 is connected to the source of the transistor 56, and the drain of the transistor 44 is connected to the source of the transistor 48. A capacitor 38 is connected to the drain of the transistor 34 and a capacitor 40 is also connected to the drain of the transistor 36, and the capacitors 38 and 40 are mutually connected. The sources of the transistors 42 and 50 are connected to the power supply, and the sources of the transistors 44 and 52 are connected to the drain of the N-channel MOS transistor 58. Transistor 58
A CMP signal is applied to the gate of the. Transistor 5
The source of 8 is grounded.

The string bit register SBR is a so-called latch circuit, which fetches data from the string bit line SBi while the STR signal input to the gate of the transistor 30 is at "H" level, and the inverter 26,
28 holds this data by itself.

Output S of string bit register SBR
The bit comparator BCM compares Bi and / SBi with the data Bi and / Bi read from the cell and defined on the bit line. The bit comparator BCM fetches data from the bit line and performs a comparison operation after being separated from the bit line. This is to prevent a change in bit line data from interfering with the comparison result because there is a marked column or the like for which data should be rewritten depending on the comparison result.

The bit line data is taken in by setting the CMPTR signal to "H" level. The bit line data is taken in through the transistors 34 and 36,
It is stored and held in the capacitors 38 and 40. After the CMPTR signal is set to "L" level, the CMP signal is set to "H" level so that the transistor 58 becomes conductive. As a result, the transistors 42, 46, 50, 54, 44,
The comparison operation by 52, 48 and 56 is performed, and the comparison result is output as the / BMTCi signal. This / BMTCi
The signal output is "L" level in the case of coincidence and "H" level in the case of disagreement.

The above-mentioned comparison result from the bit comparator BCM is put together, the match / mismatch of the strings is detected, and the mark bit is written in the string match mark circuit S.
It is MM. FIG. 10 shows this string matching mark circuit S
It is a circuit diagram which shows the detailed structure of MM.

In FIG. 10, the drains of the N-channel MOS transistors 62 and 60 are bit lines B0 and B8.
And the source is grounded. On the other hand, the drains of the N-channel MOS transistors 68 and 70 are bit lines /
It is connected to B0 and / B8 and the source is grounded. The RS signal is applied to the gate of the transistor 62. / MK
The CNT signal is input to the gate of the N channel MOS transistor 64 and the gate of the P channel MOS transistor 66. The SMTC signal is connected to the source of the transistor 66. The drains of the transistors 64 and 66 are connected to the gate of the transistor 68. The source of the transistor 64 is grounded. On the other hand, the / RSMK signal is P
It is input to the gate of the channel MOS transistor 72 and the gate of the N channel MOS transistor 74. The source of the transistor 74 is grounded, and the drain is connected to the gate of the transistor 60 and the source of the transistor 72. The / MKCMP signal is connected to the gate of the N-channel MOS transistor 76 and the gate of the P-channel MOS transistor 78. The source of the transistor 76 is grounded and its drain is connected to the gate of the transistor 70 and the drain of the transistor 78. / BMT
The Ci signal (i = 0 to 7) is input to the gates of P-channel MOS transistors 80, 81, 86 and 87 connected in series. The source of the transistor 87 is connected to the power supply. On the other hand, the drain of the transistor 80 is connected to the drain of the transistor 72 and the source of the transistor 78, and is derived as the SMTC 'signal.

In the configuration described above, / BMT
The Ci signal is a comparison result from the bit comparators BCM of eight columns forming a string. If the strings match, the level of all / BMTCi signals is "L"
Since it becomes the level, the SMTC 'signal becomes the "H" level.

The SMTC signal is a similar output from the string match mark circuit SMM adjacent to the string to which this string match mark circuit SMM belongs.

As described above, when the compared strings themselves are marked, the / MKCMP signal is set to "L".
To level. By doing so, if the SMTC 'signal is at "H" level, / B0 becomes "L" level, and "1" is written in the 0th bit of the compared strings themselves. On the other hand, in order to mark the strings belonging to the compared strings by the content search, the / MKCNT signal is set to the “L” level. SMTC
If the signal is at "H" level, "1" is written in the 0th bit of the next string of the compared strings.

By setting the RS signal to the "H" level commonly to all the string match mark circuits SMM, "0" can be written in the 0th bit of all the strings. This is a necessary function in the sense of resetting the mark for new key string data before performing a match search.

Further, the string match mark circuit SMM is provided with a circuit for resetting the mark only when the strings match. / RSMK signal to "L"
When set to level, compared strings match and SMT
If the C'signal is at "H" level, "0" is written in the 0th bit of the compared string to reset the mark.

This is useful when the string data having a tree structure is sequentially searched to access only the last string data. Also, access to independent data in the tree structure, for example, A → B → C and B →
This is useful when searching D from B in a structure such as D. That is, search for A and then B below
Mark, then search with unmarked B and mark D, and then search with marked B and reset and access that mark, because only D has mark, Only D can be read and written.

Further, in the data structure such as A → A → B, when A is searched as key string data, 2
Although the second A and B are marked, only the B can be accessed by searching for the marked A, resetting this mark, and accessing in this state.

Next, the circuit configuration of the search memory device according to the second embodiment of the present invention will be described with reference to FIGS. The schematic configuration shown in FIGS. 1 and 2 applies to the second embodiment as well, and thus the description thereof is omitted.

As shown in FIG. 11, the second embodiment is the first
In this embodiment, the configuration of the cyclic read circuit CRC, the configuration of the string bit register SBR, and the configuration of the string match mark circuit SMM are modified and some control signal lines are added.

The cyclic read circuit CRC is arranged in the upper column data line B8 (that is, B in the column block adjacent to the lower side).
0 '), and further, the PRESTR signal is input.

In the string bit register SBR, STR is input in the first embodiment, but in the present embodiment, two kinds of signals STR1 and STR2 are input.

The string match mark circuit SMM has a first
In addition to the examples of CMP, RSMKK, RSMKS,
/ MKNXT four types of signals are input and the RSMK signal is deleted.

FIG. 12 is a circuit configuration diagram of the string match mark circuit in the second embodiment. This circuit is obtained by modifying a part of the circuit shown in FIG. 10 so as to realize the three functions described below.

(1) The signal RSMKS is supplied to the node N1 of the transistor 68 so that the adjacent 8-bit mark can be reset in the "data search belonging to the key string data" described above. This node N
1 is the ground potential in FIG. ). As a result, if the signal RSMKS is "0", "1" is written in the mark bit, and the mark of the key string itself described in (2-1) and the mark of the key string itself described in (2-2) are reset. To simplify the circuit, the signal RSMK is applied to the node N2 of the transistor 70.
K is supplied (this node N2 is at ground potential in FIG. 10). As a result, if the signal RSMKK is "0", "1" is written in the mark bit and "1" is written.
Then, "0" is written in the mark bit and reset. As a result, the transistors 60, 72,
74 is no longer needed, and there is no need to add signal / RSMK.

Further, a new transistor T1 and a signal / MKNXT are provided to set "0" or "1" in the mark bit of the string following the string whose mark bit is "1". This transistor T1 bypasses the transistors 81 to 87 of FIG.
If BMTC0 and signal / MKNXT are "0", signal S
MTC 'is set to "1". That is, the mark can be set to the string having "1" as a mark bit or the next string regardless of the contents of the key string. The contents that can be set at this time are the signals RSMKS and RSM.
Depends on KK level. The transistor 62 and the signal RS can be omitted based on the provision of this function. That is, instead of the mark reset operation described in, the mark bit is "1" and / MKNXT is "0".
/ MKCMP "0", RSMKK and RSMKS are "1"
You can search with. At this time, if / MKCNT is "1", RSMKS may be "0".

The circuit CKT1 to which the signal SMTC 'controlled by the new signal CMP is added is a "0" latch circuit for preventing the signal node N3 from floating "0". The signal CMP is the signal CMPT
Since a "0" pulse is generated as an almost opposite phase signal of R, the node N3 is reset and held at "0" at this time.

Next, details of the circuit configuration of the string bit register of the second embodiment will be described.

In the circuit of FIG. 9, a key string match search is performed on all the bits that make up the string, and a match is established when all match. But,
In the actual search, you may want to search by ignoring some bits of the string. Therefore, in FIG. 13, the configuration of the bit register is modified so that the match is established even when the bits partially match.

In FIG. 9, signals / SBi 'and SB
i'was generated from one latch circuit constituted by the inverters 26 and 28. On the other hand,
In FIG. 3, two latch circuits LCH1 and LCH2 for signal / SBi 'and SBi' are provided. Further, the control signals of the transfer gates TG1 and TG2 for fetching data from the data line SBi are also STR1 and ST.
Separated from R2. In the comparison bit ignoring the read data, if both / SBi 'and SBi' are "1", regardless of the data of Bi and / Bi, /
BTCi becomes “0”. In other words, the result is the same as if a match was established for that bit. That is, the latch data is substantially controlled in three values.

With this function, the function of the / MKNXT signal of the string match mark circuit can be substituted. That is, the string bit register may be set so that bits other than the mark bit are ignored.

FIG. 13B shows the transfer signal STR.
The timing of 1 and STR2 and how to give the string bit data are shown. The right side shows the state of the string bit register.

Next, a modification of the cyclic read circuit will be described with reference to FIG.

As already mentioned, writing to the mark bit is unidirectional, either the key string itself or the next string. This does not change in the circuit example of FIG. The only strings that can be read by the cyclic read circuit are those in which "1" can be set in the mark bit. For this reason, it is not possible to read the data of the string preceding the string that matches the given key string and examine the contents. This means that you can only search backwards from the key string, which is inconvenient when checking what kind of data situation the key string data is in.

In the circuit of FIG. 4, the bit line data B0, B
8 is directly connected to the transfer gate 4. On the other hand, in the circuit of FIG. 14, the bit line data / B0 is connected via the logic circuit LCKT. That is, the cyclic read circuit can be set so that the signal IOG can be output not only by the mark bit of the string in charge thereof but also by the bit line data B0 ′ of the mark bit of the next string. The signal / B0 in the figure indicates the complementary signal of the bit line data B0 of the mark bit column of the serving string, and B0 'indicates the bit line data of the mark bit column of the next string of the serving string. Signal P
If the RESTR (PRE CEDING STRING) is "1" and the mark bit of the next string is "1", the cyclic read circuit is IOG "1" even if the mark bit of the serving string is "0". Is set to be able to output. Therefore, when the cyclic reading is performed, the string immediately before the marked string is also read, and the string data in the front can be searched.

Some examples of data search using the circuit configuration of the second embodiment of the present invention will be described below. (I) Rearrangement of Random Packet Data Table 1 shows one specific example of this example.

[0100]

[Table 1] As can be seen from Table 1, the data read by the asynchronous data transfer (ATM) can be restored by giving the header as a key string and performing cyclic reading.

More specifically, as can be seen from Table 1, each data packet has a fixed length, is composed of a header and a data part, and the data packets hanging in the header are arranged randomly. Here, an example is shown in which a data packet is composed of one string of header and one string of data. When the signal input to the string match mark circuit is in the next state, a match search is performed and cyclic reading is performed.

/ MKCMP "1" / MKCNT "0" / MKNXT "1" RSMKK "0" or "1" RSMKS "0" If the header or data is composed of many strings, the application described later. You can combine examples to create a search method. (Ii) Retrieval of hierarchical classification data Table 2 shows one specific example of this example.

[0103]

[Table 2] As can be seen from Table 2, when data exists in a hierarchically classified state, the hierarchical classification item can be regarded as constituting the header of (i) described above. In this example, a case where data hanging under the classification item data a1 b2 c2 is searched will be described. The dot above each datum indicates that a mark has been set on that string. After marking by search, unnecessary marks among those marks are erased so that only target data is cyclically read. (R) after the key
Indicates a search that resets the mark of the string following the matched string. The status setting of the search string match mark circuit with each key is shown below.

[0104]

[Table 3] (Iii) Retrieval of data having a key string in which the first key does not overlap Table 1 shows a specific example of this example.

[0105]

[Table 4] As can be seen from Table 4, this application shows the retrieval of non-fixed length data. The fact that the first key does not overlap the key string means that A does not exist in the series of key data to be searched, and other keys other than A may also overlap. There are various search paths that start from the first key A and are connected by a line. Here, the case where T out of the data hanging on these paths is read is shown.

Although the general key procedure is also shown, the first key IN must not be included in the key sequence from K1 to Kn. The search operation is continued by searching with the marked key and deleting the mark attached to the key data string with the previous key. Since only the first key is searched with the unmarked key, all the keys next to the key A in the string string to which the first key is connected are marked. In order to erase this mark, a search for erasing one's self-confidence mark (SR) is performed with the marked leading key A dot.

In this search, even if a key string string is provided from the beginning, the key strings may be searched one by one and selected while reading, and the key strings may be traced. In the case of the later search, the data is selected one by one from the key candidates, and the data is branched into one branch that is advancing.

The state setting of the string match mark circuit when erasing its own mark such as IN (SR) by the key procedure is shown below.

/ MKCMP “0” / MKCNT “1” / MKNXT “1” RSMKK “1” RSMKS “0” or “1” The status setting for other searches is as shown in the previous application example. is there. (Iv) Sequential reading of string data Table 5 shows a specific example of this example.

[0110]

[Table 5] This is a method of sequentially reading the next data with the read data itself. If the mark bit and End of the cyclically read data are ignored, string data can be obtained. Since the heading is attached only to the first X1, the memory can be saved more than the case where the heading is attached to each Xi, but the reading is troublesome.
The application example described here is the same as the application example described in (iii) above, when there is no data branch in the key after the first key and the data is isolated under the first key. Corresponds to Heading. According to the example explained here, it is not necessary to erase the mark of the key,
Data from Heading to End can be read by cyclic reading. You don't have to delete the mark, so you can save the search time. (V) Forward reading and retrieval Table 6 shows a specific example of this example.

[0111]

[Table 6] As can be seen from Table 6, in this application, when the mark string that matches the key data and the next string are marked and the mark bit is set in the cyclic read circuit, the mark bit is also set in the read circuit of the immediately preceding string. Forward reading is performed by setting. The state setting of the string match mark circuit in the search X & Key Mark, which is an operation of marking the self-confidence string that matches the key data and the next string, is as follows.

/ MKCMP “0” / MKCNT “0” / MKNXT “1” RSMKK “0” RSMKS “0” Further, as the state setting of the cyclic read circuit, PRESTR is set.
Is set to "1" and the string data c can be read. Data can be traced forward by using this as a key to trace back. (Vi) Screening search One specific example of this example is shown in Table 7.

[0113]

[Table 7] According to this search, by giving various attributes to the bits of the key string, it is possible to search for data that meets the conditions.

Further, when the data is a long data which is continuous over a plurality of strings, MKNXT marks the string next to the marked string.

This application example can be applied to all the application examples up to now. That is, one is when it is desired to perform a match search on only some of the bits of the string, but not all of the bits that make up the string, and on the other hand, when the data exists continuously over multiple strings. , When you want to mark the string next to the marked string.

In this example, the X bit is ignored, but
This bit may be set in the corresponding state of the string bit register circuit.

In the search for marking the string next to the marked string among the plurality of strings forming the data, the mark bit is set to "1", and the state of the string match mark circuit is searched as follows. .

/ MKCMP “1” / MKCNT “0” / MKNXT “0” RSMKK “0” or “1” RSMKS “0” However, the marking function of the present case is that the string bit register circuit ignores other than the mark bit. Similar results can be obtained depending on the setting.

Searches that can ignore all but the mark bit can replace various mark reset functions.
For example, as for the function of the RS signal described above, the string bit register circuit ignoring other than the mark bit is set to "1" only for the mark bit, and the string match mark circuit is set to the following I to reset the mark of the match string.
Or it can be done by setting the status like II.

[0120] I II / MKCMP “0” “0” / MKCNT “1” “1” / MKNXT “0” “1” RSMKK “1” “1” RSMKS “0” or “1” “0” or “1” In the mark reset search operation with (R) of (II) and (III), instead of giving a specific key string, only the mark bit is set by setting the string bit register circuit ignoring other than the mark bit. The search may be performed by setting "0" and resetting the mark.

As described above in (i) to (vi),
By various operations of mark bit and cyclic read circuit of marked string, it is possible to access data according to the information contents that cannot be done in the conventional memory, and IOS (Information Oriented System) which is a future information processing system.
m) can be provided, that is, according to each of the above-mentioned application examples, for example, the mark state can be arbitrarily set for the string that matches the key and the next string, and the mark can be set in the cyclic read circuit. It is possible to read a string before the string, and further, it is possible to realize a search function in which the mark of the string can be freely set only by the presence or absence of the mark.

Next, FIG. 15 shows a third embodiment of the present invention. The overall circuit configuration is the same as in FIG.

FIG. 15 shows a circuit configuration of a modified search data transfer circuit 102 'corresponding to the third embodiment. As described above, the search data transfer circuit is composed of column search units belonging to each column block CB. Further, each column search unit or each column block is connected to an 8-bit data bus / string data bus IOSB (an extension of the data bus 106 and the string data bus 107 in FIG. 1, and a multiplexer circuit (not shown) is inserted). Has been done. Further, in the search data transfer circuit 102 'of the third embodiment, an 8-bit data register 400 is connected to the data bus / string data bus IOSB.

Each column block CB includes an 8-bit column data line bundle 303 connected to a memory cell, and this column data line bundle 303 includes a 1-bit upper column data line 3031 and a 7-bit lower column data line bundle 303.
Composed of two. Each column block CB further includes a column gate circuit 301, a cyclic read circuit CRC, a string bit register SBR, and a bit comparison / mark circuit 3.
It consists of 02.

The column gate circuit 301 connects the data bus / string data bus IOSB and the column data line bundle.

The cyclic read circuit uses the column gate circuit 301 based on the data of the 1-bit upper column data line and the signal CR supplied from the column block adjacent to the upper side.
To control.

The string bit register SBR is composed of an 8-bit register string, takes in the data of the data bus / string data bus SB, and temporarily holds it.

The bit comparison / mark circuit 302 compares the 8-bit data of the column data line bundle 303 with the 8-bit string data held in the string bit register SBR, and the comparison result is the column data line bundle 303.
Write back to. There are various methods for this write back,
As a typical example, in the case of coincidence, when writing “H” data to the next upper column data line 3031 ′ (in the column block adjacent to the lower side in FIG. 2), in the case of coincidence, “H” Column data line 303 for data of its own (of the column block to which the column search unit belongs)
There are cases such as writing to 1. The bit comparison / mark circuit 302 is composed of a bit comparator BCM and a string match mark circuit SMM as described later.

The data register 400 stores the data retrieved in the first time in the second retrieval subsequently performed.
When used as string data, it is used to hold the data retrieved so far.

With the above configuration, the two buses, the data bus and the string data bus, required in the first and second embodiments can be used as one data bus. It is possible and contributes to the reduction of the chip area. Further, due to the existence of the data register 400, when the data read in the above-mentioned "sequential reading of string data" is returned as a key string, it is possible to perform a sequential search without outputting the data to the outside of the chip. As a result, it also contributes to improvement in search speed.

As described above, in content retrieval, it is important to activate all rows, that is, word lines, not randomly but sequentially. Therefore, there is a cell structure more suitable than the conventional DRAM.

For the search and access operations, it is more important to increase the cell density than the random accessibility, without increasing the required number of refreshes. A so-called cascade type dynamic cell structure is suitable for such a structure. A cell structure of this type is described in the document "IEEE JOURNAL OF SOLID-STATE CIRCUITS (Nov.
1991. Vol. 26. No. 11. pp1511-
1518) ".

A search memory device having a memory cell array composed of such cascade type cells will now be described as a fourth embodiment with reference to FIGS.

FIG. 16 is a schematic diagram of a cascade type cell structure.

This structure is different from the structure of a general DRAM in that cells C in the cascade cell array CCA are connected in series in a state of being separated by a word line WL. Therefore, the data is read from the cell C sequentially from the cell C closest to the bit line BL to the cell C in the back, and the writing is performed in the reverse order of the reading.

When the data of the cell at the back of the cells connected in cascade is being read, the cell before this becomes the data transfer path. Therefore, if the data in the cell before the transfer path is not stored somewhere,
The data will be lost. A register for restoration holds this information. The contents of the cascade cell are temporarily stored here, and when the word line is closed, they are written back in order from the cell at the back.

In FIG. 16, four bit lines BL are commonly connected to a common bit line Bi, and data in cells connected to these bit lines BL are sensed by a common sense amplifier SA. Although not shown in FIG. 16, four bit lines / BL are also connected to the common bit line / Bi. The selective transfer gate STG determines which of these four bit lines BL is selected.

If the selective transfer gate STG is also regarded as a word line, the access order is determined to be serial every 16 rows in FIG. That is, the uppermost word line WL of the cascade cell is opened, the selective transfer gates STG are sequentially opened and sensed, and data is stored in the restore register RR. Then, the operation of opening the second word line WL and opening the selective transfer gate STG in sequence and sensing and storing the data in the register RR is performed toward the innermost cell. Writing from the restore register RR to the cell C is performed in the reverse order, and a series of read or write or refresh operation is completed.

The order of the above operation is decided by selecting a certain cascade cell. For a general DRAM that requires random access, such a restriction on row access greatly limits the memory function, but in the content reference memory, access to all rows is the basis. So this limitation is never a problem.

That is, in the memory device of the embodiment of the present invention, the memory cell having the structure as shown in FIG. 16 is connected to the structure of the first embodiment shown in FIGS. 1, 2 and 3. Thereby, the cell density can be improved by at least several tens of percent as compared with the cells of a normal DRAM. That is, a structure suitable for a large capacity can be obtained.

FIG. 17 is an explanatory diagram of row scanning of the sense array when the cascade cell is used. As shown in the figure, in the cell array CA, the first row in a group of rows whose access order is determined can be set arbitrarily,
Within the group, only serial access is possible due to the limitation of the access method of the cascade cell. This is as described above. In FIG. 17, SL indicates a top scan line that can be arbitrarily set.

In the present embodiment, the D type (dynamic type) memory cell is used, and the group of bit lines belonging to one sense amplifier is used as the column forming the string data. However, the memory cell is the D type. The same access as described above can be performed for the memory cells that do not need to be provided and do not need the refresh operation.

FIG. 18 is an explanatory diagram showing the memory access method in the memory device of the present invention in comparison with the conventional access.

Now, when paying attention to a certain row, in this, the first and second data sets 1 belonging to a certain key string are
Suppose there is 2. In this case, the conventional access CAC
Then, it is necessary to read all the cells in the cell array CA and search for the key string. On the other hand, in the scheme of the embodiment of the present invention, the data set is marked at the time of refresh, and only the data set is cyclically accessed. Therefore, in this case, only three access cycles are required, including confirmation of the absence of the data set. That is, focusing on the read row RL, the content reference access CRA, the first data set access DSA1, and the data set access DSA2 may be accessed three times. As described above, in the search-type access, according to the method of the embodiment of the present invention, the efficiency can be significantly improved.

As described above, according to the memory device of the embodiment of the present invention, in the content reference type memory, the key string data and the data set are written together, and the mark is added according to the string search result. , It is configured to access based on this, and even if the search data structure is a tree structure, it is configured so that only the data at the end of the necessary branch can be accessed by the search and mark method. Since the efficiency can be significantly improved and the cascade cell can be structurally applied, the cell density can be improved and a structure suitable for a large capacity can be realized.

Next, a fifth embodiment will be described with reference to FIG. Although the first to fourth embodiments have described the present invention using the search memory device as an example, the present invention is not limited to the search memory device, but rather can be applied as a search data transfer device. it can. For example, in data communication, it is used when decoding received packet data. In packet data communication, a plurality of different types of data groups are mixed in one packet.
Therefore, in receiving packet data, it is necessary to decompose into a plurality of these data groups. If a key string is associated with each data group and added to the beginning of the data string, the search data transfer device of the present invention
The packet data can be decomposed or decoded.

FIG. 19 shows the structure of a data receiver used for compounding this packet data. The data receiver 500 includes a register array 501, a search data transfer circuit 502, a data receiving circuit 504, and a control circuit 505. Further, the register array 501 and the search data transfer circuit 502 are divided into a plurality of column blocks CB, and data transfer is performed for each column block. Furthermore, the search data transfer circuit 502 and the data reception circuit 50
4 is connected by a data bus 506. The register array 501 is configured by arranging flip-flop circuits in rows.

The search data transfer circuit 502 compares read data for each column block based on the string data input from the outside or obtained in the previous cycle, stores the comparison result, and stores the comparison result. Data transfer is performed based on the comparison result. This data transfer is sequentially performed based on the clock signal supplied from the control circuit 505. This data transfer is not performed for all column block data, but is partially performed based on the comparison result. As described above, the fact that the search data transfer circuit 502 partially transfers the data based on the comparison result contributes to the improvement of the search speed.

The control circuit 505 controls the operation of the register array 501, the various operations of the search data transfer circuit 502, the operation of the data receiving circuit 504, and the like.

Further, the data receiver 500 includes a register file 601 and a string data register 602. The register file 601 is the search data transfer circuit 50.
The search data sequentially transferred by 2 are stored sequentially. The string data register 602 is the search data transfer circuit 6
Holds the string data to be given to 02. The string data register 602 is connected to the search data transfer circuit 502 by a string data bus. The search data transfer circuit 502 uses the same circuit as the search data transfer circuit in FIG. 11 except for the sense amplifier SA and the equalize circuit EQ, and therefore description thereof will be omitted. A flip-flop as a data register is connected to the bit line pair. Next, the operation of this data receiver will be described with reference to FIG.

First, the operation of inputting data to the register array will be described.

In inputting data to the register array, the register and the bit line line are connected to each other, and the IO line pair I
OO0 to IO7, / IO0 to / IO7 are connected to bit line pair B0
It is performed by connecting to B7 and / B0 to / B7.

Input is performed serially by 8 bits. The SAC signal is pulsed to the "H" level to bring all the cyclic read circuits CRC into the selected state. Then CR
When the signal is applied in pulses, the IOG signal becomes "H" level while the CR signal is at "H" level, and the I / O line pair and the bit line are connected. That is, the cyclic read circuit CRC is sequentially selected for each pulse of the CR signal, and eight columns are sequentially connected to the I / O line. In this state, I
Packet data can be input to the register array by giving appropriate data to the / O line pair.

Next, decoding of packet data will be described.

First, the STR signal is set to "H" level,
Key string data for opening the string bit register SBR corresponding to the string bits 0 to 7 and searching the string bit data lines SB0 to SB7 in this state,
That is, the head data of the data group is given. As a result, the key string data is written in the string bit register SBR. String bit register SBR is 8
In this case, the same key string data is written in all 8-bit string bit registers SBR. Then, the CMPTR signal is pulsed to the "H" level to fetch the data in the register array into the bit comparator. Then C
By setting the MP signal to the “H” level, the data determined on the bit line of the column and the data of each bit written in the string bit register SBR are compared. If the compared bit data match, the / BMTCi signal output from the bit comparator BCM changes to "L" level. If all of the 8 bit string bits match, S from the string match mark circuit SMM
The MTC signal becomes "H" level. This signal is S
As the MTC 'signal, the next string match mark circuit S
Supplied to MM.

When the data matching the key string is found as a result of the search, it is understood that the 8 bits adjacent to the matching key string data are the data belonging thereto. In this case, you need to mark this dataset. The first 8 bits (0 ...
If 7) is the matched key string data, SMT
The C'signal becomes "H" level and is given to the string match mark circuit SMM of the columns B8 and / B8 in FIG. Here, if the / MKCNT signal is set to "L" level,
"1" is written in the column of B8 / B8. Such writing of "1" is simultaneously performed in the column blocks to which all the matching strings of the selectively activated row belong.

The above operations can be performed simultaneously. The searched and selected string is marked with the 0th bit as "1", or
It is reset to "0".

Access is made to the string with the 0th bit marked "1". There are many marked strings, and there can be multiple marked strings in one selected row.

These are accessed cyclically. That is, whether or not there is a marked string in a certain row is unknown at the time of access, but in each column, the 0th bit of the string is read out from the cyclic read circuit C.
The IOGON signal is changed to the “H” level in a pulse form to be taken into RC. After that, the IOGON signal is set to "L" level and the CR signal is toggled. as a result,
In the selected row, the 8 bits of the first marked string are connected to the I / O line while the CR signal is at "H" level.

Further, by continuing toggling the CR signal, the strings marked in order can be accessed and the data can be read from the strings.

When there is no marked string in the selected row or when the CR signal becomes "H" level after the last marked string is accessed, C
The RL signal becomes "H" level. Now this line contains
It turns out that there is no string to access.

As described above, the data continuously read by the cyclic read circuit is stored in the register file 6
01, which is a data group corresponding to a predetermined key string. In other words, it has been decrypted.

As described above, by using the circuit configuration of the present invention, the packet data can be decoded very easily and at high speed.

Although the present invention has been described with reference to the first to fifth embodiments, the present invention is not limited to the above embodiments, and various application examples can be made without departing from the gist of the invention. It goes without saying that modifications are possible.

[0165]

According to the search memory device of the present invention, specific data can be written in a cell data string by an external data string added from the outside, and only the written cell data string can be read.
Further, according to the data transfer device of the present invention, it is possible to set a cell data string in which specific data is written in advance by a repeated pulse drive signal applied from the outside as a data transfer target.

[Brief description of drawings]

FIG. 1 is a block diagram of a search memory device and its peripheral circuits according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a search data transfer device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing details of main parts of FIG.

FIG. 4 is a circuit diagram showing details of the cyclic read circuit of FIG.

FIG. 5 is an explanatory diagram of interconnection of a cyclic read circuit.

FIG. 6 is a timing chart for explaining the operation of the cyclic read circuit.

FIG. 7 is an explanatory diagram for explaining the operation of the cyclic read circuit.

FIG. 8 is an explanatory diagram for explaining the operation of the cyclic read circuit.

FIG. 9 is a circuit diagram showing details of a string bit register and a bit comparator.

FIG. 10 is a circuit diagram showing details of a string match mark circuit.

FIG. 11 is a circuit diagram showing a second embodiment of the present invention.

FIG. 12 is a circuit diagram showing details of a string match mark circuit according to a second embodiment of the present invention.

FIG. 13 is a circuit diagram showing details of a string bit register and a bit comparator according to a second embodiment of the present invention and a timing chart showing the operation thereof.

FIG. 14 is a circuit diagram showing details of a cyclic read circuit according to a second embodiment of the present invention.

FIG. 15 is a block diagram of a search data transfer device according to a third embodiment of the present invention.

FIG. 16 is an explanatory diagram of a cascade type cell structure used in a fourth embodiment of the present invention.

FIG. 17 is an explanatory diagram of row scanning when a cascade cell is used.

FIG. 18 is an explanatory diagram of a memory access method according to the present invention.

FIG. 19 is a block diagram of a packet data receiver according to a fifth exemplary embodiment of the present invention.

FIG. 20 is an explanatory diagram of general memory access.

FIG. 21 is an explanatory diagram of content reference access.

[Explanation of symbols]

 CRC cyclic read circuit SBR string bit register BCM bit comparator SMM string match mark circuit SA sense amplifier EQ equalizer

Claims (25)

[Claims] 1. A memory cell array composed of a plurality of memory cells arranged in a matrix and divided into a plurality of column blocks, and string data input from the outside and data in each column block are compared. A search memory device comprising search data transfer means for marking some of the column blocks according to the comparison result and sequentially transferring and outputting the data in the marked column blocks. 2. A search memory device according to claim 1, wherein said search data transfer means uses a predetermined bit of data in each column block as a mark. 3. The search memory according to claim 1, wherein the plurality of column blocks are ordered, and the search data transfer means matches the string data with the data in each column block according to the comparison result. A search memory device characterized in that a mark is added to the column block next to the selected column block. 4. The search memory according to claim 1, wherein the plurality of column blocks are ordered, and the search data transfer means matches the string data with the data in each column block according to the comparison result. A search memory device characterized in that a mark is added to the selected column block. 5. The search memory according to claim 1, wherein the plurality of column blocks are ordered, and the search data transfer means receives a first signal to immediately precede the marked column block. Memory device for transferring and outputting data in a column block of the above. 6. The search memory according to claim 1, wherein the plurality of column blocks are ordered, and the search data transfer means receives a second signal in accordance with the comparison result, thereby generating string data. By marking the column block next to the column block in which the data in each column block matches, and receiving the third signal, the column data in the column block in which the string data and the data in each column block match. A search memory device characterized by erasing the mark of the next column block. 7. The search memory according to claim 1, wherein the plurality of column blocks are ordered, and the search data transfer means receives a second signal in accordance with the comparison result, thereby generating string data. By marking the column block next to the column block in which the data in each column block matches, and receiving the fourth signal, the string data of the column block in which the string data and the data in each column block match. A search memory device characterized by erasing a mark. 8. The search memory according to claim 1, wherein the plurality of column blocks are ordered, and the search data transfer means is divided into a plurality of column search units corresponding to the plurality of column blocks. The search data transfer means includes a data bus extending over the plurality of column search units, each column block includes a column data line bundle for transferring the read data, and the column data line bundle includes predetermined column data. Line and other column data lines, and each column search unit controls the column gate according to the data of the column gate that selectively connects the column data line bundle and the data bus and the data of the predetermined column data line. A search memory comprising a cyclic read circuit. 9. The search memory according to claim 8, wherein the cyclic read circuit performs cyclic read in a column block immediately before a column block to which the cyclic read circuit belongs when the data of the predetermined column data line is at a first level. The column gate is connected and controlled according to the signal given from the circuit, and a signal of a predetermined level is given to the cyclic read circuit in the column block immediately after, and when the data of the predetermined column data line is at the second level, the cyclic circuit A search memory characterized in that a cyclic gate circuit in a column block immediately after a column block to which a read circuit belongs is supplied with a signal supplied from the cyclic read circuit in the immediately preceding column block and the column gate is opened. 10. The search memory according to claim 1, wherein the plurality of column blocks are ordered, and the search data transfer means is divided into a plurality of column search units corresponding to the plurality of column blocks. The search data transfer means includes a string data bus extending over the plurality of column search units, each column block includes a column data line bundle for transferring the read data, and the column data line bundle is a predetermined column. Each column search unit is composed of a data line and other column data lines, and each column search unit compares the column data line bundle with the string data provided by the string data bus and responds to a fifth signal according to the comparison result. The comparison result is given to the column block immediately after, and the ratio given from the column block immediately before. Lookup memory, characterized by comprising a bit comparing mark means subjecting the mark in the predetermined column data line based on the results. 11. The search memory according to claim 10, wherein:
The bit comparing / marking means includes string bit register means for taking in the string data on the string data bus and holding the string data. The data held in the string hit register means is first, second, and third. When the string bit register means holds the third data for a certain bit, when the column data line bundle is compared with the string data, the bit concerned becomes the comparison result. A search memory characterized by being regarded as a match regardless. 12. The search memory according to claim 1, wherein the memory cell is a dynamic memory cell. 13. The search memory according to claim 1, wherein the memory cell is a static memory cell. 14. The search memory according to claim 1, wherein the memory cells are cascaded dynamic memory cells. 15. The search memory according to claim 1, wherein the memory cell is a NAND type EEPROM cell. 16. The search memory according to claim 1, wherein the memory cell is an MROM cell. 17. A register array composed of a plurality of registers and divided into a plurality of column blocks, string data input from the outside and data in each column block are compared, and columns are output according to the comparison result. A data search device comprising a search data transfer unit that marks some of the blocks and sequentially transfers and outputs the data in the marked column blocks. 18. A data search device according to claim 17, wherein said search data transfer means uses a predetermined bit of data in each column block as a mark. 19. The data search device according to claim 17, wherein the plurality of column blocks are ordered.
The data search device, wherein the search data transfer means marks the column block next to the column block in which the string data and the data in each column block match, according to the comparison result. 20. The data search device according to claim 17, wherein the plurality of column blocks are ordered.
The data search device, wherein the search data transfer means marks the column block in which the string data and the data in each column block match, according to the comparison result. 21. The search memory according to claim 17, wherein
The plurality of column blocks are ordered, and the search data transfer unit transfers and outputs the data in the column block immediately before the marked column block by receiving the first signal. Data retrieval device. 22. The data search device according to claim 17, wherein the plurality of column blocks are ordered.
The search data transfer means may generate a second data according to the comparison result.
Signal is added to mark the column block next to the column block in which the string data and the data in each column block match, and the third signal is received to receive the string data and each column block. A data retrieval device characterized by erasing a mark in a column block next to a column block in which the data in the column match. 23. A storage element array composed of a plurality of storage elements and divided into a plurality of ordered column blocks, string data input from the outside, and data stored in the storage elements in each column block. Compare
According to the comparison result, some of the column blocks are marked, and a search data transfer means for sequentially transferring and outputting the data stored in the storage elements in the marked column blocks is used. In the method of use, the first string data is input to the search data transfer means, the first string data is compared with the data stored in the storage element in each column block, and immediately after the column block where both match. And a step of marking the column block of the second string data is input to the search data transfer means and the second string data is compared with the data stored in the storage element in each column block, And a step of marking a column block immediately after a column block that both match and are marked. Wherein the first string data inputted to the search data transfer means the first string data and the storage elements in each column block is compared with the data to be stored again,
And a step of erasing a mark in a column block immediately after a column block in which both of them coincide with each other. 24. A storage element row composed of a plurality of storage elements and divided into a plurality of ordered column blocks, string data input from the outside, and data stored in the storage elements in each column block. Compare
According to the comparison result, some of the column blocks are marked, and a search data transfer means for sequentially transferring and outputting the data stored in the storage elements in the marked column blocks is used. In the method of use, the first string data is input to the search data transfer means, the first string data is compared with the data stored in the storage element in each column block, and immediately after the column block where both match. Marking the column block of the column string and inputting the second string data to the search data transfer means and comparing the second string data with the data stored in the storage element in each column block. And the step of marking the column block immediately after the column block that is marked and is marked Wherein the first string data inputted to the search data transfer means the first string data and the storage elements in each column block is compared with the data to be stored again,
And a step of erasing a mark of a column block in which the both agree with each other, thereby using the search device for searching hierarchical data. 25. A storage element array composed of a plurality of storage elements and divided into a plurality of ordered column blocks, string data input from the outside, and data stored in the storage elements in each column block. Compare
According to the comparison result, some of the column blocks are marked, and a search data transfer means for sequentially transferring and outputting the data stored in the storage elements in the marked column blocks is used. In the method of use, the first string data is input to the search data transfer means, the first string data is compared with the data stored in the storage element in each column block, and immediately after the column block where both match. This step consists of marking the column block of the column and a sub-step that is repeated multiple times.This sub-step is performed when the last data transferred and output by the previous step or sub-step is the data indicating the end of the data string. When the sub-step is completed and the last data is not the data indicating the end of the data string The input to the search data transfer means, compares the data which the second string data and the storage elements in each column block and stores it as the second string data,
A method of using a search memory, which is a sub-step of marking a column block immediately after a column block where both match.