JPH09180470A - Semiconductor memory element and semiconductor memory device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory device in which a bit inversion processing operation is not required when data to be compared is input to a semiconductor element, which is simplified and miniaturized, whose processing time is shortened and whose processing capability is enhanced by a method wherein a circuit configuration is contrived. SOLUTION: In a semiconductor memory element 10, a node N1 on the side of a bit line B is connected to the gate of an N-type MOS transistor Q8 on the side of an inversion bit line I, and a node N2 on the side of the inversion bit line I is connected to the gate of an N-type MOS transistor Q7 on the side of the bit line B. In this manner, outputs on the side of the bit line and on the side of the inversion bit line at a fundamental circuit 11 are connected to an input on the side of an inversion bit line and to an input on the side of a bit line at a comparison and collation circuit part. Thereby, it is not required to perform a bit inversion processing operation, an inversion processing circuit or device is not required, a semiconductor memory device can be miniaturized, and its processing operation can be performed at high speed. In addition, since a current hardly flows to the gates of the transistors Q7, Q8, a stable operation can be maintained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device that utilizes a bistable circuit for storing data and compares and collates stored data with input data, and a semiconductor memory device using the same. Regarding

[0002]

2. Description of the Related Art In general, a semiconductor memory device (hereinafter, also referred to as a memory) has a memory cell array composed of a plurality of semiconductor memory elements (hereinafter, also referred to as memory cells) and provides an address and word data. Thus, word data is written and read in the memory cell array. Further, the semiconductor memory device belongs to a memory called an application memory or a functional memory such as an associative memory described in, for example, "Ultra LSI Comprehensive Dictionary" (1988) published by Science Forum Co., Ltd., page 861. There is. These memories have a specific operation function in addition to the word data write / read function described above. For example, in an associative memory, each semiconductor memory element is configured by adding a comparison and collation circuit for comparing data to a CMOS static type memory cell, and has a data comparison and collation function for performing an associative memory operation. That is, the associative memory compares the input comparison target data with the data stored in the memory, and when the data match each other, detects the address of the data in the memory and outputs it.

A concrete example of the associative memory is a CP.
There is a cache memory provided between the U and the memory and used for the virtual memory system of the microprocessor.
In the virtual memory system of this microprocessor,
The cache memory stores a predetermined logical address and data referred to by the logical address. And C
When the PU accesses a certain logical address (virtual address) and the data referred to by the logical address is stored in the cache memory, the cache memory detects the logical address and stores the data in the CPU.
Read out. If the data is not stored in the cache memory, the cache memory reads the logical address and the data from the main memory and writes the data. As described above, the cache memory checks whether or not the data referred to by the logical address is stored, and when the data is stored, detects the logical address of the data and outputs the data. Further, the associative memory is used not only in the virtual storage system described above but also in a code processing system for image and audio data. That is, the associative memory is used to detect the address of the data that matches the bit pattern of the input data.

In the associative memory as described above, the processing speed of comparison and collation between input data and stored data is
Since the overall processing speed of the microprocessor such as the virtual memory system or the code processing system is determined, it is required that the processing speed of the comparison and collation be high. Further, each semiconductor memory element of the associative memory is configured by adding a comparison and collation circuit to the CMOS static memory cell as described above, but if the scale of the comparison and collation circuit is large, the chip area increases. Therefore, the cost of the product is increased, so that it is required to make the comparison / collation circuit small.

A conventional semiconductor memory device having a data comparison / collation function will be described below with reference to FIG. FIG. 7 is a circuit diagram showing a configuration of a conventional semiconductor memory element. In FIG. 7, a semiconductor memory device 40 includes a basic circuit portion 41 for storing data, and a comparison and collation circuit portion 42 for comparing and collating the data stored in the basic circuit portion 41 with input comparison target data. It is composed of.

The basic circuit section 41 includes two P-type MOS transistors Q11, Q13 and an N-type MOS transistor Q12, each of which constitutes a bistable circuit for substantially storing data.
Q14, and N-type MOS transistors Q15 and Q16 connected to the bistable circuit and the bit line B and the inverted bit line I, respectively. Note that, as shown in FIG. 7, the P-type MOS transistor Q11 and the N-type MOS transistor Q12 form a first inverter, and the P-type MOS transistor Q13 and the N-type MOS transistor Q12.
A second inverter is constituted by 14 and. And
The bistable circuit is configured by connecting the output / input of the first inverter and the input / output of the second inverter to each other at the node N11 and the node N12.
The bistable circuit of the basic circuit portion 41 configured in this way is
Data can be stably held with a wide operating margin and low current consumption. In addition, the N-type MOS transistor Q1
Since the word line W is connected to the respective gates of 5 and Q16, when the word line W has a high potential, the N-type MOS transistors Q15 and Q16 become conductive. At this time, in the semiconductor memory element 40, data write or read operation can be performed between the bistable circuit and the bit line B and the inverted bit line I.

The comparison / collation circuit section 42 includes three N-type MOSs.
It is composed of transistors Q17, Q18 and Q19. Specifically, in the N-type MOS transistor Q17, the gate is connected to the bit line B, the drain is connected to the node N11 on the bit line B side of the basic circuit portion 41, and the source is connected to the node N13. Also, N-type MO
In the S transistor Q18, the gate is connected to the inverted bit line I, the drain is connected to the node N12 on the inverted bit line I side of the basic circuit portion 41, and the source is the node N.
13 is connected. N-type MOS transistor Q19
Represents a discharge path of the match line M, the gate of which is connected to the node N13, the source of which is connected to the ground line and the drain of which is connected to the match line M. And
When the N-type MOS transistor Q19 is turned on, the charge on the match line M is discharged to the ground line, and the comparison result of the data can be obtained (details will be described later).

Next, the operation of comparing and collating data in the semiconductor memory element 40 will be described below. In the following description, a high potential that is an active potential and a low potential that is an inactive potential are abbreviated as H and L with reference to an N-type MOS transistor. First, in the period of the comparison and collation operation, the word line W is set to L and N is set to N in order to prohibit the data read and write operations between the basic circuit section 41 and the bit line B and the inverted bit line I. The type MOS transistors Q15 and Q16 are made non-conductive. Next, the bit line B and the inverted bit line I are set to L. as a result,
In the comparison / verification circuit section 42, the gate of the N-type MOS transistor Q19 becomes L, and the discharge path of the match line M is cut off. Then, while the discharge path is cut off, the match line M is charged by an unillustrated precharge circuit provided outside, and the match line M is set to H. Subsequently, the comparison target data is bit-inverted by an arithmetic circuit, a register and the like (not shown), and then the bit inversion data is input to the bit line B and the inversion bit line I.
That is, when the bit value of the comparison target data is 1, the bit line B and the inverted bit line I are set to L and H, respectively, and when the bit value is 0, the bit line B and the inverted bit line I are set to H and L, respectively. (Hereinafter referred to as bit inversion processing). Next, in the comparison / collation circuit section 42, the data stored in the basic circuit section 41 is compared with the comparison target data. When the above two data match, the node N13 becomes L and the N-type MOS transistor Q19
Becomes non-conductive. As a result, the discharge path of the match line M is cut off and the match line M is kept at H. Specifically, when the bit values of the above two data match with each other at 0, the node N11 is L, the node N12 is H, the bit line B is H, and the inverted bit line I is L. . Also,
When each bit value is 1 and coincides, the node N11 is H,
This is the case where the node N12 is L, the bit line B is L, and the inverted bit line I is H. Conversely, when the above two data do not match, the node N13 becomes H and the N-type MOS transistor Q19 becomes conductive. As a result, the discharge path of the match line M communicates, and the charge of the match line M is discharged. As a result, the match line M becomes L. Specifically, when the bit values of the above two data do not match, the node N11 is L, the node N12 is H, and the bit line B is
Is L and the inverted bit line I is H, or the node N11
Is H, the node N12 is L, the bit line B is H, and the inverted bit line I is L.

The conventional associative memory described above is composed of a memory cell array in which a plurality of semiconductor memory elements 40 are arranged in a predetermined arrangement. For example, in an associative memory that stores word data composed of 2 bits at four addresses, a memory cell array forming one address includes two semiconductor memory elements 40 in one set of word line W and match line M. It is configured by connecting. When the comparison target data and the stored data are compared and collated, if one of the bit values forming the word data does not match, the N-type MOS transistor Q19 of the mismatched semiconductor memory element 40 is detected. Is turned on and the match line M becomes L. Further, as a result, the address of the data that matches the comparison target data is detected.

[0010]

In the above conventional semiconductor memory device and the semiconductor memory device using the same, it is necessary to perform bit inversion processing when inputting comparison target data. Therefore, it is necessary to provide an arithmetic circuit, a register, and the like outside the memory cell array, which causes a problem that the semiconductor memory device cannot be downsized. Further, when continuous data is input and successive comparison is performed, the time required for the bit inversion processing becomes long, and there is a problem that the processing capacity per unit time in the entire processing decreases. In particular, in the case of performing the comparison and collation processing of bit patterns of image and audio data, it is necessary to temporarily store the data in the memory, read the data outside the memory, and then perform the bit inversion processing. Therefore, there is a problem that the time required for other than the comparison and collation processing which is the original processing becomes long, and the overhead in the semiconductor memory device becomes very large. Further, the P-type MOS transistors Q11 and Q used in the basic circuit section 41 are also provided.
13, and N-type MOS transistors Q12, Q14, Q
In determining the amplification degree depending on the sizes of 15 and Q16, it was necessary to consider the stability of the data read / write operation. For example, the comparison and matching circuit unit 42
In the read operation in the basic circuit section 41 except for the above, the access transistor is configured so that the data of the low potential can be read from the node N11 when the charge remains on the bit line B and the potential of the bit line B is the high potential. Q15, which is a pull-down transistor,
It was necessary to make it smaller than the amplification degree of 12. In addition, in the write operation, when the data stored in the bistable circuit described above has a high potential, the amplification degree of the access transistor Q15 is set so that a low potential can be written from the bit line B to the node N11. It was necessary to increase the amplification degree as compared with the amplification degree of Q11 which is a pull-up transistor. However, the conventional semiconductor memory device 40
In this case, since the nodes N11 and N12 are connected to the drains of the N-type MOS transistors Q7 and Q8, respectively, current paths are formed by the nodes N11 and N12 and the N-type MOS transistors Q7 and Q8, respectively. Therefore, it is necessary to determine the amplification factor ratio of the transistors so as to ensure stable operation including the operation of these transistors. In this way, the semiconductor memory device 40
However, there is a problem that the design becomes difficult.

The present invention has been made to solve the above problems, and is a semiconductor memory device capable of inputting comparison target data without performing bit inversion processing,
Another object of the present invention is to provide a semiconductor memory device using the same. Further, the present invention, without considering the current path formed between the basic circuit unit and the comparison and collation circuit unit,
It is an object of the present invention to provide a semiconductor memory element that can easily determine the amplification factors of P-type and N-type MOS transistors, and a semiconductor memory device using the same.

[0012]

According to another aspect of the present invention, there is provided a semiconductor memory device or a semiconductor memory device, wherein a bit line side output and an inverted bit line side output of a basic circuit section storing data are provided.
It is connected to the input on the inverted bit line side and the input on the bit line side of the comparison and collation circuit unit, respectively. With this configuration, when inputting the comparison target data to the bit line and the inverted bit line, it is not necessary to perform the bit inversion process of inverting the bit value and the inverted bit value with each other.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION In the semiconductor memory device of the present invention, the output of the first inverter is first input to the input of the second inverter.
Node of the second inverter and the output of the second inverter
A bistable circuit connected to the input of the second inverter by a second node, and a first bistable circuit connected to the first node and separating the input of the second inverter and the bit line by the potential of the word line. Switch element and a second switch element that is connected to the second node and that separates the input of the first inverter and the inverted bit line by the potential of the word line. A basic circuit portion that stores data in a stable circuit, a third switch element that separates between the bit line and the third node by the potential of the second node, the inverted bit line, and the third node. A fourth switch element that is separated from the node of the third node by the potential of the first node, and a fifth switch element that is separated from the match line and the ground line by the potential of the third node. Is stored in the basic circuit section. Comprising a comparator check circuit which compares the data inputted from the data and the bit line and the inverted bit line. In the semiconductor memory device configured as described above, the N-type MOS transistor forming the comparison and collation circuit, the first node on the bit line side and the second node on the inverted bit line side of the bistable circuit of the basic circuit portion are provided. The data to be compared is introduced to the bit line and the inverted bit line as they are without bit inversion by crossing and connecting. Since almost no current flows through the gate of the N-type MOS transistor of the comparison / collation circuit section, the semiconductor memory element operates stably. Further, when designing the semiconductor memory element, the amplification degree of the P-type and N-type MOS transistors can be easily determined without considering the current path formed between the basic circuit section and the comparison and verification circuit section.

In the semiconductor memory device of the present invention, the output of the first inverter is connected to the input of the second inverter by the first node, and the output of the second inverter is input to the input of the first inverter. A bistable circuit connected by nodes,
A first switch element that is connected to the first node and that separates an input of the second inverter and a bit line by a potential of a word line; and a first switch element that is connected to the second node,
A basic circuit section that stores a data in the bistable circuit, and a second switch element that opens between an input of the first inverter and an inverted bit line by a potential of the word line. A third switch element that separates the line from the third node by the potential of the second node, and the third switch element between the inverted bit line and the third node by the potential of the first node. A fourth switch element that is opened, and a fifth switch element that is opened between the match line and the ground line by the potential of the third node, and stores the data stored in the basic circuit section and the What is claimed is: 1. A semiconductor memory device comprising: a memory cell array having a plurality of semiconductor memory elements arranged in a predetermined array, the memory cell array comprising a bit line and a comparison / collation circuit section for comparing data input from the inverted bit line. The potential of the line A word line fixing circuit for setting a constant potential, a potential for the bit line and the inverted bit line set to a predetermined potential in a first period, and a data for the bit line and the inverted bit line in a second period. Data input circuit, a match line precharge circuit that sets the match line to a predetermined potential during the first period, and an address by encoding the potential of the match line during the second period. An address conversion circuit. In the semiconductor memory device configured as described above, since it is not necessary to perform bit inversion processing on the comparison target data and input the data, it is not necessary to provide an arithmetic circuit and a register.

Further, in the semiconductor memory device of another invention, in the semiconductor memory device, the logical product of the potential of the match line and the negation of the potential of the word line is obtained, and the result of the logical product is obtained by the address conversion circuit. It is provided with a match line conversion circuit for outputting to. In the semiconductor memory device configured as described above, a specific address is prevented from being output from the address conversion circuit by taking the logical product of the potential of the match line and the negation of the potential of the word line.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a semiconductor memory device of the present invention and a semiconductor memory device using the same will be described below with reference to the drawings.

<< Embodiment 1 >> FIG. 1 is a circuit diagram showing a structure of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, a semiconductor memory device 10 includes a basic circuit section 11 for storing data, and a comparison / collation circuit section 12 for comparing and collating the data stored in the basic circuit section 11 with input comparison target data. It is composed of. Basic circuit section 11
Is a bistable circuit that stores data substantially 2
P-type MOS transistors Q1, Q3, 2 N-type M
N connected to the OS transistors Q2 and Q4 and the bistable circuit and the bit line B and the inverted bit line I, respectively.
Type MOS transistors Q5 and Q6.
Then, as shown in FIG. 1, a P-type MOS transistor Q
The first inverter is configured by connecting 1 and the N-type MOS transistor Q2 complementarily. A second inverter is formed by connecting the P-type MOS transistor Q3 and the N-type MOS transistor Q4 in a complementary manner. The bistable circuit is configured by connecting the outputs of the first and second inverters to the inputs of the second and first inverters at nodes N1 and N2, respectively. The semiconductor memory element 10 thus configured has a wide operation margin and can stably hold data with a small current consumption. The N-type MOS transistors Q5 and Q6 respectively function as switch elements, and depending on the potential of the word line W, the node N
It controls the conduction state between 1 and the bit line B and the conduction state between the node N2 and the inverted bit line I. For example, when the word line W is at a high potential, since the word line W is connected to the gates of the N-type MOS transistors Q5 and Q6, the N-type MO transistor is formed.
The S transistors Q5 and Q6 are conductive. At this time, in the semiconductor memory element 10, data write or read operation can be performed between the bistable circuit and the bit line B and the inverted bit line I.

The comparison / collation circuit section 12 includes three N-type MOSs.
It is composed of transistors Q7, Q8 and Q9. Specifically, in the first N-type MOS transistor Q7 on the bit line B side, the drain is connected to the bit line B, and the gate is the node N2 on the inverted bit line I side of the basic circuit section 11.
, And the source is connected to the node N3. In the second N-type MOS transistor Q8 on the inverted bit line I side, the drain is connected to the inverted bit line I, and the gate is the node N on the bit line B side of the basic circuit section 11.
1 and the source is connected to the node N3.
That is, the node N1 of the basic circuit section 11 is the inverted bit line I
Of the N-type MOS transistor Q8 on the side of the bit line B is connected to the gate of the N-type MOS transistor Q8 on the side of the bit line B.
The gates of the OS transistors Q7 are connected to each other. The N-type MOS transistor Q9 constitutes a discharge path of the match line M, and has a gate connected to the node N3, a source connected to the ground line, and a drain connected to the match line M. Then, when the N-type MOS transistor Q9 is turned on, the charge of the match line M is discharged to the ground line, and the comparison result of the data can be obtained (details will be described later).

Next, the operation of comparing and collating data in the semiconductor memory device 10 will be described below. In the following description, a high potential that is an active potential and a low potential that is an inactive potential are abbreviated as H and L with reference to an N-type MOS transistor. First, in the comparison / verification operation period, the word line W is set to L and N is set to N in order to prohibit the data read and write operations between the basic circuit section 11 and the bit line B and the inverted bit line I. The type MOS transistors Q5 and Q6 are turned off. Next, the bit line B and the inverted bit line I are set to L. As a result, in the comparison and matching circuit unit 12, the gate of the N-type MOS transistor Q9 becomes L regardless of the data stored in the basic circuit unit 11, and the discharge path of the match line M is cut off. Then, while the discharge path is being cut off, the match line precharge circuit (not shown) provided externally charges the match line M to charge the match line M to H level.
Set to. Then, the comparison target data is input to the bit line B and the inverted bit line I. That is, when the bit value of the comparison target data is 1, the bit line B and the inverted bit line I
Are set to H and L, respectively, and when the bit value is 0, the bit line B and the inverted bit line I are set to L and H, respectively. Next, in the comparison / collation circuit unit 12, the data stored in the basic circuit unit 11 is compared with the comparison target data. If the above two data match, the node N
3 becomes L, and the N-type MOS transistor Q9 becomes non-conductive. As a result, the discharge path of the match line M is cut off and the match line M is kept at H. Specifically, when the bit values of the above two data match with each other at 0, the node N1 is L, the node N2 is H, the bit line B is L, and the inverted bit line I is H. . Also, each bit value is 1
, The node N1 is H, the node N2 is L,
This is the case where the bit line B is H and the inverted bit line I is L. Conversely, when the above two data do not match, the node N3 becomes H and the N-type MOS transistor Q9 becomes conductive. As a result, the discharge path of the match line M communicates, and the charge of the match line M is discharged. As a result, the match line M becomes L. Specifically, when the bit values of the two data do not match, the node N1 is L, the node N2 is H, the bit line B is H, and the inverted bit line I is L, or the node N1 is H. , The node N2 is L, the bit line B is L, and the inverted bit line I is H. As described above, in the semiconductor memory element 10 of the present embodiment, the comparison and collation result can be obtained by detecting the potential of the match line M.

As described above, according to the semiconductor memory device 10 of the present embodiment, the node N1 on the bit line B side is used as the gate of the N-type MOS transistor Q8 on the inverted bit I line side, and the node N1 on the inverted bit line I side is provided. The node N2 is an N-type M on the bit line B side
Each is connected to the gate of the OS transistor Q7. Therefore, when the comparison target data is input to the bit line B and the inverted bit line I, it is not necessary to perform the bit inversion process and input the data as in the conventional example. Furthermore, since almost no current flows through the gates of N-type MOS transistors Q7 and Q8, semiconductor memory element 10 can perform stable operation. Further, when designing the semiconductor memory device 10, the basic circuit section 11 and the comparison and collation circuit section 1 are
2 without considering the current path formed between
Type and N-type MOS transistor amplification can be easily determined.

<< Embodiment 2 >> FIG. 2 is a circuit diagram showing a structure of a semiconductor memory device according to a second embodiment of the present invention. In the present embodiment, for simplification of description, a semiconductor memory device that stores, for example, four 2-bit word data will be described below. In FIG. 2, the semiconductor memory device 14 is
A memory cell array 21 for storing predetermined word data,
A row decoder 22 for decoding an input address signal AD for designating an address of the memory cell array 21, a data input circuit 23 for inputting word data in bit units from the input terminal DI to the memory cell array 21, and a memory cell array 21 to an output terminal DO. It has a data input circuit 24 for outputting word data in bit units. In the memory cell array 21, a semiconductor memory element array of four stages for respectively storing 2-bit word data corresponds to the eight semiconductor memory elements 10-1 to 10-8 shown in the first embodiment by 2 bits ×.
It is configured by arranging in an array of 4 words. One address is assigned to each semiconductor memory element column. The data input circuit 23 has first and second gates 23b and 23i which take the logical product of the bit value and the inverted bit value of the input data and the control signal PC, respectively. First and second gates 23b and 23
Each output terminal of i is connected to the bit line B1 and the inverted bit line I1 connected to one of the semiconductor memory elements 10-1, 10-3, 10-5 and 10-7 of each semiconductor memory element column. There is. With this configuration, the bit line B1 and the inverted bit line I1 can be set to L, and the match lines M1 to M4 described below can be held at H. The data output circuit 24 is connected to the bit line B1 and the inverted bit line I1, and the sense amplifier 28 provided therein causes the bit line B1 and the inverted bit line I1.
The small potential difference of is amplified and output. The bit line B1
The inverted bit line I1 is connected to the data input circuit 23 or the data output circuit 24 by the control signal WR. Similarly, the same data input circuit 23 and data output circuit 24 are connected to the other semiconductor memory elements 10-2, 10-4, 10-6, and 10-8 of each semiconductor memory element column in a bit line. B2 and inverted bit line I2 are connected (not shown). Further, the semiconductor memory device 14 is provided with a word line fixing circuit 25 that takes a logical product of the output from the row decoder 22 and the control signal MT for each semiconductor memory element column (for each address). The output of the word line fixing circuit 25 is connected to the gates of the N-type MOS transistors Q5 and Q6 (FIG. 1) of each semiconductor memory element column by the word lines W1 to W4. With this configuration, it is possible to prohibit the data read and write operations for each semiconductor memory element column. Furthermore, the semiconductor memory device 14
Is a match line precharge circuit 26 that detects a comparison and collation result between the data stored in each semiconductor memory element column and the comparison target data, and an address conversion circuit 27 that encodes the output of the match line precharge circuit 26 into an address. And have. The match line precharge circuit 26 is VDD
Power supply and four P-type M provided for each semiconductor memory element array
It is composed of an OS transistor and is connected to the drain of the N-type MOS transistor Q9 (FIG. 1) of each semiconductor memory element column by match lines M1 to M4. The match line precharge circuit 27 is provided with three OR gates connected to the match lines M1 to M4, and outputs a 3-bit address to the output terminal MAD by the charges on the match lines M1 to M4.

Next, referring to FIG. 3, the semiconductor memory device 1
The comparison and collation operation of No. 4 will be described. FIG. 3 shows control signals MT and P in the comparison and collation operation of the semiconductor memory device shown in FIG.
7 is a time chart showing changes over time of C, word lines, bit lines, inverted bit lines, and match lines. As shown in FIG. 3, in the first period, each semiconductor memory element 10-1
In order to prohibit the data read / write operation in 10-8, all the word lines W1 to W4 are set to L by setting the control signal MT to L. Further, by setting the control signal PC to L, the bit lines B1 and B2
The inverted bit lines I1 and I2 are set to L. As a result, regardless of the data stored in each of the semiconductor memory elements 10-1 to 10-8, each of the semiconductor memory elements 10-1 to 10-1
The gate of the N-type MOS transistor Q9 (FIG. 1) of 10-8 becomes L, and the discharge paths of the match lines M1 to M4 are cut off. Further, since the control signal PC is set to L,
In the match line precharge circuit 26, the match lines M1 to M4
The P-type MOS transistor that conducts between the power supply and the VDD power source is turned on, charges the match lines M1 to M4, and sets the match lines M1 to M4 to H.

Next, in the second period, the control signal PC
Is set to H, and the comparison target data is input in bit units from the input terminal DI (FIG. 2). That is, the bit line B1,
The corresponding bit value of the data is input to B2, and the inverted bit value of the corresponding bit value is input to the inverted bit lines I1 and I2. In the semiconductor memory device 14 of the present embodiment, the comparison target data can be input without performing the bit inversion process. That is, if the bit value of the input data is 1, H is set to the bit lines B1 and B2 and the inverted bit line I is set.
L is input to 1 and I2, and if the bit value is 0, L is input to the bit lines B1 and B2, and H is input to the inverted bit lines I1 and I2. Bit lines B1 and B2 and inverted bit lines I1 and I2
When the potential of is determined, all the semiconductor memory elements 10-1 to 10-1
In the comparison and collation circuit section 12 (FIG. 1) of 10-8, the comparison target data and the data stored in the memory cell are compared and collated, and the result is obtained for each semiconductor memory device 1.
It appears in the potential of the node N3 of 0-1 to 10-8. The comparison and collation operation in each of the semiconductor memory elements 10-1 to 10-8 is the same as that of the semiconductor memory element 10 of the first embodiment, and the description thereof will be omitted.

Next, the data comparing and collating operation in each semiconductor memory element array will be described. In the memory cell array 21,
The transistors Q9 in the semiconductor memory element array are connected to the same match lines M1 to M4 as described above. Therefore, when there is a mismatch in at least one semiconductor memory element, the potential of the node N3 of that semiconductor memory element becomes H, the N-type MOS transistor Q9 of that semiconductor memory element is turned on, and the discharge path of the match line is Conduct. Therefore, the potential of the match line becomes L. Also,
When all the semiconductor memory elements are matched, the potentials of the nodes N3 of all the semiconductor memory elements become L, the N-type MOS transistors Q9 of all the semiconductor memory elements are turned off, and the discharge paths of the match lines are turned off. . Therefore, the potential of the match line is held at H. In this way, only the match line of the semiconductor memory element row that stores the data that matches the comparison target data becomes H. Then, in the address conversion circuit 27, the values of the match lines M1 to M4 are input, encoded into a matching address, and a 3-bit address is output to the output terminal MAD. For example, when the data stored in the second semiconductor memory element row from the bottom and the comparison target data match, only the match line M2 becomes H, and the three OR gates in the address conversion circuit 27. From "010"
The address of is output.

As described above, according to the semiconductor memory device 14 of the present embodiment, the bit lines B1 and B2 and the inverted bit line I are processed without bit inversion processing of the comparison target data.
1, I2 can be input. In addition, this makes it possible to omit the arithmetic circuit, register, and the like required for the bit inversion process, and it is possible to downsize the semiconductor memory device.

<< Third Embodiment >> FIG. 4 is a circuit diagram showing a structure of a semiconductor memory device 15 according to a third embodiment of the present invention. In the configuration of the semiconductor memory device 15, the match line conversion circuit 3
Since the second embodiment is exactly the same as the second embodiment except that it is provided, the description thereof will be omitted. The difference from the second embodiment is that the comparison and collation result is not directly input to the address conversion circuit 27 through the match lines M1 to M4, but the comparison and comparison result is input to the address conversion circuit 27 through the match line conversion circuit 32. It is a point. That is, as shown in FIG. 4, the match line conversion circuit 32 includes the match line M1 for each semiconductor memory element column.
.. M4 and the negation of the potentials of the word lines W1 to W4. With this configuration, the semiconductor memory device 15 can input the data to be compared from the outside through the data input circuit 23, as in the second embodiment. Further, word data stored at a specific address designated by the input address signal AD can be used as comparison target data.

The comparison and collation operation when the word data stored at the specific address designated by the input address signal AD is the comparison target data will be described below with reference to FIG. FIG. 5 is a time chart showing changes with time of the control signals MT and PC, the word line, the bit line, the inverted bit line and the match line in the comparison and collation operation of the semiconductor memory device shown in FIG. In FIG. 5, the first period is a preparation period for the comparison and collation operation of the semiconductor memory device 15, and the second embodiment
The same operation as the first period in FIG. 3 in FIG. That is, all the word lines W1 to W4 are set to L by setting the control signal MT to L in order to prohibit the data read / write operation in each of the semiconductor memory elements 10-1 to 10-8. . Further, by setting the control signal PC to L, the bit lines B1 and B2 and the inverted bit lines I1 and I
2 is set to L. As a result, each semiconductor memory element 10
-1, regardless of the data stored in 10-8,
The gate of the N-type MOS transistor Q9 (FIG. 1) of each of the semiconductor memory elements 10-1 to 10-8 becomes L, and the match line M
The discharge paths 1 to M4 are cut off. Also, control signal PC
Is set to L, in the match line precharge circuit 26, the P-type MOS transistor that conducts between the match lines M1 to M4 and the VDD power supply is turned on to turn on the match line M.
1 to M4 are charged and the match lines M1 to M4 are set to H.

Next, in the second period, the control signal MT
To H. Input a specific address Address signal A
Input by D, and the corresponding word line is activated. For example, when the address "100" is input to the row decoder 22 (FIG. 4) by the input address signal AD, only the word line W4 becomes H and the semiconductor element 10 in the fourth semiconductor memory element column from the bottom in FIG. -7 and 10-8 (Fig. 1)
The respective N-type MOS transistors Q5 and Q6 are turned on to turn on the semiconductor elements 10-7 and 10-8, and the bit lines B1 and B.
2 and the inverted bit lines I1 and I2 are brought into conduction. Then, the bit lines B1 and B2 and the inverted bit lines I1 and I
2 is connected to the data output circuit 24 (FIG. 4) by the control signal WR, the semiconductor elements 10-7 and 10-
The word data stored in 8 is read from the output terminal DO as the comparison target data. Since the remaining word lines W1 to W3 are still set to L, the word data of the semiconductor memory element columns connected to these word lines W1 to W3 are not changed. After that, in all the semiconductor memory element arrays, the comparison target data and the stored word data are compared and collated.

The operation of comparing and collating data in all the semiconductor memory element columns is the same as that in the second period of FIG. 3 in the second embodiment. That is, in the memory cell array 21, the N-type MOS transistors Q9 in the semiconductor memory element column are the same match lines M1 to M as described above.
4 is connected. Therefore, when there is a mismatch in at least one semiconductor memory element, the potential of the node N3 of that semiconductor memory element becomes H, the N-type MOS transistor Q9 of the semiconductor memory element is turned on, and the discharge path of the match line concerned is changed. Conduct. Therefore, the potential of the match line becomes L. Further, when all the semiconductor memory elements are matched, the potentials of the nodes N3 of all the semiconductor memory elements become L, the N-type MOS transistors Q9 of all the semiconductor memory elements are turned off, and the discharge paths of the match lines are non-conductive. Becomes As a result, the potential of the match line is held at H.
In the present embodiment, the comparison target data is stored in the semiconductor memory element column referenced by the address “100”. Therefore, the match line M4 becomes H indicating a match. However, in the match line conversion circuit 32, the match line M4 is
The logical product operation of the negation of the word line W4 and the match line M4 is performed, and the result L is input to the address conversion circuit 27. That is, the match line M4 that stores the comparison target data
Can be output from the MAD, which is excluded in the address conversion circuit 32 and stores the data that matches the comparison target data among the semiconductor memory element columns connected to the remaining match lines M1 to M3.

As described above, according to the semiconductor memory device 15 of the present embodiment, the word data stored at the specific address is used as the comparison target data, and the comparison is made with the word data stored at the other addresses. can do.

Now, referring to FIG. 6, a description will be given of the comparison / retrieval process of the bit pattern of the termination code in the code processing system for image and audio data using the semiconductor memory device 15. FIG. 6 is an explanatory diagram for explaining the comparison search processing of the bit pattern of the termination code using the semiconductor memory device shown in FIG. It should be noted that in image and audio data, word data composed of a series of variable-length codes composed of codes in which the bit length of one code is variable is used. These codes are terminated with a word data termination code having a predetermined characteristic bit pattern. When decoding this variable-length code sequence, the end code is recognized and one variable-length code is extracted, so it is necessary to search the position of the end code. In the conventional example, a variable-length code sequence is input to a shift register or the like and sequentially compared with the bit pattern of the termination code, so that the end position of the code is determined by the number of cycles depending on the code length. It took several cycles. In the semiconductor memory device 15 of this embodiment, for example, a termination code is stored in the head address (“00000000”) of the memorial array 21 (FIG. 4), and a variable length code sequence whose code length is unknown is stored next to the head address. The data is stored in order starting from the address. In order to clarify the code length of this variable length code, the start address is designated as the comparison target address. As a result, word data "00110011" is output from the data output circuit 24, and this word data is used as comparison target data to perform comparison and collation with the word data stored in the memorial array 21. As a result, the matching address is output from the output terminal MAD of the address conversion circuit 27. This matching address is the end position of the input variable length code. As described above, by using the semiconductor memory device 15 of the present embodiment, it is possible to significantly reduce the time required for the comparison search process of bit patterns such as image and audio data.

[0032]

As described above, according to the semiconductor memory device of the present invention, the first node on the bit line side is used as the gate of the N-type MOS transistor on the inversion bit line side of the comparison and collation circuit section, and the inversion bit. The second node on the line side is connected to the gate of the N-type MOS transistor on the bit line side of the comparison / collation circuit section,
Each is connected. Therefore, the comparison target data can be input to the bit line and the inverted bit line without performing the bit inversion process. Furthermore, N of the above-mentioned comparison and matching circuit unit
Since almost no current flows through the gate of the MOS transistor, the semiconductor memory element can perform stable operation. In addition, when designing the semiconductor memory element, the amplification factors of the P-type and N-type MOS transistors can be easily determined without considering the current path formed between the basic circuit section and the comparison and verification circuit section.

According to the semiconductor memory device of the present invention, the comparison target data can be input to the bit line and the inverted bit line without performing the bit inversion process. In addition, this makes it possible to omit the arithmetic circuit, register, and the like required for the bit inversion process, and it is possible to downsize the semiconductor memory device.

According to the semiconductor memory device of the present invention,
By taking the logical product of the potential of the match line and the negation of the potential of the word line, the word data stored at a specific address is used as the comparison target data and compared and compared with the word data stored at other addresses. can do.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory element that is Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a semiconductor memory device that is Embodiment 2 of the present invention.

3 is a time chart showing changes over time of control signals MT and PC, a word line, a bit line, an inverted bit line, and a match line in the comparison and collation operation of the semiconductor memory device shown in FIG.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor memory device that is Embodiment 3 of the present invention.

5 is a time chart showing changes over time of control signals MT and PC, a word line, a bit line, an inverted bit line, and a match line in a comparison and collation operation of the semiconductor memory device shown in FIG.

6 is an explanatory diagram illustrating a comparison search process of a bit pattern of a termination code using the semiconductor memory device illustrated in FIG.

FIG. 7 is a circuit diagram showing a configuration of a conventional semiconductor memory element.

[Explanation of symbols]

Q1, Q3 P-type MOS transistor Q2, Q4, Q5, Q6, Q7, Q8 N-type MOS transistor N1 First node N2 Second node N3 Third node B, B1, B2 Bit line I, I1, I2 Inversion Bit line W, W1, W2, W3, W4 Word line M, M1, M2, M3, M4 Match line 10 Semiconductor memory element 11 Basic circuit section 12 Comparison and collation circuit section 14, 15 Semiconductor memory device 21 Memory cell array 23 Data input circuit 25 word line fixing circuit 26 match line precharge circuit 27 address conversion circuit 32 match line conversion circuit

Claims (3)

[Claims] 1. A bistable wherein the output of a first inverter is connected to the input of a second inverter by a first node and the output of a second inverter is connected to the input of a first inverter by a second node. A circuit, a first switch element connected to the first node and opening between an input of the second inverter and a bit line by a potential of a word line, and a first switch element connected to the second node, A basic circuit section that has a second switch element that opens between an input of the first inverter and an inverted bit line according to the potential of the word line, and stores the data in the bistable circuit; A third switch element that separates the line from the third node by the potential of the second node, and the third switch element between the inverted bit line and the third node by the potential of the first node. 4th switch element to open And a fifth switch element that separates between the match line and the ground line by the potential of the third node, and stores the data stored in the basic circuit section from the bit line and the inverted bit line. A semiconductor memory device comprising: a comparison / collation circuit unit for comparing input data. 2. A bistable wherein the output of a first inverter is connected to the input of a second inverter by a first node and the output of a second inverter is connected to the input of a first inverter by a second node. A circuit, a first switch element connected to the first node and opening between an input of the second inverter and a bit line by a potential of a word line, and a first switch element connected to the second node, A basic circuit section that has a second switch element that opens between an input of the first inverter and an inverted bit line according to the potential of the word line, and stores the data in the bistable circuit; A third switch element that separates the line from the third node by the potential of the second node, and the third switch element between the inverted bit line and the third node by the potential of the first node. 4th switch element to open And a fifth switch element that separates between the match line and the ground line by the potential of the third node, and stores the data stored in the basic circuit section from the bit line and the inverted bit line. A semiconductor memory device having a memory cell array having a plurality of semiconductor memory elements arranged in a predetermined array, the semiconductor memory device having a comparison / collation circuit section for comparing input data, wherein a potential of the word line is set to a predetermined potential. A word line fixing circuit to be set, and data for setting the potentials of the bit line and the inverted bit line to a predetermined potential in the first period and inputting data to the bit line and the inverted bit line in the second period. An input circuit, a match line precharge circuit that sets the match line to a predetermined potential during the first period, and an add that generates an address by encoding the potential of the match line during the second period. The semiconductor memory device characterized by comprising: a scan conversion circuit. 3. A match line conversion circuit for calculating a logical product of the potential of the match line and the negation of the potential of the word line and outputting the result of the logical product to the address conversion circuit. The semiconductor memory device according to claim 2.