JPH10134583A - Associative memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an associative memory with a function which can detect a soft error produced in the data stored in a memory cell. SOLUTION: In an associative memory which uses a memory cell 10 with a built-in comparison function by which the agreement between data inputted from the outside and data stored inside is detected, the data are held by doubled memory circuits and the agreement is detected by doubled comparison circuits. The identical data are stored in the 1st and 2nd memory circuits 11A and 11B. The 1st comparison circuit 12A detects the agreement between the data stored in the 1st memory circuit 11A and the data inputted from the outside and the 2nd comparison circuit 12B detects the agreement between the data stored in the 1st memory circuit 11A and the data stored in the 2nd memory circuit 11B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory and, more particularly, to an associative memory having a data coincidence detecting function, and more particularly to a technique effective for use in an associative memory used for a cache memory or the like.

[0002]

2. Description of the Related Art An associative memory is a memory in which, instead of accessing by designating an address, a part of stored content is designated and one or the rest of the stored content can be read. In a computer system, it is used for a cache memory, a table for address translation, and the like.

The associative memory is composed of two memory units, and a first memory unit stores data (data to be searched) to be compared with data (search data) inputted from the outside, and a second memory unit. The memory section stores data to be taken out when a match is found in the comparison in the first memory. The first memory unit has a comparison function of detecting coincidence between data input from the outside and data held therein, in addition to the original storage function of the memory for holding data. (Content Addressable Memory).

In a conventional CAM, a memory cell (CAM cell) having a built-in comparison function for detecting coincidence is used for each storage circuit holding data, and the data held in the storage circuit is read from outside without being read. There has been proposed a device configured to execute coincidence detection between data and data held in a storage circuit (Japanese Patent Laid-Open No. 59-231789). The conventional memory cell with a built-in comparison function has a disadvantage that the number of constituent elements of the cell increases because a data coincidence detection circuit including a plurality of logic gate circuits is provided for each memory cell. .

Accordingly, the present inventors have studied a memory cell having a built-in comparison function as shown in FIG. In the figure, 10 is a memory cell with a built-in comparison function, 11 is a storage circuit, 12 is a comparison circuit, WL1 is a word line, DL1-P and DL1-N are differential data lines, and HIT is a comparison output line. Storage circuit 11
Is a static storage element composed of general 6 MOSs, and data writing / reading is performed by the word line WL1 via the differential data lines DL1-P and DL1-N. The comparison circuit 12 implements EOR logic of two complementary data, detects a match between the data held in the storage circuit 1 and the data on the differential data lines DL1-P and DL1-N, and compares the result with a comparison output line. Output to HIT.

In order to store data in the memory cell and detect coincidence between data (search data) input from the outside and data (hold data) held in the memory cell, the comparison output line HIT is precharged in advance. Keep the word line W
Differential data line with storage circuit 11 not selected at L1
Enter search data into DL1-P and DL1-N. Then, the data held in the storage circuit 11 and the differential data line DL1-
A match with the search data of P and DL1-N is detected, and the result is output to the comparison output line HIT. That is, if a memory cell with a built-in comparison function is used, a match / mismatch can be detected without reading data held in the storage circuit.

[0007]

In the above-mentioned associative memory, the data held in the memory cell is output without reading out the data held in the memory cell when the match is determined, so that the data is held in the memory cell. There is a problem that even if a soft error occurs in data, it cannot be detected.

An object of the present invention is to provide an associative memory having a function of detecting a soft error generated in data held in a memory cell.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, in an associative memory using a memory cell having a built-in comparison function for detecting a match between externally input data and internally held data, the memory cell is matched with a storage circuit holding data. Are respectively duplicated, the same data is stored in the first and second storage circuits, and the first comparison circuit
And the second comparison circuit detects a match between the data held in the first storage circuit and the data held in the second storage circuit. It was made.

Storing the same data in the first and second storage circuits and detecting coincidence of the stored data with the second comparison circuit includes providing a parity bit in units of one bit,
This is equivalent to performing a parity check. Therefore, the second
The output of the comparison circuit of FIG.
By monitoring the output of the comparison circuit, the occurrence of a soft error can be detected without reading the data held in the storage circuit.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a memory cell having a built-in comparison function according to an embodiment of the present invention. In FIG. 1, 10 is a memory cell with a built-in comparison function, 11A and 11B are storage circuits,
12A and 12B are comparison circuits, WL1 is a word line, DL1-
P and DL1-N are differential data lines on the storage circuit 11A side, and HIT is a comparison output line on the storage circuit 11A side. DL10-P, DL
10-N is a differential data line on the storage circuit 11B side, PCK is a comparison output line on the storage circuit 11B side, and Qp1 and Qp2 are the above-mentioned comparison output lines.
The precharge MOSFETs SA1 and SA2 connected to one end of HIT and PCK respectively correspond to the comparison output line HI.
A sense circuit 13 is connected to the other ends of T and PCK, respectively. A soft error detection circuit 13 detects the presence or absence of a soft error based on the signals of the comparison output lines HIT and PCK.

The storage circuit 11A is connected to the differential data line
Transmission MOSFET with source / drain terminals connected to DL1-P and DL1-N and gate terminals connected to the above word line WL1
Q1 and Q2, and MOSFETs Q3 to Q6 forming a flip-flop type latch circuit. Qp
1, Qp2, Q3 and Q4 are P-channel MOSFETs,
The other is an N-channel MOSFET. The storage circuit 11
B has the same circuit configuration as the storage circuit 11A, the word line WL1 is common, and the differential data lines are provided independently of each other.

The comparison circuit 12A includes MOSFETs connected in series between a comparison output line HIT and a ground point.
Q11, Q12 and Q21, Q22. The gate terminal of Q11 is connected to the internal node NN of the storage circuit 11A.
The gate terminal of Q12 is connected to the differential data line DL1-P, the gate terminal of Q21 is connected to the internal node NP of the storage circuit 11A, and the gate terminal of Q22 is connected to the differential data line DL1-N. , The match / mismatch between the data held in the storage circuit 11A and the data on the differential data lines DL1-P and DL1-N is detected, and the result is output to the comparison output line HIT.

That is, the precharge MOSFET
When the comparison output line HIT is precharged by turning on Qp1 and the search data is placed on the differential data lines DL1-P and DL1-N, if the data matches the data held in the storage circuit 12A, the MOSFETs Q11, The MOSFETs of any pair of Q12 and Q21, Q22 are turned on at the same time, a current flows, and the charge on the comparison output line HIT is pulled out to a low level, which is amplified and detected by the sense circuit SA1.

If the search data on the differential data lines DL1-P and DL1-N do not match the data held in the storage circuit 12A, the MOSFETs Q11 and Q12 in series form and Q21 and Q22
Since any one of the MOSFETs of each pair is turned off, the charge of the comparison output line PCK is maintained at a high level without being extracted, and is amplified and detected by the sense circuit SA2. The sense circuits SA1 and SA2 only need to be able to detect the difference between the high level and the low level of the comparison output lines HIT and PCK, respectively, and may be configured by a simple circuit such as an inverter.

The comparison circuit 12B has the same circuit configuration as the comparison circuit 12A, and includes four MOSFETs Q11 ', Q12' and Q2.
1 'and Q22'. Comparison circuit 12B is different from comparison circuit 12A in that MOSFETs Q12 'and Q2
The only difference is that the gate terminal 2 'is connected not to the differential data lines DL1-P and DL1-N but to the internal nodes NP and NN of the storage circuit 11A. The gate terminal of the MOSFET Q11 'is connected to the internal node NN' of the storage circuit 11B.
The gate terminal 12 'is connected to the internal node N of the storage circuit 11B.
Connected to P '. As a result, the comparison circuit 12B detects a match / mismatch between the data held in the storage circuit 11A and the data held in the storage circuit 11B, and outputs the result (exclusive NOR logical value) to the comparison output line PCK.

That is, the precharge MOSFET
When the comparison circuit 12B is operated with Qp2 turned on to precharge the comparison output line PCK, when the data held in the memory circuit 12A and the data held in the memory circuit 12B match, the MOSFET Q11 'in the serial form is used. , Q12 'and Q2
Either pair of MOSFETs 1 'and Q22' are turned on at the same time, a current flows, and the charge on the comparison output line PCK is pulled out to a low level, and the sense circuit SA2
Is detected by

The search data on the differential data lines DL1-P and DL1-N, the data held in the storage circuit 12A, and the storage circuit 12B
If the stored data does not match the
MOS of each pair of SFETs Q11 ', Q12' and Q21 ', Q22'
Since one of the FETs is turned off, the comparison output line
The charge of PCK is maintained at a high level without being extracted, and is detected by a sense circuit SA2 (not shown). In this way,
A match / mismatch between the data held in the storage circuit 11A and the data held in the storage circuit 11B is detected, and the result is output to the comparison output line PCK.

Although not shown, the word line WL1
In addition, a plurality of memory cells with built-in comparison functions having the same configuration as described above are connected to the comparison output lines HIT and PCK to form one memory row, and even one data in one memory row does not match. If there is a memory cell, the comparison output lines HIT and PCK corresponding to that memory row become low level, and if data match in all the memory cells, the comparison output line HI
T and PCK are configured to be at a high level. Furthermore, a memory array such as a tag array is configured by providing a plurality of memory rows having the above configuration. The signal of the comparison output line HIT can be used as a word line selection signal of a data array in which original data is stored. As a result, after data match / mismatch determination, if the data match, immediately You can get the data you need.

When data is stored in the memory cell 10 of the embodiment shown in FIG. 1, the differential data lines DL1-P and DL1 are set in a state where the word line WL1 is at a selected level (high level) and the MOSFETs Q1 and Q2 are turned on. -N and differential data lines DL10-P, DL
The same data is loaded on 10-N and the same data is written into the storage circuits 11A and 11B. In order to detect a match / mismatch between data (search data) input from the outside and data (hold data) held in the memory cell, the word line WL is used.
1 as a non-selection level (low level)
The differential data lines DL1-
Enter search data in P, DL1-N.

Then, the comparison circuit 12A causes the storage circuit 11A
Match / mismatch between the held data of the data and the search data of the differential data lines DL1-P and DL1-N, and the result is compared with the comparison output line HIT.
Is output to At this time, another comparison circuit 12B detects a match / mismatch between the data held in the storage circuit 11A and the data held in the storage circuit 11B, and outputs the result to the comparison output line PCK. Therefore, the signal on the comparison output line PCK is compared with the signal on the comparison output line HIT to compare the signal on the comparison output line HIT.
If the comparison output line PCK is at a low level indicating a mismatch even though is at a high level indicating a match, it can be known that a data error has occurred in the memory cell. The soft error detection circuit 13 is a circuit for this purpose. For example, the soft error detection circuit 13 includes an inverter INV that inverts the level of the comparison output line PCK and an AND gate G1 that receives the signal inverted by the inverter and the signal of the comparison output line HIT as input signals. Can be configured.

In the above operation, storing the same data in the storage circuits 11A and 11B and detecting the coincidence of the stored data by the comparison circuit 12B is performed by providing a parity bit for each bit and performing a parity check. Is equivalent to Therefore, the signal on the comparison output line PCK is the output result of the parity check, and by monitoring the comparison output line PCK, the occurrence of a soft error can be detected. That is, the use of the memory cell of the present embodiment realizes a comparison function of detecting a match between data input from the outside and data held inside, and at the same time, detects a soft error occurring in the held data. Functions can also be realized. As a result, there is an advantage that it is not necessary to provide a circuit for checking the parity of the read data outside the memory array.

Further, in the memory cell of this embodiment, a comparison circuit added to realize a function of detecting a soft error generated in the held data is provided for comparing the data inputted from the outside with the data held inside. It has the same circuit configuration as the comparison circuit for realizing the comparison function for detecting coincidence, and the circuit for extracting the soft error detection signal output to the comparison output line is the same circuit as the circuit for extracting the coincidence detection signal. It can be configured. Therefore, the design is easy, an extra space is hardly generated in the layout, and a circuit for parity check is not required, so that an increase in chip size can be minimized.

Further, by preparing a memory cell for storing a parity bit in each memory row and storing a parity bit generated by an external parity generation circuit, an alpha memory is stored in a memory cell of a certain bit. If a soft error occurs due to a line or the like, a mismatch occurs between the parity of the data including the bit and the content of the parity bit. Since the parity bits do not match with each other, it is possible to prevent a signal (low level) from being output erroneously to match the data.

In the above embodiment, in order to prevent a through current from flowing through the comparison circuit in the memory cell at the time of precharging, for example, the MOSFET Q1 shown in FIG.
2, a MOSFET which is turned off at the time of precharging may be provided between Q22 and the ground point.

FIG. 2 shows a configuration example of a cache memory using the memory cell with a built-in comparison function. In the figure,
Reference numeral 20 denotes a tag array in which memory cells 10 with built-in comparison functions as shown in FIG. 1 are arranged in a matrix, and 30 denotes a data array in which original data is stored. Is connected to the word line WL2 of the data array 30 via the sense circuit SA, and a memory row in the data array 30 corresponding to the comparison output line HIT whose data is matched and set to the high level is selected and held. The read data is read. As the memory cell 31 forming the data array 30, for example, a static memory cell having the same circuit configuration as the storage circuits 11A and 11B of the memory cell 10 forming the tag array 20 is used.

In the cache memory of this embodiment, there is provided a NAND circuit G4 for calculating the logical product of all the comparison output lines HIT in the tag array 20, and when the data does not match in all the memory rows. ,
A signal indicating a mishit is output to the outside. When the external microprocessor receives the mishit signal, it determines that there is no desired data in the data array 30 and accesses a main memory (not shown) to read the desired data, or caches a block containing the data. The data can be transferred to a memory to replace a block.

Further, in the cache memory of this embodiment, there is provided an OR gate G5 for calculating the logical sum of the soft error detection circuit 13 provided for every memory row in the tag array 20. When a soft error in which the data held in the storage circuit 11A does not match the data held in the memory circuit 11B is detected in the memory row, a signal indicating the soft error is output to the outside. When the external microprocessor receives the soft error detection signal, it can execute processing such as rewriting of all the data in the cache memory to guarantee the reliability of the data.

In FIG. 2, reference numeral 21 denotes a tag array 2
This is a decoder that decodes an externally input address signal when writing data to 0 and the data array 30. G2 and G3 are the differential data lines DL1-P and DL1 when writing data to the memory cells 10 in the tag array 20.
-N, a logic gate for giving differential data to BFF1,
The BFF 2 is an output buffer that outputs read data of the data array 30 to the outside and an input buffer that takes in write data to the data array input from the outside and puts it on a data line.

As described above, in the above-described embodiment, the associative memory using the memory cell having the built-in comparison function for detecting the coincidence between the data input from the outside and the data held in the inside is described as follows. , A storage circuit for holding data and a comparison circuit for detecting coincidence are each configured to be duplicated, the same data is stored in the first and second storage circuits, and the first comparison circuit is a first storage circuit. And the second comparator detects the match between the data held in the first storage circuit and the data held in the second storage circuit. Monitoring the output of the second comparison circuit has the effect that the occurrence of a soft error can be detected without reading the data held in the storage circuit.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say. For example, in the embodiment, the comparison circuits 12A and 12B
ET only, but only P-channel MOSFET or P-channel MOSFET and N-channel MOS
It is also possible to configure a comparison circuit by combining with an FET.

In the above description, the case where the invention made by the inventor is mainly applied to the associative memory which is the background of the application has been described. However, the present invention is not limited to this, The present invention can be widely used for a semiconductor integrated circuit having a circuit for determining whether or not the stored data matches data stored in advance.

[0036]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, a comparison function for detecting a match between data input from the outside and data held inside is realized, and at the same time, a soft error generated in the data held in the memory cell is reduced. The function of detecting can also be realized, which has the effect of improving the reliability of the associative memory.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a memory cell with a built-in comparison function to which the present invention is applied.

FIG. 2 is a block diagram showing an embodiment of the entire associative memory using the memory cells of the embodiment.

FIG. 3 is a circuit diagram showing an example of a memory cell with a built-in comparison function studied prior to the present invention.

[Description of Signs] 10 Memory cell 11A, 11B Storage circuit 12A, 12B Comparison circuit 13 Soft error detection circuit WL1 word line DL1-P, DL1-N Differential data line DL10-P, DL10-N Differential data line HIT comparison Output line PCK comparison output line 20 Tag array 21 Address decoder 30 Data array 31 Memory cell

Claims (7)

[Claims] 1. An associative memory using a memory cell having a built-in comparison function for detecting a match between externally input data and internally held data, the memory cell being matched with a storage circuit holding data. , And the same data is stored in the first and second storage circuits, and the first comparison circuit receives the data held in the first storage circuit and externally input data. An associative memory configured to detect a match with the data, and the second comparison circuit is configured to detect a match between the data held in the first storage circuit and the data held in the second storage circuit. . 2. A data line for writing / reading data to / from the first storage circuit and the second storage circuit is independently provided, and a word line for controlling writing / reading is shared. 2. The associative memory according to claim 1, wherein 3. The first storage circuit and the second storage circuit have the same circuit configuration, and the first comparison circuit and the second comparison circuit have the same circuit configuration. 3. The associative memory according to claim 1, wherein 4. The memory device according to claim 1, wherein a plurality of memory cells including the first and second storage circuits and the first and second comparison circuits are connected to the word line. ,
4. The associative memory according to 2 or 3. 5. A first comparison circuit comprising a pair of MOS transistors connected in series between a first comparison output line and a power supply voltage terminal.
The gate terminal of one MOSFET is connected to a predetermined node in the first storage circuit, and the other is
The gate terminal of the SFET is connected to the corresponding data line, and the second comparison circuit includes a pair of M series connected in series between the second comparison output line and the power supply voltage terminal.
The gate terminal of one MOSFET is connected to a predetermined node in the first storage circuit, and the gate terminal of the other MOSFET is connected to a predetermined node in the second storage circuit. A signal indicating the match / mismatch between the data on the data line and the data held in the first storage circuit is output from the comparison output line, and the data held in the first storage circuit is output from the second comparison output line. 5. The associative memory according to claim 2, wherein a signal indicating match / mismatch with the data held in said second storage circuit is output. 6. A tag array for storing an address tag,
2. A cache memory comprising: a data array for storing data associated with the address tag;
A cache memory comprising the associative memory according to 2, 3, 4, or 5, as a tag array, wherein a corresponding word line in the data array is selected by a comparison output of the tag array. 7. A tag array for storing an address tag,
7. A cache memory comprising a data array for storing data associated with the address tag, wherein the content addressable memory according to claim 5 is provided as a tag array, and the data is output by comparison output from a first output line of the tag array. A cache memory configured to select a corresponding word line in the array and to output a signal indicating a soft error based on a comparison output from a first output line of the tag array. .